JP4645022B2 - Thin film transistor array substrate and active matrix liquid crystal display device - Google Patents

Description

  The present invention relates to a thin film transistor array substrate and an active matrix type liquid crystal display device, and more specifically, a thin film transistor array substrate using a thin film transistor as an active element for controlling a pixel, and an active device including the same. The present invention relates to a matrix type liquid crystal display device.

  In recent years, various display devices using a liquid crystal display device have been developed as a wall-mounted TV, a projection TV, or a display device for OA equipment. In particular, an active matrix liquid crystal display device using a thin film transistor, which is an active element, as a switching element has advantages such as that the contrast and response speed do not decrease even when the number of scanning lines is increased. It is influential in realizing devices and high-definition TV display devices. Further, when used as a light valve of a projection display device called a projector, there is an advantage that a large screen display can be easily obtained.

  In a liquid crystal display device for a light valve using a transmissive liquid crystal, light with high luminance is usually incident on a liquid crystal display device from a light source, and the transmission is controlled according to image information. That is, the transmission of incident light is controlled by switching the thin film transistor and applying an electric field to the liquid crystal layer for each pixel to change the orientation of the liquid crystal. The light that has passed through the liquid crystal display device is enlarged and projected on a screen via a projection optical system including a lens. In this case, the light source is disposed on the counter substrate side of the liquid crystal display device, and the projection optical system is disposed on the thin film transistor array substrate side of the liquid crystal display device.

  In a thin film transistor having an active layer made of amorphous silicon or polycrystalline silicon, when light is applied to a channel region or an LDD region, a light leakage current is generated by photoexcitation, which affects the characteristics of the thin film transistor. There's a problem. Here, the light incident on the active layer of the thin film transistor is not only the light from the light source but also once transmitted through the liquid crystal display device and reflected by the projection optical system, and again enters the liquid crystal display device from the back side of the liquid crystal display device. Incident light, that is, return light is included.

  In particular, the light valve liquid crystal display device uses high-intensity light, so that the intensity of light source light and return light incident on the liquid crystal display device is large, and the intensity of light incident on the active layer is also large. For this reason, a large light leakage current is generated. In recent years, projection-type display devices have been downsized and increased in brightness, and the intensity of light incident on the liquid crystal display device tends to increase further, so that the light leakage current further increases and the characteristics of the thin film transistor are improved. There was a problem that the effect was even greater.

  In order to suppress the light leakage current, generally in liquid crystal display devices, an upper light-shielding film that blocks light source light from entering the active layer and a back-surface light-shielding film that blocks return light from entering the active layer are each provided with an insulating film. And provided above and below the active layer. Here, in order to sufficiently reduce the light leakage current, it is necessary to sufficiently increase the light shielding areas of the upper light shielding film and the rear light shielding film. This is because when the light shielding area of the upper light shielding film and the rear light shielding film is small, light incident obliquely with respect to the normal direction of the substrate is between the rear light shielding film and the data line, the gate line, or the upper light shielding film. This is because, as a result of multiple reflections, the light easily enters the channel region or LDD region of the active layer. In addition, when a backside light shielding film or the like is electrically connected in parallel to the pixel electrode to constitute a storage capacitor, the storage capacity is increased by increasing the area of the backside light shielding film, thereby increasing the retention characteristics. And the influence of light leakage current can be reduced.

  However, when the light shielding area such as the upper light shielding film and the back light shielding film is increased in order to enhance the light shielding effect against multiple reflections, the area of the pixel opening region is relatively reduced. As a result, there is a problem that the brightness at the time of white display decreases and the contrast ratio decreases. Therefore, in order to obtain a liquid crystal display device having a large contrast ratio, it is necessary to keep the light shielding areas of the upper light shielding film and the rear light shielding film as small as possible.

  Patent Document 1 proposes a configuration in which a second back surface light-shielding film is provided between the back surface light-shielding film and the active layer. FIG. 17 shows a configuration of an example of a thin film transistor array substrate having a second back surface light-shielding film, and FIG. 18 shows a cross section taken along line XVIII-XVIII of FIG. In the thin film transistor array substrate 130, as shown in FIG. 17, the gate lines 109 and the data lines 122 are arranged orthogonally, and the thin film transistors are arranged at the intersections thereof.

As shown in FIG. 18, below the polycrystalline silicon layer 107 constituting the active layer, a first back surface light-shielding film 103 that is opposite to the polycrystalline silicon layer 107 and has substantially the same shape as the polycrystalline silicon layer 107 is provided. ing. The first backside light shielding film 103 is made of a material having low light transmittance such as tungsten silicide. In addition, a second back surface light-shielding film 105 having substantially the same shape as that of the first back surface light-shielding film 103 is provided between the polycrystalline silicon layer 107 and the first back surface light-shielding film 103. ing. The second back light shielding film 105 is made of a light-absorbing material such as amorphous silicon. An insulating film such as a silicon oxide film is interposed between the first back light shielding film 103 and the second back light shielding film 105 and between the second back light shielding film 105 and the polycrystalline silicon layer 107.
JP 2003-131261 A (FIGS. 1 and 2)

  According to Patent Document 1, the second backside light shielding film 105 having light absorption provided between the polycrystalline silicon layer 107 and the first backside light shielding film 103 is incident obliquely with respect to the normal direction of the substrate. Before the light reaches the channel region 107c and the LDD regions 107b and 107d by the multiple reflection between the first back surface light shielding film 103 and the data line 122, the light is incident on the second back surface light shielding film 105 having light absorption, Can be absorbed. Therefore, it is possible to reduce the light leakage current while keeping the area necessary for light shielding small. In this case, by reducing the distance between the second backside light-shielding film 105 and the polycrystalline silicon layer 107, that is, the film thickness d2 of the silicon oxide film 106, the light incident obliquely with respect to the substrate normal direction is more It is possible to efficiently enter and absorb the second back surface light shielding film 105.

  However, if the thickness of the silicon oxide film 106 is reduced and the second back surface light shielding film 105 and the channel region 107c and the LDD regions 107b and 107d of the polycrystalline silicon layer 107 are brought close to each other, the second back surface light shielding film 105 is formed. A back gate effect that acts as a gate electrode is generated for the channel region 107c and the LDD regions 107b and 107d, which causes a problem that characteristics of the thin film transistor are fluctuated. For this reason, it is necessary to keep the film thickness d2 of the insulating film interposed between the polycrystalline silicon layer 107 and the second back light shielding film 105 at a certain value or more, and the second back light shielding film 105 can reduce the light leakage current. There were limits.

  In view of the above, an object of the present invention is to provide a thin film transistor array substrate and an active matrix liquid crystal display device that simultaneously suppress fluctuations in characteristics of thin film transistors due to the back gate effect and light leakage current.

The thin film transistor array substrate according to the present invention that achieves the above object includes a light-transmitting substrate, a first back surface light-shielding film, a first interlayer film, and a second back surface light-shielding film that are sequentially formed on the light-transmitting substrate. And a thin film transistor having an active layer formed on the second interlayer film, wherein the first back surface light shielding film is formed at a position facing at least the active layer of the thin film transistor. the second back light-shielding film have a opening to a position opposed to at least a portion of the channel region of the active layer, the outer shape of the first back light shielding film and the second back light-shielding film, wherein It is characterized by overlapping with each other when viewed in a direction orthogonal to the light transmissive substrate . Alternatively, the thin film transistor array substrate according to the present invention includes a light transmissive substrate, a first back light shielding film, a first interlayer film, a second back light shielding film, and a first back light shielding film formed on the light transmissive substrate in sequence. Two interlayer films and a thin film transistor having an active layer formed on the second interlayer film, wherein the first back surface light-shielding film is formed at a position facing at least the active layer of the thin film transistor, When the second back surface light-shielding film has an opening at a position facing at least a part of the channel region of the active layer and the surface of the light transmissive substrate is used as a reference, The upper part is located above the upper surface of the active layer of the thin film transistor.

  An active matrix liquid crystal display device according to the present invention includes a thin film transistor array substrate according to the present invention, a counter substrate disposed opposite to the thin film transistor array substrate, and a space between the thin film transistor array substrate and the counter substrate. The liquid crystal layer is provided.

  According to the thin film transistor array substrate of the present invention, since the second back surface light shielding film has the opening at a position facing at least a part of the channel region of the active layer, the back gate for the channel region of the second back surface light shielding film. The effect can be reduced. In addition, the second back light shielding film around the opening can block light directed to the channel region of the active layer by multiple reflection between the first back light shielding film and the data line, gate line, or upper light shielding film. Therefore, the incidence of light on the channel region of the active layer can be suppressed and the light leakage current can be reduced. Variation in characteristics of the thin film transistor can be suppressed by the back gate effect and the reduction of the light leakage current.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the second back surface light-shielding film is formed of a light absorbing material. In this case, since the light incident on the second back surface light-shielding film is absorbed, the light traveling toward the channel region of the active layer can be effectively blocked. In the thin film transistor array substrate of the present invention, preferably, the second back surface light shielding film is made of impurity-doped silicon or a silicon-containing material.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the second back surface light shielding film is maintained at a constant potential. In the thin film transistor array substrate of the present invention, preferably, the second back surface light shielding film is continuously formed on the back surface of the thin film transistors arranged in the column or row direction. Alternatively, the first back surface light-shielding film and the drain region of the active layer can be electrically connected. In this case, a storage capacitor can be formed between the first backside light shielding film and the drain region of the active layer, and the capacitance value of the storage capacitor per unit area can be increased.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the outer shapes of the first back surface light-shielding film and the second back surface light-shielding film overlap each other when viewed in a direction orthogonal to the light transmissive substrate.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the thickness of the second interlayer film is 30 nm to 100 nm. When the thickness of the second interlayer film is 100 nm or less, the second backside light-shielding film can be formed near the active layer, and the light leakage current can be effectively reduced. Further, when a storage capacitor is formed between the drain region of the active layer and the second back surface light shielding film, the capacitance value can be sufficiently increased. When the thickness of the second interlayer film is 30 nm or more, an effect similar to the back gate effect by the second back surface light shielding film can be sufficiently suppressed.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the sum of the thickness of the first interlayer film and the thickness of the second interlayer film is 150 nm or more. The back gate effect can be sufficiently reduced.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, when the surface of the light transmissive substrate is used as a reference, the uppermost portion of the second back surface light shielding film is above the upper surface of the active layer of the thin film transistor. To position. In this case, in addition to the above-described light-shielding effect against multiple reflections, the light incident on the channel region of the active layer from a direction substantially parallel to the surface of the light-transmitting substrate is the first surface whose upper surface is located above the upper surface of the active layer. 2 can be blocked by the back surface light shielding film. Therefore, the light incident on the channel region of the active layer can be reduced, and the light leakage current can be further reduced.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the opening overlaps with a position where the gate electrode of the thin film transistor and the active layer face each other when viewed in a direction orthogonal to the light transmissive substrate. Since there is no step due to the second back-surface light-shielding film on the gate line, the probability of wire breakage is reduced, and yield and reliability can be increased.

  In a preferred embodiment of the thin film transistor array substrate of the present invention, the distance between the end of the opening of the second backside light shielding film and the end of the source / drain region of the thin film transistor is the first interlayer film. And the sum of the thickness of the second interlayer film. Thereby, an effect similar to the back gate effect exerted on the channel region of the active layer from the direction substantially parallel to the surface of the light transmissive substrate by the second back surface light shielding film can be suppressed.

  According to the active matrix type liquid crystal display device according to the present invention, an active matrix type liquid crystal display device having the same effects as those of the thin film transistor array substrate according to the present invention can be obtained.

  Hereinafter, with reference to the drawings, the present invention will be described in more detail based on exemplary embodiments according to the present invention. 1 is a plan view showing a configuration of a thin film transistor array substrate according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing a cross section taken along line II-II of FIG. 1, and FIG. It is sectional drawing which shows the cross section along the III-III line of FIG. 1 to 3 show a thin film transistor corresponding to one pixel and its vicinity. In the thin film transistor array substrate 30, a plurality of pixels are arranged in a matrix, and are arranged opposite to a counter substrate having a counter electrode on the surface via a liquid crystal.

  The thin film transistor array substrate 30 includes a glass substrate 1 and a first silicon oxide film 2 formed on the glass substrate 1. The first silicon oxide film 2 is formed to prevent diffusion of heavy metals contained in the glass substrate 1.

  A first backside light shielding film 3 is formed on the first silicon oxide film 2. The first back surface light-shielding film 3 is formed between adjacent pixels, and includes a stripe-shaped first portion 3a extending along the row direction and a stripe-shaped second portion 3b extending along the column direction. It has a grid-like portion that intersects and a third portion 3 c formed below the contact hole 17, and is formed to face the polysilicon layer 7, the gate line 9, and the data line 12. . The first back surface light-shielding film 3 is made of, for example, tungsten silicide having light blocking properties. A second silicon oxide film 4 is formed so as to cover the first silicon oxide film 2 and the first back surface light shielding film 3.

  A second back surface light shielding film 5 is formed on the second silicon oxide film 4. The second back surface light shielding film 5 includes a first portion 5 a that faces the first portion 3 a of the first back surface light shielding film 3 and a second portion 5 b that faces the second portion 3 b of the first back surface light shielding film 3. The second backside light shielding film 5 is made of a light-absorbing material, such as amorphous silicon. In addition, the polycrystalline silicon layer 7 has an opening 19 that faces the channel region 7c and the LDD region 7b. The second back surface light-shielding film 5 is connected to a power supply line having a predetermined constant potential at the outer edge of the thin film transistor array substrate 7. A third silicon oxide film 6 is formed so as to cover the second silicon oxide film 4 and the second back light shielding film 5. The film thickness of the third silicon oxide film 6 is 30 nm to 300 nm.

  A polycrystalline silicon layer 7 is formed on the third silicon oxide film 6. The polycrystalline silicon layer 7 has a channel region 7c not doped with impurities, LDD regions 7b and 7d doped with low-concentration impurities, and a source region 7a and drain region 7e doped with high-concentration impurities. . The distance between the edge of the opening 19 of the second back surface light shielding film 5 and the channel region 7c or the LDD regions 7b and 7d is the film thickness d1 of the second silicon oxide film 4 and the film thickness d2 of the third silicon oxide film 6. And the sum (d1 + d2).

  A part of the drain region 7e extends along the second back surface light shielding film 5, and a part of the storage capacitor is formed by sandwiching the third silicon oxide film 6 between the drain region 7e and the second back surface light shielding film 5. is doing. Here, by forming the third silicon oxide film 6 as thin as 30 nm to 300 nm and forming the second back light-shielding film 5 near the polycrystalline silicon layer 7, the light leakage current can be reduced, The capacity value of the storage capacity can be increased. A gate oxide film 8 is formed covering the third silicon oxide film 6 and the polycrystalline silicon layer 7.

  On the gate insulating film 8, a gate line 9 made of a polycrystalline silicon film doped with an impurity, a silicide film, or the like is formed. The gate line 9 is formed passing over the channel region 7c and functions as a gate electrode of the thin film transistor. A first interlayer insulating film 10 is formed so as to cover the gate insulating film 8 and the gate line 9.

  A contact hole 11 that penetrates through the first interlayer insulating film 10 and the gate insulating film 8 and reaches the source region 7a is formed. A data line 12 made of a low resistance metal such as aluminum is formed continuously in the contact hole 11 and on the first interlayer insulating film 10. A second interlayer insulating film 13 is formed so as to cover the first interlayer insulating film 10 and the data line 12.

  An upper light shielding film 14 is formed on the second interlayer insulating film 13. The upper light shielding film 14 is formed in a lattice shape so as to cover the polycrystalline silicon layer 7 excluding the contact connection region 7f, the gate line 9, and the data line 12. The upper light shielding film 14 is also connected to a power supply line having a predetermined constant potential at the outer edge of the thin film transistor array substrate 30. A third interlayer insulating film 15 is formed so as to cover the second interlayer insulating film 13 and the upper light shielding film 14.

  A planarizing film 16 is formed on the third interlayer insulating film 15, and a pixel electrode 18 made of ITO (Indium Tin Oxide) is formed on the planarizing film 16. As shown in FIG. 3, the contact hole 17 that penetrates the planarizing film 16, the third interlayer insulating film 15, the second interlayer insulating film 13, the first interlayer insulating film 10, and the gate insulating film 8 and reaches the drain region 7e. Is formed. On the bottom and side walls of the contact hole 17, the pixel electrode 18 is formed continuously with the pixel electrode 18 formed on the planarizing film 16, thereby constituting a thin film transistor array substrate 30.

  When the thin film transistor array substrate 30 is used as a light valve of an active matrix type liquid crystal display device, as shown in FIG. Light L1 that is incident from the counter substrate 40 side and goes directly to the channel region 7c and the LDD regions 7b and 7d is blocked by the upper light shielding film 14. Part of the light L2 that is not blocked by the upper light shielding film 14 or the like passes through the thin film transistor array substrate 30. The other part L3 of the light not blocked by the upper light shielding film 14 and the like is reflected by the first back light shielding film 3, but is incident and absorbed by the second back light shielding film 5, so that the channel region 7c and the LDD Incidence to the regions 7b and 7d is blocked.

  A part of the light passing through the thin film transistor array substrate 30 is reflected by an optical system (not shown) provided on the back side of the thin film transistor array substrate 30 and enters the thin film transistor array substrate 30 as return light L4. Of the return light L4, the light directing toward the channel region 7c and the LDD regions 7b and 7d is blocked by the first back surface light shielding film 3. Further, since the light reflected by the gate line 9, the data line 12, and the upper light shielding film 14 and traveling toward the channel region 7c and the LDD regions 7b and 7d is incident on and absorbed by the second back surface light shielding film 5, the channel region 7c and the LDD. Incidence to the regions 7b and 7d is blocked.

  Here, although the opening portion 19 is provided in the second back surface light shielding film 5, most of the light traveling toward the channel region 7c and the LDD regions 7b and 7d is blocked by the second back surface light shielding film 5 around the opening portion 19. . Therefore, the incidence of light on the channel region 7c and the LDD regions 7b and 7d can be suppressed, and the light leakage current can be reduced. Further, the distance between the first back surface light-shielding film 3 and the polycrystalline silicon layer 7, that is, the sum (d1 + d2) of the film thickness d1 of the second silicon oxide film 4 and the film thickness d2 of the third silicon oxide film 6 is kept large. The channel region 7c and the LDD regions 7b, 7d are suppressed while reducing the back gate effect by reducing the distance between the second back surface light-shielding film 5 and the polycrystalline silicon layer 7, that is, the film thickness d2 of the third silicon oxide film 6. This effectively blocks light traveling toward the light source, thereby further reducing the light leakage current.

  FIG. 5 shows the measurement results of the light leakage current in the thin film transistor array substrate 30 of the present embodiment, the thin film transistor array substrate of Comparative Example 1, and the thin film transistor array substrate of Comparative Example 2. The thin film transistor array substrate of Comparative Example 1 has the same configuration as the thin film transistor array substrate 30 of the present embodiment except that the first back light shielding film 3 and the second back light shielding film 5 are not provided. The thin film transistor array substrate of Comparative Example 2 has the same configuration as the thin film transistor array substrate 30 of the present embodiment example, except that the second back surface light-shielding film 5 does not include the opening 19. In the figure, the data shown in graph (a) is the light leakage current of the thin film transistor array substrate of Comparative Example 1, the data shown in graph (b) is the light leakage current of the thin film transistor array substrate of Comparative Example 2, and the graph (c). The data shown in FIG. 6 respectively indicate the light leakage current of the thin film transistor array substrate 30 of the present embodiment.

  As can be understood from FIG. 5, in the thin film transistor array substrate 30 of the present embodiment, the light leakage current is significantly reduced as compared with the thin film transistor array substrate of the comparative example 1, and is approximately the same as the thin film transistor array substrate of the comparative example 2. It has been reduced to.

  FIG. 6 shows an insulating film thickness between the first backside light-shielding film 3 and the polycrystalline silicon layer 7, that is, the film thickness d1 of the second silicon oxide film 2 and the third oxidation in the thin film transistor array substrate 30 of the present embodiment. The result of measuring the relationship between the sum (d1 + d2) of the film thickness d2 of the silicon film 3 and the TFT leakage current due to the back gate voltage is shown. From the figure, when the insulating film thickness (d1 + d2) is 100 nm, the increase in the TFT leakage current due to the back gate voltage is large, and when the insulating film thickness is 200 nm, the increase in the TFT leakage current due to the back gate voltage can be suppressed. I understand that.

  Although the optimum value of the back gate voltage obtained by experiments is about 3 V, the bias condition depending on the back gate voltage of the thin film transistor differs depending on the video signal. Also, the optimum value of the back gate voltage varies depending on the writing of signals having different polarities for each frame. Therefore, when the insulating film thickness (d1 + d2) is thin, the TFT leakage current is significantly increased due to the back gate voltage. On the other hand, when the insulating film thickness (d1 + d2) is 200 nm, since the characteristics are included in a flat region, the problem of an increase in TFT leakage current due to the back gate voltage does not occur.

  In the present embodiment, the second backside light-shielding film 5 is reduced by reducing the film thickness d2 of the third silicon oxide film 5 so that the second backside light-shielding film 5 and the polycrystalline silicon layer 7 are sufficiently close to each other. And the capacitance value of the storage capacitor constituted by a part of the drain region 7e can be increased. As a result, the fluctuation of the holding potential due to the light leakage current can be suppressed.

  Further, the insulating film in which the distance between the edge of the opening 19 of the second back surface light-shielding film 5 and the channel region 7 c or the LDD regions 7 b and 7 d is interposed between the first back surface light-shielding film 3 and the polycrystalline silicon layer 7. By setting the film thickness to be larger than the film thickness, the back gate effect similar to the back gate effect exerted by the second back surface light shielding film 5 from the lateral direction of the channel region 7c or the LDD regions 7b and 7d can be suppressed.

  As described above, according to the present embodiment, the two effects of suppressing the light leakage current and increasing the storage capacity can be obtained, so that the fluctuation of the pixel potential can be sufficiently suppressed even when intense light is irradiated. I can do it.

  7A to 7C, 8D, and 8E are cross-sectional views showing respective manufacturing stages of the thin film transistor array substrate 30. FIG. First, as shown in FIG. 7A, a first silicon oxide film 2 is deposited on the surface of the glass substrate 1 by using a CVD (Chemical Vapor Deposition) method. Next, a tungsten silicide film (not shown) is formed on the first silicon oxide film 2, and the tungsten silicide film is patterned using a general photolithography technique and etching technique, thereby forming the first backside light shielding film 3. To do. Subsequently, a second silicon oxide film 4 is deposited on the first silicon oxide film 2 and the first back light-shielding film 3 by using the CVD method, and the first back light-shielding film 3 is covered with the second silicon oxide film 4.

  Next, an amorphous film (not shown) is formed on the second silicon oxide film 4 by using a low pressure chemical vapor deposition (LPCVD) method or a plasma chemical vapor deposition (PCVD) method. A silicon film is deposited, and the second backside light shielding film 5 is formed by patterning the amorphous silicon film using a photolithography technique and an etching technique.

  Next, as shown in FIG. 7B, a third silicon oxide film 6 is deposited on the second silicon oxide film 4 and the second back surface light shielding film 5 using the CVD method, and the second back surface light shielding film 5 is deposited. Is covered with a third silicon oxide film 6. Next, after depositing an amorphous silicon film (not shown) on the third silicon oxide film 6 using LPCVD, PCVD, or the like, the amorphous silicon film is crystallized using a laser annealing method or the like. Subsequently, the polycrystalline silicon layer 7 functioning as an active layer of the thin film transistor 31 is formed by patterning the crystallized amorphous silicon film using a photolithography technique and an etching technique.

  Next, as shown in FIG. 7C, a gate insulating film 8 made of a silicon oxide film is formed on the third silicon oxide film 6 and the polycrystalline silicon layer 7 by using the CVD method, and a polycrystalline silicon layer is formed. 7 is covered with a gate insulating film 8. Next, a polysilicon film (not shown) doped with impurities and a silicide film (not shown) are sequentially formed on the gate insulating film 8. Subsequently, the gate line 9 is formed by patterning the stacked polycrystalline silicon film and silicide film using a photolithography technique and an etching technique.

  Next, the polycrystalline silicon layer 7 is selectively doped with low-concentration impurities using the gate line 9 as a mask. Next, the polycrystalline silicon layer 7 is selectively doped with high-concentration impurities using a patterned photoresist film (not shown) as a mask. As a result, the source region 7a, the LDD regions 7b and 7d, the channel region 7c, and the drain region 7e can be formed in the polycrystalline silicon layer 7, respectively.

  Next, as shown in FIG. 8D, a first interlayer insulating film 10 made of a silicon oxide film is formed on the gate insulating film 8 and the gate line 9 by using the CVD method, and the gate line 9 is formed into the first line. Cover with an interlayer insulating film 10. Next, the first interlayer insulating film 10 and the gate insulating film 8 are selectively removed using a photolithography technique and an etching technique, and a contact hole 11 exposing the source region 7a is formed. Subsequently, an aluminum film (not shown) is deposited on the first interlayer insulating film 10 by a sputtering method or the like, and the data line 12 is formed by patterning the aluminum film using a photolithography technique and an etching technique. The data line 12 is also formed inside the contact hole 11 and is electrically connected to the source region 7a.

  Next, as shown in FIG. 8E, a second interlayer insulating film 13 made of a silicon oxide film is formed on the first interlayer insulating film 10 and the data line 12 by using the CVD method, and the data line 12 is Cover with a second interlayer insulating film 13. Next, a chromium film (not shown) is deposited on the second interlayer insulating film 13 by sputtering or the like, and the chromium film is patterned using a photolithography technique and an etching technique to form the upper light shielding film 14. Next, a third interlayer insulating film 15 made of a silicon oxide film is deposited on the second interlayer insulating film 13 and the upper light shielding film 14 by CVD, and the upper light shielding film 14 is covered with the third interlayer insulating film 15. . Subsequently, a planarizing film 16 is formed on the third interlayer insulating film 15 using a coating method.

  Next, the planarization film 16, the third interlayer insulating film 15, the second interlayer insulating film 13, the first interlayer insulating film 10, and the gate insulating film 8 are selectively removed by using a photolithography technique and an etching technique. A contact hole 17 exposing the drain region 7e is formed. Next, an ITO film is formed on the planarizing film 16, and the pixel electrode 18 is formed by patterning the ITO film using a photolithography technique and an etching technique. The pixel electrode 18 is also formed inside the contact hole 17 and is electrically connected to the drain region 7e. Through the above process, the thin film transistor array substrate 30 of the present embodiment shown in FIGS. 1 to 3 is obtained.

  FIG. 9 is a plan view showing the configuration of the thin film transistor array substrate 31 according to the second embodiment of the present invention, and FIG. 10 is a cross-sectional view showing a cross section taken along line XX of FIG. In the thin film transistor array substrate 31 of the present embodiment example, the first back surface light-shielding film 3 formed in a lattice shape in the thin film transistor array substrate 30 of the first embodiment example is formed in an island shape by being separated pixel by pixel. . Further, a contact hole 22 is provided from the lower surface of the drain region 7 e so as to penetrate the third silicon oxide film 6 and the second silicon oxide film 4 and reach the first back surface light shielding film 3. A contact made of polycrystalline silicon is provided in the contact hole 22 so as to be continuous with the polycrystalline silicon constituting the drain region 7e and connected to the first backside light-shielding film 3, and the first backside light-shielding film 3 and the drain region 7e. And are electrically connected. The second back surface light-shielding film 5 is not formed in a region where the contact hole 22 is provided and a region in the vicinity thereof. The thin film transistor array substrate 31 of the present embodiment has the same configuration as the thin film transistor array substrate 30 of the first embodiment except for the above. In these drawings, the same reference numerals are given to portions having the same configuration as the thin film transistor array substrate 30 of the first embodiment shown in FIGS.

  According to the thin film transistor array substrate of the present embodiment, accumulation also occurs between the second back surface light-shielding film 5 connected to a constant potential and the first back surface light-shielding film 3 that is separated in pixel units and formed in an island shape. Capacitance can be configured, and the capacity value of the storage capacity per unit area can be increased. Therefore, as compared with the thin film transistor array substrate 30 of the first embodiment, the fluctuation of the pixel potential can be further reduced, and the area necessary for securing a predetermined storage capacity can be further reduced.

  In this embodiment, the contact between the drain region 7e and the first back surface light-shielding film 3 is made by providing a contact hole 22 that penetrates directly from the bottom surface of the drain region 7e to the top surface of the first back surface light-shielding film 3. However, the drain region 7e and the first back surface light-shielding film 3 are respectively extended in a region not facing the data line 12, and a contact hole is provided in the extended region, whereby the drain region 7e and the first back surface light-shielding film 3 are provided. You may connect with.

  FIGS. 11A to 11C, 12D, and 12E are cross-sectional views showing respective manufacturing stages of the thin film transistor array substrate 31 according to the second embodiment. First, as shown in FIG. 11A, a first silicon oxide film 2 is deposited on the surface of the glass substrate 1 by using a general CVD method. Next, a tungsten silicide film (not shown) is deposited on the first silicon oxide film 2, and the tungsten silicide film is patterned by using a general photolithography technique and etching technique, so that island-shaped first islands separated in pixel units are obtained. 1 The back surface light-shielding film 3 is formed. Subsequently, a second silicon oxide film 4 is deposited on the first silicon oxide film 2 and the first back light-shielding film 3 by using the CVD method, and the first back light-shielding film 3 is covered with the second silicon oxide film 4.

  Next, an amorphous silicon film (not shown) is deposited on the second silicon oxide film 4 by using a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method, and an amorphous silicon film is formed by using a photolithography technique and an etching technique. By patterning the silicon film, a substantially lattice-shaped second back surface light-shielding film 5 is formed.

  Next, as shown in FIG. 11B, a third silicon oxide film 6 is deposited on the second silicon oxide film 4 and the second back light-shielding film 5 by using the CVD method, and the second back light-shielding film 5 is deposited. Is covered with a third silicon oxide film 6. Subsequently, the third silicon film 6 and the second silicon oxide film 4 are selectively removed by using a photolithography technique and an etching technique to form a contact hole 22 through which the first backside light shielding film 3 is exposed.

  Next, after depositing an amorphous silicon film (not shown) on the third silicon oxide film 6 using LPCVD, PCVD, or the like, the amorphous silicon film is crystallized using a laser annealing method or the like. Subsequently, the polycrystalline silicon layer 7 functioning as an active layer of the thin film transistor 31 is formed on the second silicon oxide film 4 by patterning the crystallized amorphous silicon film using a photolithography technique and an etching technique. . The polycrystalline silicon layer 7 is also formed inside the contact hole 22 and is electrically connected to the first back surface light shielding film 3.

  Next, as shown in FIG. 11C, a gate insulating film 8 made of a silicon oxide film is formed on the third silicon oxide film 6 and the polycrystalline silicon layer 7 by using the CVD method, and a polycrystalline silicon layer is formed. 7 is covered with a gate insulating film 8. Subsequently, a polycrystalline silicon film doped with impurities (not shown) and a silicide film are sequentially deposited on the gate insulating film 8 to form a laminated film, and this laminated film is then formed by using a photolithography technique and an etching technique. The gate line 9 is formed by patterning.

  Next, the polycrystalline silicon layer 7 is selectively doped with low-concentration impurities using the gate line 9 as a mask. Next, the polycrystalline silicon layer 7 is selectively doped with high-concentration impurities using a patterned photoresist film (not shown) as a mask. Thereby, the source region 7a, the LDD regions 7b and 7d, the channel region 7c, and the drain region can be formed in the polycrystalline silicon layer 7.

  Next, as shown in FIG. 12D, a first interlayer insulating film 10 made of a silicon oxide film is formed on the gate insulating film 8 and the gate line 9 by using the CVD method, and the gate line 9 is formed into the first line. Cover with an interlayer insulating film 10. Next, the first interlayer insulating film 10 and the gate insulating film 8 are selectively removed using a photolithography technique and an etching technique to form a contact hole 11 exposing the source region 7a. Subsequently, an aluminum film (not shown) is formed on the first interlayer insulating film 10 by using a sputtering method or the like, and the data line 12 is formed by patterning the aluminum film by using a photolithography technique and an etching technique. The data line 12 is also formed inside the contact hole 11 and is electrically connected to the source region 7a.

  Next, as shown in FIG. 12E, a second interlayer insulating film 13 made of a silicon oxide film is formed on the first interlayer insulating film 10 and the data line 12 by the CVD method, and the data line 12 is connected to the second interlayer insulating film. Cover with an insulating film 13. Next, a chromium film (not shown) is deposited on the second interlayer insulating film 13 by sputtering or the like, and the chromium film is patterned by using a photolithography technique and an etching technique to form the upper light shielding film 14. . Subsequently, a third interlayer insulating film 15 made of a silicon oxide film is deposited on the second interlayer insulating film 13 and the upper light shielding film 14 by using the CVD method, and the upper light shielding film 14 is formed by the third interlayer insulating film 15. cover. Subsequently, a planarizing film 16 is formed on the third interlayer insulating film 15 using a coating method.

  Next, the planarization film 16, the third interlayer insulating film 15, the second interlayer insulating film 13, the first interlayer insulating film 10, and the gate insulating film 8 are selectively removed by a photolithography technique and an etching technique, and the drain A contact hole 17 shown in FIG. 9 is formed to expose the region 7e. Next, an ITO film is formed on the planarization film 16, and the ITO film is patterned by using a photolithography technique and an etching technique to form a pixel electrode (not shown). The pixel electrode is also formed inside the contact hole 17 and is electrically connected to the drain region 7e. Through the above-described steps, the thin film transistor array substrate 31 of the present embodiment shown in FIGS. 9 and 10 is obtained.

  FIG. 13 is a plan view showing a configuration of a thin film transistor array substrate according to a third embodiment of the present invention, and FIG. 14 is a cross-sectional view showing a cross section taken along line XIV-XIV in FIG. In the thin film transistor array substrate 32 of the present embodiment example, the opening 20 of the second back surface light-shielding film 5 faces the polycrystalline silicon layer 7 except for the contact connection region 7f. Further, the first portion 5a and the second portion 5b of the second back surface light-shielding film 5 are formed to the inside of the pixel opening region than the first portion 3a and the second portion 3b of the first back surface light-shielding film 3, respectively. Further, the film thickness of the second back surface light-shielding film 5 is set so that the upper surface of the second back surface light-shielding film 5 is above the upper surfaces of the channel region 7c and the LDD regions 7b and 7d with reference to the surface of the glass substrate 1. Has been. The thin film transistor array substrate 32 of the present embodiment has the same configuration as the thin film transistor array substrate 30 of the first embodiment except for the above. In these drawings, the same reference numerals are given to portions having the same configuration as the thin film transistor array substrate 30 of the first embodiment shown in FIGS.

  According to the thin film transistor array substrate 32 of the present embodiment example, light incident on the channel region 7c and the LDD regions 7b and 7d in a direction parallel to the surface of the glass substrate 1 is blocked by the second back surface light shielding film 5. The channel region 7c and the LDD regions 7b and 7d cannot be reached. As described above, the light traveling toward the channel region 7c and the LDD regions 7b and 7d is also efficiently blocked by the second back surface light-shielding film 5 due to refraction and reflection in the multilayer film constituting the thin film transistor array substrate 32, and is light-absorbing. Are absorbed by the second back surface light-shielding film 5. Accordingly, since the amount of light reaching the channel region 7c and the LDD regions 7b and 7d is extremely small, the light leakage current can be suppressed to a very low level. Further, the back gate effect can be suppressed by sufficiently increasing the distance between the channel region 7c and the LDD regions 7b and 7d and the edge of the opening 20 in the first back surface light shielding film 3 and the second back surface light shielding film 5. I can do it. By these, the fluctuation | variation of the characteristic of a thin-film transistor can be suppressed.

  A method for manufacturing the thin film transistor array substrate 32 will be described. The manufacturing method of the thin film transistor array substrate 32 of the present embodiment is the same as the manufacturing method of the thin film transistor array substrate 30 of the first embodiment described with reference to FIGS. 7 and 8 except for the following points. is there.

  That is, in the process shown in FIG. 7A, the thickness of the first backside light-shielding film 3 is 200 nm, the thickness of the second silicon oxide film 4 is 300 nm, and the thickness of the second backside light-shielding film 5 is 400 nm. To form each. When patterning the second back surface light shielding film 5, the inner region in the pixel opening region and the region facing the polycrystalline silicon layer 7 excluding the contact connection region 7f are removed. Further, if the side surface of the second back surface light-shielding film 5 is tapered, the coverage of the upper layer can be improved. In the step shown in FIG. 7B, the third silicon oxide film 6 is formed to a thickness of 100 nm, and the polycrystalline silicon layer 7 is formed to a thickness of 50 nm.

  In the thin film transistor array substrate 32 of the present embodiment, the second back surface light-shielding film 5 and the first back surface light-shielding film 3 partially overlap each other, so that the second back surface is based on the surface of the first silicon oxide film 2. The top of the light shielding film 5, that is, the height of the upper surface is 200 nm + 300 nm + 400 nm = 900 nm. On the other hand, the height of the upper surface of the channel region 7 c is 200 nm + 300 nm + 100 nm + 50 nm = 650 nm, which is lower than the upper surface of the second back surface light shielding film 5. For this reason, the polycrystalline silicon layer 7 is completely shielded from light incident on the polycrystalline silicon layer 7 in the horizontal direction, that is, in the direction parallel to the surface of the glass substrate 1.

  In the present embodiment, the second back surface light-shielding film 5 and the first back surface light-shielding film 3 are formed so as to partially overlap each other. Also in this case, the film thickness of each layer constituting the thin film transistor array substrate is preferably set so that the uppermost portion of the second back surface light-shielding film 5 is located above the channel region 7c and the LDD regions 7b and d. If the thickness of the second silicon oxide film 4, the second back surface light shielding film 5, the third silicon oxide film 6, and the polycrystalline silicon layer 7 in the thin film transistor array substrate 32 of this embodiment is set, the first back surface light shielding film. 3 and the second back surface light-shielding film 5 do not overlap with each other, the uppermost height of the second back surface light-shielding film 5 is (300 + 400) = 700 nm, and the heights of the upper surfaces of the channel region 7c and the LDD regions 7b and 7d Is 650 nm, the uppermost portion of the second back surface light-shielding film 5 is located above the channel region 7c and the LDD regions 7b and 7d.

  In this embodiment, the opening 20 of the second back surface light-shielding film 5 is opposed to all the regions of the polycrystalline silicon layer 7 except the contact connection region 7f. Since 20 faces at least the channel region 7c and the LDD regions 7b and 7d, the effect of the present invention can be obtained. Further, the same effect can be obtained by using amorphous silicon instead of amorphous silicon as the material of the second back surface light shielding film 5.

  FIG. 15 is a plan view showing a configuration of a thin film transistor array substrate according to the fourth embodiment of the present invention, and FIG. 16 is a cross-sectional view showing a cross section taken along line XVI-XVI of FIG. In the thin film transistor array substrate 33 of the present embodiment example, the opening 21 of the second back surface light-shielding film 5 is formed on the gate line 9 in addition to the region of the opening 20 of the second back surface light-shielding film 5 in the third embodiment example. The structure is the same as that of the thin film transistor array substrate 32 of the third embodiment except that it includes regions that face each other.

  In the thin film transistor array substrate 32 of the third embodiment, a step is generated in the wiring such as the gate line 9 formed above the second back surface light-shielding film 5 having a large film thickness, so that the reliability of the wiring may be lowered. There is. According to the thin film transistor array substrate 33 of the present embodiment example, since the opening 21 includes a region facing the gate line 9, a step due to the second back surface light shielding film 5 does not occur in the gate line 9. Probability is reduced, yield and reliability can be increased. Thus, according to the thin film transistor array substrate 33 of the present embodiment, high reliability can be obtained in addition to the effects of the thin film transistor array substrate 32 of the third embodiment.

  The manufacturing method of the thin film transistor array substrate 33 according to the present embodiment is the same as that according to the third embodiment except that the region facing the gate line 9 is further removed when the second back surface light-shielding film 5 is patterned. This is the same as the manufacturing method of the thin film transistor array substrate 32. In the present embodiment example, the second back surface light-shielding film 5 is also removed in the region 23 that is continuous with the gate electrode portion in the gate line 9, but the effect of the present embodiment example can be obtained without removing it. I can do it.

  As described above, the present invention has been described based on the preferred embodiment. However, the thin film transistor array substrate and the active matrix liquid crystal display device according to the present invention are not limited to the configuration of the above-described embodiment. A thin film transistor array substrate and an active matrix type liquid crystal display device which are variously modified and changed from the configuration of the embodiment are also included in the scope of the present invention. The thin film transistor array substrate and the active matrix liquid crystal display device according to the present invention can be suitably configured as a light valve.

It is a top view which shows the structure of the thin-film transistor array substrate of the example of 1st Embodiment. It is sectional drawing which shows the cross section along the II-II line | wire of FIG. It is sectional drawing which shows the cross section along the III-III line of FIG. It is sectional drawing which shows the function of the thin-film transistor array substrate which concerns on the example of 1st Embodiment. It is a graph which shows each the optical leakage current in the example of 1st Embodiment, and the conventional thin-film transistor array substrate. It is a graph which shows the relationship between the back gate voltage and TFT leak current in the first embodiment and the conventional thin film transistor array substrate. 7A to 7C are cross-sectional views showing respective stages of manufacturing the thin film transistor array substrate according to the first embodiment. FIGS. 8D and 8E are cross-sectional views showing respective manufacturing steps subsequent to FIG. 7 of the thin film transistor array substrate according to the first embodiment. It is a top view which shows the structure of the thin-film transistor array substrate which concerns on the example of 2nd Embodiment. It is sectional drawing which shows the cross section along XX of FIG. FIGS. 11A to 11C are cross-sectional views showing respective stages of manufacturing the thin film transistor array substrate according to the second embodiment. 12D and 12E are cross-sectional views showing respective manufacturing steps subsequent to FIG. 11 of the thin film transistor array substrate according to the second embodiment. It is a top view which shows the structure of the thin-film transistor array substrate which concerns on the example of 3rd Embodiment. It is sectional drawing which shows the cross section along the XIV-XIV line | wire of FIG. It is a top view which shows the structure of the thin-film transistor array substrate which concerns on the example of 4th Embodiment. It is sectional drawing which shows the cross section along the XVI-XVI line | wire of FIG. It is a top view which shows the structure of an example of the thin-film transistor array board | substrate which has a 2nd lower light shielding film. It is sectional drawing which shows the cross section along the XVIII-XVIII line of FIG.

Explanation of symbols

1: glass substrate 2: first silicon oxide film 3: first back light shielding film 3a: first part 3b: second part 3c: third part 4: second silicon oxide film 5: second back light shielding film 5a: first 1 part 5b: second part 6: third silicon oxide film 7: polycrystalline silicon film 7a: source region 7b, 7d: LDD region 7c: channel region 7e: drain region 7f: contact connection region 8: gate insulating film 9: Gate line 10: First interlayer insulating film 11: Contact hole 12: Data line 13: Second interlayer insulating film 14: Upper light shielding film 15: Third interlayer insulating film 16: Planarizing film 17: Contact hole 18: Pixel electrode 19 , 20, 21: opening (of the second lower light shielding film) 22: contact hole 23: region continuous with the gate electrode portion (in the gate line) 30, 31, 32, 33, 130: Thin film transistor array substrate

Claims (5)

A light-transmitting substrate, a first backside light-shielding film, a first interlayer film, a second backside light-shielding film and a second interlayer film, which are sequentially formed on the light-transmitting substrate, and the second interlayer A thin film transistor having an active layer formed on the film, wherein the first back light shielding film is formed at a position facing at least the active layer of the thin film transistor, and the second back light shielding film is a channel of the active layer. possess an opening at a position facing at least a portion of the region, the outer shape of the first back light shielding film and the second back light shielding film, overlap each other as viewed in the direction perpendicular to the light transmitting substrate, A thin film transistor array substrate.   The thin film transistor array substrate according to claim 1, wherein the second back surface light shielding film is formed of a light absorbing material.   The thin film transistor array substrate according to claim 2, wherein the second back surface light shielding film is made of impurity-doped silicon or a silicon-containing material. A light-transmitting substrate, a first backside light-shielding film, a first interlayer film, a second backside light-shielding film and a second interlayer film, which are sequentially formed on the light-transmitting substrate, and the second interlayer A thin film transistor having an active layer formed on the film, wherein the first back light shielding film is formed at a position facing at least the active layer of the thin film transistor, and the second back light shielding film is a channel of the active layer. An opening is provided at a position facing at least a part of the region, and the uppermost portion of the second back light-shielding film is above the upper surface of the active layer of the thin film transistor when the surface of the light transmissive substrate is used as a reference. A thin film transistor array substrate , wherein the thin film transistor array substrate is located on the substrate. A thin film transistor array substrate according to any one of claims 1-4, a liquid crystal layer sealed between the counter substrate arranged to face the thin film transistor array substrate, and the counter substrate and the thin film transistor array substrate An active matrix liquid crystal display device comprising:

Images