JP3767696B2 - Thin film transistor array substrate and active matrix liquid crystal display device - Google Patents

Description

  The present invention relates to a thin film transistor array substrate (hereinafter also referred to as a TFT array substrate) having a plurality of thin film transistors (hereinafter also referred to as TFTs) arranged in a matrix, and an active matrix including the same. The present invention relates to a liquid crystal display device. This liquid crystal display device can be suitably used as a light valve of a projection display device.

  In recent years, various display devices using a liquid crystal display device have been developed as a display device for a wall-mounted TV (Television), a projection TV, or an OA (Office Automation) device. In particular, an active matrix type liquid crystal display device using an active element TFT as a switching element has the advantage that the contrast and response speed do not decrease even if the number of scanning lines is increased. It is influential in realizing devices and high-definition TV display devices. Further, when used as a light valve of a projection display device called a projector, there is an advantage that a large screen display can be easily obtained.

  Usually, in a light valve liquid crystal display device, high-intensity light is incident on a liquid crystal display device from a light source, and the incident light is controlled according to image information when passing through the liquid crystal display device. That is, the intensity of transmitted light is adjusted by changing the transmittance of each pixel by applying an electric field to the liquid crystal layer for each pixel while switching the TFT. Then, the light passing through the liquid crystal display device is enlarged and projected through a projection optical system constituted by a lens or the like.

  The light source is arranged on the counter substrate side of the liquid crystal display device, and the optical system is arranged on the TFT array substrate side of the liquid crystal display device. Therefore, not only light from the light source but also light reflected by the projection optical system is incident on the liquid crystal display device.

  In an active matrix liquid crystal display device, a semiconductor layer such as amorphous silicon or polycrystalline silicon is used as an active layer of a TFT. When this active layer is irradiated with light, a leakage current ( That is, light leakage current) occurs. As described above, in the liquid crystal display device for a light valve, light with a high luminance is incident, so that the generated light leakage current is also increased. Furthermore, since the reflected light from the projection optical system is also applied to the active layer of the TFT, the light leakage current is further increased. In recent years, the projection type display device has been reduced in size and increased in brightness, and the brightness of light incident on the liquid crystal display device tends to increase, so this problem has become more serious.

  Therefore, conventionally, in the active matrix type liquid crystal display device for a light valve, a light-shielding film for preventing light irradiation to the active layer of the TFT is provided.

  23 and 24 show a schematic configuration of the TFT array substrate 100 of this type of conventional liquid crystal display device. FIG. 23 is a plan view of the main part, and FIGS. 24A and 24B are cross-sectional views of the main part taken along lines GG and HH in FIG. Note that FIG. 23 and FIG. 24 show only the configuration for one pixel.

  The TFT array substrate 100 of FIGS. 23 and 24 includes a light-transmitting substrate 101 having a plurality of TFTs 131 arranged in a matrix.

A lower light shielding film 103 made of a tungsten silicide film or the like is formed on the substrate 101 with a silicon oxide (SiO ₂ ) film 102 interposed therebetween. The lower light-shielding film 103 has a stripe-like portion extending along the row direction of the matrix (X direction in FIG. 23) and a stripe-like shape extending along the column direction of the matrix (Y direction in FIG. 23). It has a grid-like planar shape formed by intersecting with the part. The entire lower light shielding film 103 is covered with a silicon oxide film 104 formed on the silicon oxide film 102.

  On the silicon oxide film 104, a plurality of polycrystalline silicon films 107 patterned in a substantially L shape are formed. The polycrystalline silicon film 107 functions as an active layer of the TFT 131.

  That is, each of the polycrystalline silicon films 107 has a channel region 107c that is not doped with impurities, LDD (Lightly Doped Drain) regions 107b and 107d that are doped with impurities at a low concentration, and impurities that are doped at a high concentration. A source region 107a and a drain region 107e are included. The source region 107a and the drain region 107e are formed with the channel region 107c interposed therebetween. The LDD region 107b is formed between the source region 107a and the channel region 107c, and the LDD region 107d is formed between the channel region 107c and the drain region 107e.

  The source region 107a, the LDD region 107b, the channel region 107c, the LDD region 107d, and the drain region 107e are arranged along the Y direction so as to overlap the lower light shielding film 103. A part of the drain region 107e extends along the X direction. Each of the polycrystalline silicon films 107 is covered with a gate insulating film 108 formed on the silicon oxide film 104.

  On the gate insulating film 108, a plurality of gate lines 109 made of an impurity-doped polycrystalline silicon film or silicide film are formed. The gate lines 109 are parallel to each other and all extend along the X direction. Each gate line 109 is disposed so as to overlap with the channel region 107 c of the TFT 131 belonging to the same row of the matrix, and functions as a gate electrode of the TFT 131. Each gate line 109 is covered with a first interlayer insulating film 110 formed on the gate insulating film 108.

  A plurality of data lines 111 made of an aluminum film or the like are formed on the first interlayer insulating film 110. These data lines 111 are parallel to each other, extend along the Y direction, and are arranged so as to overlap the polycrystalline silicon film 107 of the TFT 131 belonging to the same column of the matrix. The entire source region 107a, channel region 107c, and LDD regions 107b and 107d of each TFT 131 are covered with the corresponding data line 111. The drain region 107 e of each TFT 131 is partially covered with the corresponding data line 111. Each data line 111 is electrically connected to the source region 107a of the TFT 131 belonging to the same column of the matrix via a contact hole 121 penetrating the first interlayer insulating film 110 and the gate insulating film. Each data line 111 is covered with a second interlayer insulating film 112 formed on the first interlayer insulating film 110.

  On the second interlayer insulating film 112, a substantially lattice-shaped black matrix film 113 extending in each of the X direction and the Y direction is formed. The black matrix film 113 is disposed so as to overlap each gate line 109 and each data line 111 and covers the TFT 131. The black matrix film 113 is made of a chromium film or the like and functions as an upper light shielding film. The entire black matrix film 113 is covered with a third interlayer insulating film 114 formed on the second interlayer insulating film 112.

  A plurality of substantially rectangular pixel electrodes 115 are formed on the third interlayer insulating film 114. The pixel electrodes 115 are respectively disposed in a plurality of pixel regions 120 defined by the gate lines 109 and the data lines 111. Each pixel electrode 115 is electrically connected to the drain region 107e of the corresponding TFT 131 through a contact hole 122 that penetrates the third interlayer insulating film 114, the second interlayer insulating film 112, the first interlayer insulating film 110, and the gate insulating film 108. Connected.

  In the liquid crystal display device including the conventional TFT array substrate 100 having the above-described configuration, the black matrix film 113 receives light incident from the surface side of a counter substrate (not shown) disposed to face the TFT array substrate 100. Cut off. Further, the lower light shielding film 103 blocks light incident from the back side of the TFT array substrate 100.

  However, there is a problem that light incident from the back side of the TFT array substrate 100 cannot be sufficiently prevented from irradiating the LDD regions 107b and 107d and the channel region 107c of the TFT 131.

  That is, as shown in FIG. 25, the light L101 from the surface side of the counter substrate is blocked by the black matrix film 113 or passes through the TFT array substrate 100 without being reflected by the lower light shielding film 103. As such, the width of the black matrix film 113, the width of the lower light shielding film 103, the interval between the black matrix film 113 and the lower light shielding film 103, and the like are set. Further, the light L 102 traveling from the back surface side of the TFT array substrate 100 toward the lower light shielding film 103 is blocked by the lower light shielding film 103.

  However, as shown in FIG. 25, the light L103 directed from the back surface side of the TFT array substrate 100 toward the black matrix film 113 is reflected by the black matrix film 113 and then travels toward the lower light shielding film 103 and the lower light shielding film 103 and the data line. The LDD region 107b is irradiated with multiple reflections from the light source 111. Further, the light L104 directed from the back surface side of the TFT array substrate 100 toward the data line 111 is irradiated with multiple reflection between the lower light shielding film 103 and the data line 111 to the LDD region 107b. Similarly, the LDD region 107d is also irradiated with multiple reflected light. Actually, not only L103 and L104 as shown in FIG. 25, but also light of various angles and directions is incident from the back side of the TFT array substrate 100, so that light is also applied to the channel region 107c by the multiple reflection described above. Irradiated.

  Therefore, various improvements have been made so far in order to prevent such problems.

  For example, Japanese Patent Laid-Open No. 2000-180899 discloses a liquid crystal display device in which an end portion of a lower light shielding film is tapered. In this liquid crystal display device, by appropriately setting the width of the lower light-shielding film and the width of the data line, light incident from the back side of the TFT array substrate is blocked and light irradiation to the channel region of the TFT is prevented. Is done.

  Japanese Laid-Open Patent Publication No. 2000-356787 discloses a liquid crystal display device in which dummy contact holes are formed in an insulating film covering a lower light shielding film in the vicinity of a TFT channel region, and a wiring material film is filled therein. It is disclosed. In this liquid crystal display device, since the film of the wiring material filled in the dummy contact hole blocks light incident from the back side of the TFT array substrate, light irradiation to the channel region of the TFT is prevented.

  In general, there are a case where the black matrix film is formed on the TFT array substrate and a case where it is formed on the counter substrate. When the black matrix film is formed on the counter substrate, it is necessary to allow an alignment error of about 10 μm between the black matrix film and the TFT in consideration of the overlay accuracy between the TFT array substrate and the counter substrate. Therefore, the width of the black matrix must be increased. Therefore, there is a drawback that the aperture ratio cannot be increased.

On the other hand, when the black matrix film is formed on the TFT array substrate, the alignment accuracy between the black matrix film and the TFT can be increased by using the manufacturing process of the semiconductor device. Therefore, a method of forming a black matrix film on the TFT array substrate as in the TFT array substrate 100 of FIGS. 23 and 24 is becoming mainstream.
JP 2000-180899 A JP 2000-356787 A

As described above, in the liquid crystal display device provided with the conventional TFT array substrate 100 of FIGS. 23 and 24, a part of the light incident from the back side of the TFT array substrate 100 is caused by the LDD regions 107b and 107d and the channel of the TFT 131. thus irradiated to the region 107c. Therefore, there is a problem that the light leakage current increases, resulting in a decrease in contrast and non-uniform image quality.

  In the liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 2000-180899, a manufacturing process for processing the end portion of the lower light-shielding film into a tapered shape is required, and thus there is a problem that the manufacturing process becomes complicated.

  In the liquid crystal display device disclosed in Japanese Patent Laid-Open No. 2000-356787, a manufacturing process is required for forming a dummy contact hole in an insulating film covering the lower light-shielding film and filling the wiring material film therein. . Therefore, like the liquid crystal display device disclosed in Japanese Patent Laid-Open No. 2000-180899, there is a problem that the manufacturing process becomes complicated.

  Further, in the liquid crystal display devices disclosed in Japanese Patent Laid-Open Nos. 2000-180899 and 2000-356787, when used in a light valve of a projection type display device with high brightness, sufficient light is directed toward the active layer of the TFT. It is difficult to block.

The present invention has been made in view of the above problems of the prior art. That is, the object of the present invention is to reduce the light leakage current of the thin film transistor in the pixel matrix portion , and to provide high mobility to the thin film transistor in the drive circuit portion, and easily without requiring a complicated manufacturing process. It is an object to provide a thin film transistor substrate that can be manufactured, a manufacturing method thereof , and an active matrix liquid crystal display device.

Another object of the present invention is to provide a thin film transistor array substrate, a method of manufacturing the same, and an active matrix liquid crystal display device capable of improving the uniformity of contrast and image quality.

  Other objects of the present invention will become clear from the following description.

(1) A thin film transistor array substrate according to a first aspect of the present invention includes:
A thin film transistor array substrate having a pixel matrix portion including a plurality of thin film transistors arranged in a matrix and a driving circuit portion including a thin film transistor on a light-transmitting substrate,
Each of the plurality of thin film transistors in the pixel matrix portion includes at least the thin film transistor between the thin film transistor and the light transmissive substrate, on the opposite side of the light transmissive substrate from the thin film transistor, or both. It has a high thermal conductive film formed so as to overlap the active layer,
The thin film transistor of the drive circuit unit does not have the high thermal conductive film,
Each active layer of the thin film transistor in the pixel matrix portion and the drive circuit portion is formed of a semiconductor crystallized by laser irradiation,
The high thermal conductive film has a thermal conductivity equivalent to that of silicon or a material containing silicon .

(2) In the thin film transistor array substrate according to the first aspect of the present invention, each active layer of the thin film transistor in the pixel matrix portion and the drive circuit portion is formed of a semiconductor crystallized by laser irradiation. In addition, each of the plurality of thin film transistors in the pixel matrix portion has the high heat conductive film, and the thin film transistor in the driving circuit portion does not have the high heat conductive film. For this reason, it is generated when each active layer of the thin film transistor of the pixel matrix part and the driving circuit part is formed by irradiating the semiconductor film (for example, amorphous silicon film) with laser light and crystallizing. The heat to be transmitted to the surroundings is faster in the thin film transistors in the pixel matrix portion than in the thin film transistors in the driving circuit portion. As a result, compared to the thin film transistor of the drive circuit section, wherein in the said thin film transistor in the pixel matrix portion lower semiconductor film degree of crystallinity (for example, polysilicon film) is obtained, it is possible to reduce it by light leakage current . This leads to an improvement in contrast and image quality uniformity. On the other hand, the thin film transistor in the driver circuit portion can have a higher mobility than the thin film transistor in the pixel matrix portion because a semiconductor film (for example, a polysilicon film) having a high degree of crystallinity can be obtained. .

  In addition, it can be easily manufactured without requiring a complicated manufacturing process unlike the conventional liquid crystal display devices disclosed in Japanese Patent Laid-Open Nos. 2000-180899 and 2000-356787.

(3) In a preferred example of the thin film transistor array substrate according to the first aspect of the present invention, the high thermal conductive film is located between the corresponding thin film transistor and the translucent substrate, and the high thermal conductive film and the active layer The thickness of the insulating film existing between is in the range of 100 nm to 500 nm. The thickness of the insulating film is more preferably in the range of 150 nm to 300 nm.

In another preferable example of the thin film transistor array substrate according to the first aspect of the present invention, the high thermal conductive film functions as a light blocking film that blocks light toward the active layer of the corresponding thin film transistor . This is because the light shielding effect is improved. In this case, it is more preferable that the high thermal conductive film can absorb the irradiated light. This is because the light shielding effect is further improved.

In another preferable example of the thin film transistor array substrate according to the first aspect of the present invention, the light blocking the light toward the active layer of the corresponding thin film transistor formed between the high thermal conductive film and the translucent substrate. It further has a membrane. This is because the light shielding effect is further improved.

  The high thermal conductive film is preferably formed of a silicon film or a film of a material containing silicon. In this case, the light leakage current can be efficiently reduced. The light shielding film may be formed of a silicon film doped with impurities. In this case, a light shielding film having conductivity can be easily realized.

(4) An active matrix type liquid crystal display device according to a second aspect of the present invention provides:
Any one of the thin film transistor array substrates according to the above (1) or (3);
A counter substrate disposed to face the thin film transistor array substrate;
A liquid crystal layer provided between the thin film transistor array substrate and the counter substrate.

(5) In the active matrix type liquid crystal display device of the second aspect of the present invention, the same effect as that of the thin film transistor array substrate is obtained for the same reason as that of the thin film transistor array substrate of the first aspect of the present invention. It is done.
(6) A method of manufacturing a thin film transistor array substrate according to the third aspect of the present invention includes:
A method of manufacturing a thin film transistor array substrate according to a first aspect of the present invention, comprising:
Forming a semiconductor film for each active layer of the thin film transistor in the pixel matrix portion and the drive circuit portion;
For each of the plurality of thin film transistors in the pixel matrix portion, at least for the thin film transistor, between the thin film transistor and the light transmissive substrate, on the opposite side of the light transmissive substrate from the light transmissive substrate, or both. Forming the high thermal conductive film so as to overlap the semiconductor film of
Forming an active layer of each of the thin film transistors of the pixel matrix portion and the drive circuit portion by crystallizing the semiconductor film of the pixel matrix portion and the drive circuit portion by laser irradiation;
It is characterized by comprising.
(7) In the method of manufacturing a thin film transistor array substrate according to the third aspect of the present invention,
It is apparent that the thin film transistor array substrate according to the first aspect of the present invention is manufactured.

According to the thin film transistor array substrate and a manufacturing method thereof a liquid crystal display device of the present invention, it is possible to reduce light leakage current of the thin film transistor of the pixel matrix portion, so that the uniformity of the contrast and image quality is enhanced. On the other hand, the thin film transistor in the driver circuit portion can have high mobility. And it can manufacture easily, without requiring a complicated manufacturing process.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.
(First embodiment)
1 and 2 show a schematic configuration of the TFT array substrate 30 according to the first embodiment of the present invention. FIG. 1 is a plan view of the main part, and FIGS. 2A and 2B are cross-sectional views of the main part along the lines AA and BB in FIG. On this substrate, a drive circuit portion is formed together with the pixel matrix portion (see FIG. 22), and the following description is about the TFT of the pixel matrix portion. The TFT of the drive circuit portion does not have the second light shielding film .

  1 and 2 show a configuration for one pixel. This also applies to other embodiments described later.

  The TFT array substrate 30 shown in FIGS. 1 and 2 includes a translucent substrate 1 having a plurality of TFTs 31 arranged in a matrix. The substrate 1 is made of an insulating material such as glass.

A silicon oxide film (SiO ₂ ) 2 is formed on the entire surface of the substrate 1. This silicon oxide film 2 is for preventing the diffusion of heavy metals contained in the substrate 1.

  On the silicon oxide film 2, stripe-shaped first portions 3a extending along the matrix row direction (X direction in FIG. 1) and the matrix column direction (Y direction in FIG. 1) are extended. A lattice-shaped first light-shielding film 3 is formed so as to intersect with the existing stripe-shaped second portion 3b. The first light shielding film 3 is formed of a material having a low light transmittance (for example, tungsten silicide), and has a film thickness that can sufficiently block light directly incident from the back side of the TFT array substrate 30. The entire first light shielding film 3 is covered with a silicon oxide film 4 formed on the silicon oxide film 2.

  On the silicon oxide film 4, a plurality of second light shielding films 5 made of an amorphous silicon film capable of absorbing light are formed. Each of the second light shielding films 5 includes a plurality of stripe-shaped first portions 5a extending along the X direction and a plurality of parallel portions that extend along the Y direction and are arranged along the X direction. And a second portion 5b. The first portions 5a of the second light shielding film 5 are parallel to each other. Each of the second portions 5b of the second light shielding film 5 has a rectangular shape. Each of the second light shielding films 5 is disposed so as to overlap the first light shielding film 3 and is covered with a silicon oxide film 6 formed on the silicon oxide film 4.

  In this embodiment, the second light shielding film 5 functions as a high thermal conductive film.

  On the silicon oxide film 6, a plurality of polycrystalline silicon films 7 patterned in a substantially L shape are formed. These polycrystalline silicon films 7 are respectively disposed under intersections of gate lines 9 and data lines 11 described later. Each of the polycrystalline silicon films 7 functions as an active layer of the TFT 31.

  That is, each of the polycrystalline silicon films 7 includes a channel region 7c that is not doped with impurities, LDD regions 7b and 7d that are doped with impurities at a low concentration, a source region 7a and a drain that are doped with impurities at a high concentration. Region 7e. The source region 7a and the drain region 7e are formed with the channel region 7c interposed therebetween. The LDD region 7b is formed between the source region 7a and the channel region 7c, and the LDD region 7d is formed between the channel region 7c and the drain region 7e.

  The source region 7a, the LDD region 7b, the channel region 7c, the LDD region 7d, and the drain region 7e are arranged along the Y direction so as to overlap the first and second light shielding films 3 and 5. A part of the drain region 7e extends along the X direction. Each of the polycrystalline silicon films 7 is covered with a gate insulating film 8 formed on the silicon oxide film 6.

  On the gate insulating film 8, a plurality of gate lines 9 made of an impurity-doped polycrystalline silicon film or silicide film are formed. Those gate lines 9 are parallel to each other and all extend along the X direction. Each gate line 9 is disposed so as to overlap the channel region 7c of the TFT 31 belonging to the same row of the matrix, and functions as a gate electrode of the TFT 31. Each gate line 9 is covered with a first interlayer insulating film 10 formed on the gate insulating film 8.

  On the first interlayer insulating film 10, a plurality of data lines 11 made of an aluminum film or the like are formed. These data lines 11 are parallel to each other, extend along the Y direction, and are arranged so as to overlap the polycrystalline silicon film 7 of the TFT 31 belonging to the same column of the matrix. The entire source region 7a, channel region 7c, and LDD regions 7b and 7d of each TFT 31 are covered with the corresponding data line 11. The drain region 7 e of each TFT 31 is partially covered with the corresponding data line 11. Each data line 11 is electrically connected to the source region 7a of the TFT 31 belonging to the same column of the matrix via a contact hole 21 penetrating the first interlayer insulating film 10 and the gate insulating film 8. Each data line 11 is covered with a second interlayer insulating film 12 formed on the first interlayer insulating film 10.

  On the second interlayer insulating film 12, a substantially lattice-like black matrix film 13 extending in each of the X direction and the Y direction is formed. The black matrix film 13 is disposed so as to overlap each gate line 9 and each data line 11 and covers the TFT 31. The black matrix film 13 is made of a chromium film or the like and functions as a third light shielding film. The entire black matrix film 13 is covered with a third interlayer insulating film 14 formed on the second interlayer insulating film 12.

  A plurality of substantially rectangular pixel electrodes 15 are formed on the third interlayer insulating film 14. The pixel electrodes 14 are respectively disposed in a plurality of pixel regions 20 defined by the gate lines 9 and the data lines 11. Each pixel electrode 15 is electrically connected to the drain region 7e of the corresponding TFT 31 through the contact hole 22 that penetrates the third interlayer insulating film 14, the second interlayer insulating film 12, the first interlayer insulating film 10, and the gate insulating film 8. Connected.

  In the liquid crystal display device including the TFT array substrate 30 having the above-described configuration, as shown in FIG. 3, light L1 incident from the surface side of a counter substrate (not shown) arranged to face the TFT array substrate 30 Is blocked by the black matrix film 13 or passes through the TFT array substrate 30 without being reflected by the first light shielding film 3. As such, the width of the black matrix film 13, the width of the first light shielding film 3, the distance between the black matrix film 13 and the first light shielding film 3, and the like are set.

  On the other hand, the light L <b> 2 that enters from the back side of the TFT array substrate 30 and travels toward the first light shielding film 3 is blocked by the first light shielding film 3. Light L3 that is incident from the back side of the TFT array substrate 30 and travels toward the black matrix film 13 is reflected by the black matrix film 13 and then the second light shielding film 5 provided between the first light shielding film 3 and the TFT 31. Is irradiated. Alternatively, after being reflected by the black matrix film 13 and the first light shielding film 3, the second light shielding film 5 is irradiated. Further, the light L 4 that is incident from the back side of the TFT array substrate 30 and travels toward the data line 11 is reflected by the data line 11 and then irradiated to the second light shielding film 5. As described above, the second light shielding film 5 is made of an amorphous silicon film capable of absorbing light. Therefore, these lights irradiated to the second light shielding film 5 are absorbed by the second light shielding film 5.

  As described above, even if light from the back surface side of the TFT array substrate 30 is reflected directly or reflected by the black matrix film 13 and is incident between the first light shielding film 3 and the data line 11, the light is reflected by the second light shielding film. 5 is absorbed. Therefore, the light traveling toward the channel region 7c and the LDD regions 7b and 7d of the TFT 31 is effectively and reliably blocked.

  In addition, since the channel region 7c is covered with the gate line 9, the effect | action which interrupts | blocks the light which goes to the channel region 7c is further improved.

  In general, a silicon film has a spectral absorption characteristic that has a high light absorption rate for green and blue wavelengths and a low light absorption rate for red wavelengths. This also applies to the amorphous silicon film and the polycrystalline silicon film 7 that form the second light shielding film 5. As is well known, the light leakage current of the TFT 31 is generated when the polycrystalline silicon film 7 which is an active layer absorbs light, so the magnitude of the light leakage current changes according to the wavelength of the irradiated light. Therefore, the light leakage current can be efficiently reduced by forming the second light-shielding film 5 with an amorphous silicon film having the same spectral absorption characteristics as the polycrystalline silicon film 7.

  In addition, when high-intensity light is incident on the TFT array substrate 30, a temperature rise in the vicinity of the TFT 31 occurs due to heat generated by light absorption of the second light shielding film 5. As described above, since the light absorption of the red wavelength by the second light shielding film 5 is low, there is an advantage that the temperature rise in the vicinity of the TFT 31 is suppressed accordingly.

  In addition to the amorphous silicon film, even if a microcrystalline silicon film or a polycrystalline silicon film having a crystallization component is used, substantially the same effect as in the case of the amorphous silicon film can be obtained. The same applies to a silicide film containing silicon.

  Next, a method for manufacturing the TFT array substrate 30 of FIGS. 1 and 2 will be described with reference to FIGS.

  First, as shown in FIG. 4, a silicon oxide film 2 is deposited on the entire surface of the translucent substrate 1 by a general CVD (Chemical Vapor Deposition) method. Next, a tungsten silicide film (not shown) is formed on the silicon oxide film 2, and the tungsten silicide film is patterned by using a general photolithography technique and etching technique, whereby the first light shielding film 3 is formed. Form. Thereafter, a silicon oxide film 4 is deposited on the silicon oxide film 2 by a CVD method, and the entire first light shielding film 3 is covered with the silicon oxide film 4.

  Subsequently, an amorphous silicon film (on the silicon oxide film 4) is formed by using a low pressure chemical vapor deposition (LPCVD) method, a plasma chemical vapor deposition (PCVD) method, or the like. (Not shown) is deposited and the amorphous silicon film is patterned by photolithography and etching techniques. Thus, a plurality of second light shielding films 5 are formed on the silicon oxide film 4.

  Next, as shown in FIG. 5, a silicon oxide film 6 is deposited on the silicon oxide film 4 by the CVD method, and each of the second light shielding films 5 is covered with the silicon oxide film 6. Subsequently, after depositing an amorphous silicon film (not shown) on the silicon oxide film 6 by LPCVD, PCVD, or the like, the amorphous silicon film is crystallized by laser annealing or the like. Further, the crystallized film is patterned by a photolithography technique and an etching technique. Thus, a plurality of polycrystalline silicon films 7 functioning as the active layer of the TFT 31 are formed on the silicon oxide film 4.

  Next, as shown in FIG. 6, a gate insulating film 8 made of a silicon oxide film is formed on the silicon oxide film 6 by the CVD method, and each of the polycrystalline silicon films 7 is covered with the gate insulating film 8. Further, after forming an impurity-doped polycrystalline silicon film (not shown) and a silicide film (not shown) on the gate insulating film 8 in that order, the films are patterned by a photolithography technique and an etching technique. A plurality of gate lines 9 are formed.

  Subsequently, by using each of the gate lines 9 as a mask, each of the polycrystalline silicon films 7 is selectively doped with low-concentration impurities. Further, using the patterned photoresist film (not shown) as a mask, each polycrystalline silicon film 7 is selectively doped with a high concentration impurity. Thus, the source region 7a, the LDD regions 7b and 7d, the channel region 7c, and the drain region 7e are formed in each of the polycrystalline silicon films 7.

  Next, as shown in FIG. 7, a first interlayer insulating film 10 made of a silicon oxide film is formed on the gate insulating film 8 by a CVD method, and each of the gate lines 9 is covered with the first interlayer insulating film 10. Thereafter, the first interlayer insulating film 10 and the gate insulating film 8 are selectively removed by photolithography technique and etching technique to form a contact hole 21 exposing the source region 7a. Subsequently, an aluminum film (not shown) is formed on the first interlayer insulating film 10 by sputtering or the like, and the aluminum film is patterned by a photolithography technique and an etching technique to form a plurality of data lines 11. Each of the data lines 11 is also formed inside the contact hole 21 and is electrically connected to the source region 21.

  Next, as shown in FIG. 8, a second interlayer insulating film 12 made of a silicon oxide film is formed on the first interlayer insulating film 10 by the CVD method, and each of the data lines 11 is covered with the second interlayer insulating film 12. . Subsequently, a chromium film (not shown) is formed on the second interlayer insulating film 12 by sputtering or the like, and the chromium film is patterned by a photolithography technique and an etching technique to form a black matrix film (that is, a third light shielding film). ) 13 is formed. Thereafter, a third interlayer insulating film 14 made of a silicon oxide film is formed on the second interlayer insulating film 12 by the CDV method, and the black matrix film 13 is covered with the third interlayer insulating film 14.

  Next, the third interlayer insulating film 14, the second interlayer insulating film 12, the first interlayer insulating film 10, and the gate insulating film 8 are selectively removed by photolithography technique and etching technique to expose the drain region 7e. Contact hole 22 is formed. Further, an ITO (Indium Thin Oxide) film (not shown) is formed on the third interlayer insulating film 14, and the ITO film is patterned by a photolithography technique and an etching technique to form a plurality of pixel electrodes 15. Each of the pixel electrodes 15 is also formed inside the contact hole 22 and is electrically connected to the drain region 7e.

  Through the above steps, the TFT array substrate 30 shown in FIGS. 1 and 2 is obtained.

  Thus, the manufacturing process of the TFT array substrate 30 is simple, and the TFT array substrate 30 can be easily manufactured.

  As described above, in the TFT array substrate 30 of the first embodiment, the first light shielding film 3 is provided between the translucent substrate 1 and the TFT 31, and the first light shielding film 3 and the TFT 31 are provided with the first light shielding film 3. Two light shielding films 5 are provided. The first and second light-shielding films 3 and 5 are disposed so as to overlap the polycrystalline silicon film 7 (that is, the active layer of the TFT 31), and the second light-shielding film 5 can absorb the irradiated light.

  Therefore, even if the light incident from the back side of the TFT array substrate 30 is reflected by the black matrix film 13 or the data line 11 and further reflected by the first light shielding film 3, all of the reflected light is reflected by the second light shielding film 5. Will be irradiated. Then, since the second light shielding film 5 absorbs the irradiated light, the light traveling toward the channel region 7c and the LDD regions 7b and 7d of the TFT 31 is effectively blocked. Therefore, the light leakage current is reduced, and as a result, the contrast and image quality uniformity of the liquid crystal display device are improved.

  Further, it can be easily manufactured without requiring a complicated manufacturing process unlike the conventional liquid crystal display devices disclosed in Japanese Patent Application Laid-Open Nos. 2000-180899 and 2000-356787.

In the present invention, the thickness of the insulating film between the first light-shielding film 3 and the second light-shielding film 5 and the thickness of the insulating film between the second light-shielding film 5 and the active layer (that is, the polycrystalline silicon film) 7 It is an important parameter. In particular, the thickness of the insulating film between the second light shielding film 5 and the active layer 7 is important. The smaller the thickness of the insulating film between the second light shielding film 5 and the active layer 7, the greater the light shielding effect. According to experiments, it has been found that a remarkable light-shielding effect can be obtained by setting the thickness to 500 nm or less.

  Further, when the thickness of the insulating film between the second light shielding film 5 and the active layer 7 is reduced, the transistor characteristics of the TFT 31 are affected. It was also found that the process of crystallization by annealing is also affected. Therefore, in order to obtain the light shielding effect of the present invention, the thickness of the insulating film between the second light shielding film 5 and the active layer 7 is preferably in the range of 500 nm to 100 nm, more preferably in the range of 150 nm to 300 nm. I found out. The same applies to other embodiments described later.

(Second Embodiment)
9 and 10 show a schematic configuration of a TFT array substrate 30A according to the second embodiment of the present invention. FIG. 9 is a plan view of the main part, and FIGS. 10A and 10B are cross-sectional views of the main part taken along the lines CC and DD of FIG.

  The TFT array substrate 30A of FIGS. 9 and 10 is different from the TFT array substrate 30 of the first embodiment in that the second light-shielding film 5A has conductivity and is electrically connected to the corresponding gate line 9. Is different. Other configurations are the same as those of the TFT array substrate 30 of the first embodiment. Therefore, in FIGS. 9 and 10, the same or corresponding components as those in the TFT array substrate 30 of the first embodiment are denoted by the same reference numerals as those in FIGS. 1 and 2, and the description of the components having the same configuration is omitted.

  In the TFT array substrate 30 </ b> A, a plurality of second light shielding films 5 </ b> A made of a polycrystalline silicon film into which impurities are introduced are formed on the silicon oxide film 4. Each of the second light shielding films 5A includes a stripe-shaped first portion 5Aa extending along the row direction of the matrix (X direction in FIG. 9) and the column direction of the matrix (Y direction in FIG. 9). And a plurality of second portions 5Ab parallel to each other disposed along the X direction. The first portions 5Aa of the second light shielding film 5A are parallel to each other. Each of the second portions 5Ab of the second light shielding film 5A has a rectangular shape. Each of the second light shielding films 5A is arranged so as to overlap with the first light shielding film 3, and each of the second portions 5Ab of the second light shielding film 5A overlaps with the polycrystalline silicon film 7.

  Each of the second light shielding films 5 </ b> A is electrically connected to the corresponding gate line 9 via the internal wiring 41. Therefore, the gate line 9 functions as a first gate electrode of the TFT 31 and the second light shielding film 5A functions as a second gate electrode of the TFT 31. That is, the TFT 31 operates as a dual gate type field effect transistor.

Thus, when the second light shielding film 5A is used as the second gate electrode of the TFT 31, the interelectrode capacitance of the TFT 31 increases. Therefore, an increase in the interelectrode capacitance of the TFT 31 is suppressed by reducing the length L (that is, the length along the Y direction) L of the second portion 5Ab of the second light shielding film 5A.

  That is, the second portion 5Ab of the second light shielding film 5A overlaps the channel region 7c and the LDD regions 7b and 7d of the TFT 31, but hardly overlaps the source region 7a and the drain region 7e of the TFT 31. By forming the second portion 5Ab of the second light shielding film 5A in this manner, the interelectrode capacitance of the TFT 31 can be increased while maintaining the effect of blocking the light directed to the channel region 7c and the LDD regions 7b and 7d of the TFT 31. It is possible to make it practically unproblematic.

  The TFT array substrate 30A is manufactured by a manufacturing method substantially similar to that of the TFT array substrate 30 of the first embodiment.

  In the TFT array substrate 30A of the second embodiment, the same effect as the TFT array substrate 30 of the first embodiment can be obtained. That is, the light toward the channel region 7c and the LDD regions 7b and 7d of the TFT 31 is effectively blocked. Therefore, the light leakage current is reduced, and as a result, the contrast and image quality uniformity of the liquid crystal display device are improved. And it can manufacture easily, without requiring a complicated manufacturing process.

  Furthermore, the TFT array substrate 30A of the second embodiment has an advantage that excellent on / off characteristics can be obtained because the TFT 31 operates as a dual gate type field effect transistor.

(Third embodiment)
FIG. 11 is a plan view of an essential part showing a schematic configuration of a TFT array substrate 30B according to the third embodiment of the present invention.

The TFT array substrate 30B of FIG. 11 is different from the TFT array substrate 30 of the first embodiment in that one second light shielding film 5B is provided and a constant voltage V _C is supplied to the second light shielding film 5B. ing. Other configurations are the same as those of the TFT array substrate 30 of the first embodiment. Therefore, in FIG. 11, the same or corresponding components as those of the TFT array substrate 30 of the first embodiment are denoted by the same reference numerals as those in FIGS. 1 and 2, and the description of the same components is omitted.

  In the TFT array substrate 30B, the second light shielding film 5B is made of a polycrystalline silicon film into which impurities are introduced. The second light-shielding film 5B includes a plurality of stripe-shaped first portions 5Ba extending in the matrix row direction (X direction in FIG. 11) and the matrix column direction (Y direction in FIG. 11). And a plurality of stripe-shaped second portions 5Bb extending along the line. Each of the first portions 5Ba of the second light shielding film 5B is parallel to each other, and each of the second portions 5Bb of the second light shielding film 5B is parallel to each other. The first portion 5Ba and the second portion 5Bb of the second light shielding film 5B intersect with each other to form a lattice-like planar shape. The second light shielding film 5B is disposed so as to overlap the first light shielding film 3, and each of the second portions 5Bb of the second light shielding film 5B overlaps the polycrystalline silicon film 7.

In addition, a constant voltage V _C is supplied to the second light shielding film 5B via the external terminal 51. The constant voltage V _C biases the second light shielding film 5B to a constant potential. Therefore, the characteristics of the TFT 31 can be controlled by adjusting the voltage value of the constant voltage V _C.

  The TFT array substrate 30B is manufactured by a manufacturing method substantially similar to that of the TFT array substrate 30 of the first embodiment.

  In the TFT array substrate 30B of the third embodiment, the same effect as that of the TFT array substrate 30 of the first embodiment can be obtained. That is, the light toward the channel region 7c and the LDD regions 7b and 7d of the TFT 31 is effectively blocked. Therefore, the light leakage current is reduced, and as a result, the contrast and image quality uniformity of the liquid crystal display device are improved. And it can manufacture easily, without requiring a complicated manufacturing process.

Furthermore, the TFT array substrate 30B of the third embodiment has an advantage that the characteristics of the TFT 31 can be controlled by adjusting the constant voltage V _C supplied to the second light shielding film 5B.

(Fourth embodiment)
12 and 13 show a schematic configuration of a TFT array substrate 30C according to the fourth embodiment of the present invention. 12 is a plan view of the main part, and FIGS. 13A and 13B are cross-sectional views of the main part taken along the lines EE and FF of FIG.

  The TFT array substrate 30 </ b> C in FIGS. 12 and 13 is obtained by applying the present invention to a TFT array substrate in which the TFT 31 is not covered with the data line 11.

That is, the plurality of polycrystalline silicon films 7 ′ functioning as the active layer of the TFT 31 extend along the row direction of the matrix, and the first light shielding film 3 ′ and the first light shielding film 3 ′ are overlapped with the polycrystalline silicon films 7 ′. 2 A light shielding film 5C and a black matrix film 13 ′ are formed, and the TFT 31 has a gate electrode 9a electrically connected to the gate line 9. The rest of the configuration is the same as that of the TFT array substrate 30 of the first embodiment. Therefore, in FIGS. 12 and 13, the same or corresponding components as those of the TFT array substrate 30 of the first embodiment are denoted by the same reference numerals as those in FIGS.

  In the TFT array substrate 30C shown in FIGS. 12 and 13, the first light-shielding film 3 ′ formed on the silicon oxide film 2 has a stripe shape extending along the row direction of the matrix (X direction in FIG. 12). The first portion 3a ′, the stripe-shaped second portion 3b ′ extending along the column direction of the matrix (Y direction in FIG. 12), and the third portion 3c ′ protruding toward the corresponding pixel region 20 And have. The first, second and third portions 3a ', 3b' and 3c 'form a substantially lattice-like planar shape. The first light-shielding film 3 ′ is formed of a material having a low light transmittance (for example, tungsten silicide), and has a film thickness that can sufficiently shield light directly incident from the back side of the TFT array substrate 30C. . The entire first light shielding film 3 ′ is covered with a silicon oxide film 4 formed on the silicon oxide film 2.

  On the silicon oxide film 4, a plurality of second light shielding films 5C made of an amorphous silicon film capable of absorbing light are formed. Each of the second light-shielding films 5C includes a stripe-shaped first portion 5Ca extending along the X direction and a plurality of parallel parallel to each other extending along the Y direction and arranged along the X direction. And a second portion 5Cb. The first portions 5Ca of the second light shielding film 5C are parallel to each other. Each of the second portions 5Cb of the second light shielding film 5C has a rectangular shape and protrudes toward the corresponding pixel region 20 side. Each of the second light shielding films 5 </ b> C is disposed so as to overlap the first light shielding film 3 ′, and is covered with a silicon oxide film 6 formed on the silicon oxide film 4.

  On the silicon oxide film 6, a plurality of polycrystalline silicon films 7 'patterned in a substantially rectangular shape are formed. These polycrystalline silicon films 7 ′ are arranged in the vicinity of the intersections between the gate lines 9 and the data lines 11. Each of the polycrystalline silicon films 7 ′ functions as an active layer of the TFT 31.

  That is, each of the polycrystalline silicon films 7 ′ includes a channel region 7c ′ that is not doped with impurities, LDD regions 7b ′ and 7d ′ that are doped with impurities at a low concentration, and a source that is doped with impurities at a high concentration. A region 7a ′ and a drain region 7e ′ are included. The source region 7a 'and the drain region 7e' are formed with the channel region 7c 'interposed therebetween. The LDD region 7b 'is formed between the source region 7a' and the channel region 7c ', and the LDD region 7d' is formed between the channel region 7c 'and the drain region 7e'.

  The source region 7a ′, the LDD region 7b ′, the channel region 7c ′, the LDD region 7d ′, and the drain region 7e ′ are arranged along the X direction so as to overlap the first and second light shielding films 3 ′ and 5C. ing. Each of the polycrystalline silicon films 7 ′ is covered with a gate insulating film 8 formed on the silicon oxide film 6.

  On the gate insulating film 8, a plurality of gate electrodes 9a corresponding to the respective TFTs 31 and a plurality of gate lines 9 which are parallel to each other and extend along the X direction are formed. The gate electrode 9a and the gate line 9 are made of a polycrystalline silicon film or a silicide film doped with impurities. Each gate electrode 9a extends along the Y direction and is parallel to each other. Each gate electrode 9 a is disposed so as to overlap the channel region 7 c ′ of the corresponding TFT 31 and is electrically connected to the corresponding gate line 9. Each gate electrode 9 a and each gate line 9 are covered with a first interlayer insulating film 10 formed on the gate insulating film 8.

  The black matrix film 13 ′ formed on the second interlayer insulating film 12 has a substantially lattice-like planar shape extending in each of the X direction and the Y direction. The black matrix film 13 ′ is disposed so as to overlap each gate line 9 and each data line 11. A part of the black matrix film 13 ′ protrudes toward the pixel region 20, and the protruding part covers the TFT 31. The black matrix film 13 is made of a chromium film or the like and functions as a third light shielding film. The entire black matrix film 13 is covered with a third interlayer insulating film 14 formed on the second interlayer insulating film 12.

  Also in the liquid crystal display device including the TFT array substrate 30C having the above-described configuration, a light shielding effect almost similar to that in the case of the TFT array substrate 30 of the first embodiment can be obtained.

  That is, as shown in FIG. 14, the light L1 incident from the surface side of the counter substrate (not shown) arranged to face the TFT array substrate 30C is blocked by the black matrix film 13 ′ or the first The light passes through the TFT array substrate 30 without being reflected by the light shielding film 3 ′.

  On the other hand, the light L2 incident from the back side of the TFT array substrate 30C and traveling toward the first light shielding film 3 'is blocked by the first light shielding film 3'. The light L3 incident from the back side of the TFT array substrate 30C and traveling toward the black matrix film 13 ′ is reflected by the black matrix film 13 and then second light shielding provided between the first light shielding film 3 ′ and the TFT 31. The film 5C is irradiated. Alternatively, after being reflected by the black matrix film 13 'and the first light shielding film 3', the second light shielding film 5C is irradiated. As described above, the second light shielding film 5C is made of an amorphous silicon film capable of absorbing light. Therefore, these lights irradiated to the second light shielding film 5C are absorbed by the second light shielding film 5C.

  Thus, even if the light from the back surface side of the TFT array substrate 30 is reflected by the black matrix film 13 ′ and further reflected by the first light shielding film 3 ′, the reflected light is absorbed by the second light shielding film 5C. The Therefore, the light traveling toward the channel region 7c 'and the LDD regions 7b' and 7d 'of the TFT 31 is effectively and reliably blocked.

  The TFT array substrate 30C is manufactured by a manufacturing method substantially similar to that of the TFT array substrate 30 of the first embodiment.

  As described above, the TFT array substrate 30C of the fourth embodiment can obtain the same effects as those of the TFT array substrate 30 of the first embodiment. That is, light directed to the channel region 7c 'and the LDD regions 7b' and 7d 'of the TFT 31 is effectively blocked. Therefore, the light leakage current is reduced, and as a result, the contrast and image quality uniformity of the liquid crystal display device are improved. And it can manufacture easily, without requiring a complicated manufacturing process.

(Fifth embodiment)
FIG. 15 is a plan view of an essential part showing a schematic configuration of a TFT array substrate 30D according to the fifth embodiment of the present invention.

  The TFT array substrate 30D of FIG. 15 is different from the TFT array substrate 30C of the fourth embodiment in that the second light-shielding film 5D has conductivity and is electrically connected to the corresponding gate line 9. . The other configuration is the same as that of the TFT array substrate 30C of the fourth embodiment. Therefore, in FIG. 15, the same reference numerals as those in FIGS. 12 and 13 are given to the same or corresponding components as those in the TFT array substrate 30C of the fourth embodiment, and the description of the parts having the same configuration is omitted.

  In the TFT array substrate 30D, the second light shielding film 5D is made of a polycrystalline silicon film into which impurities are introduced. Each of the second light-shielding films 5D includes a stripe-shaped first portion 5Da extending along the X direction and a plurality of parallel parallel to each other extending along the Y direction and arranged along the X direction. And a second portion 5Db. The first portions 5Da of the second light shielding film 5D are parallel to each other. Each of the second portions 5Db of the second light shielding film 5D has a rectangular shape and protrudes toward the corresponding pixel region 20 side. Each of the second light shielding films 5D is disposed so as to overlap with the first light shielding film 3 ', and the second portion 5Db of the second light shielding film 5D overlaps with the polycrystalline silicon film 7'.

  Further, each of the second light shielding films 5D is electrically connected to the corresponding gate line 9 via the internal wiring 41, like the TFT array substrate 30A of the second embodiment. Therefore, the gate electrode 9a functions as the first gate electrode of the TFT 31, and the second light shielding film 5D functions as the second gate electrode of the TFT 31. That is, the TFT 31 operates as a dual gate type field effect transistor.

  Thus, when the second light-shielding film 5D is used as the second gate electrode of the TFT 31, the interelectrode capacitance of the TFT 31 increases. Therefore, the increase in the interelectrode capacitance of the TFT 31 is suppressed by reducing the width W (that is, the length in the X direction) W of the second portion 5Db of the second light shielding film 5D.

  That is, the second portion 5Db of the second light-shielding film 5D overlaps the channel region 7c 'and the LDD regions 7b' and 7d 'of the TFT 31, but hardly overlaps the source region 7a' and the drain region 7e 'of the TFT 31. By forming the second portion 5Db of the second light-shielding film 5D in this way, the interelectrode capacitance of the TFT 31 is maintained while maintaining the effect of blocking the light directed to the channel region 7c ′ and the LDD regions 7b ′ and 7d ′ of the TFT 31. Can be increased to the extent that there is no practical problem.

  The TFT array substrate 30D is manufactured by a manufacturing method substantially similar to that of the TFT array substrate 30 of the first embodiment.

  As described above, the TFT array substrate 30D of the fifth embodiment can obtain the same effects as those of the TFT array substrate 30 of the first embodiment. That is, light directed to the channel region 7c 'and the LDD regions 7b' and 7d 'of the TFT 31 is effectively blocked. Therefore, the light leakage current is reduced, and as a result, the contrast and image quality uniformity of the liquid crystal display device are improved. And it can manufacture easily, without requiring a complicated manufacturing process.

  Further, in the TFT array substrate 30D of the fifth embodiment, as the TFT array substrate 30A of the second embodiment, the TFT 31 operates as a dual-gate field effect transistor, so that excellent on / off characteristics can be obtained. There are advantages.

(Sixth embodiment)
FIG. 16 is a plan view of a principal part showing a schematic configuration of a TFT array substrate 30E according to the sixth embodiment of the present invention.

The TFT array substrate 30E of FIG. 16 is different from the TFT array substrate 30C of the fourth embodiment in that one second light shielding film 5E is provided and a constant voltage V _C is supplied to the second light shielding film 5E. ing. The other configuration is the same as that of the TFT array substrate 30C of the fourth embodiment. Therefore, in FIG. 16, the same reference numerals as those in FIGS. 12 and 13 are given to the same or corresponding components as those of the TFT array substrate 30C of the fourth embodiment, and the description of the same components will be omitted.

  In the TFT array substrate 30E, the second light shielding film 5E is made of a polycrystalline silicon film into which impurities are introduced. The second light-shielding film 5E includes a plurality of stripe-shaped first portions 5Ea extending along the matrix row direction (X direction in FIG. 16) and the matrix column direction (Y direction in FIG. 16). A plurality of rectangular second portions 5Eb extending along the X direction and arranged in parallel with each other along the X direction, and a plurality of stripe-shaped third portions 5Ec extending along the Y direction. ing. The first portions 5Ea of the second light shielding film 5E are parallel to each other, and the third portions 5Ec are parallel to each other. The first and second portions 5Ea and 5Ec of the second light shielding film 5E intersect with each other to form a lattice-like planar shape. Each of the second portions 5Eb of the second light shielding film 5E protrudes toward the corresponding pixel region 20 side. Each of the second light shielding films 5E is disposed so as to overlap with the first light shielding film 3 ', and the second portion 5Eb of the second light shielding film 5E overlaps with the polycrystalline silicon film 7'.

Further, the constant voltage V _C is supplied to the second light shielding film 5E via the external terminal 51, as in the TFT array substrate 30B of the third embodiment. This constant voltage V _C biases the second light shielding film 5E to a constant potential. Therefore, the characteristics of the TFT 31 can be controlled by adjusting the voltage value of the constant voltage V _C.

  The TFT array substrate 30B is manufactured by a manufacturing method substantially similar to that of the TFT array substrate 30 of the first embodiment.

  In the TFT array substrate 30E of the sixth embodiment, the same effect as that of the TFT array substrate 30 of the first embodiment can be obtained. That is, light directed to the channel region 7c 'and the LDD regions 7b' and 7d 'of the TFT 31 is effectively blocked. Therefore, the light leakage current is reduced, and as a result, the contrast and image quality uniformity of the liquid crystal display device are improved. And it can manufacture easily, without requiring a complicated manufacturing process.

Further, in the TFT array substrate 30E of the sixth embodiment, the characteristics of the TFT 31 are controlled by adjusting the constant voltage V _C supplied to the second light shielding film 5E, similarly to the TFT array substrate 30B of the third embodiment. There is an advantage that you can.

(Seventh embodiment)
In the first to sixth embodiments described above, in addition to the first light shielding film 3 and the third light shielding film (black matrix film) 13, the second light shielding film having light absorption between the first light shielding film 3 and the TFT 31. 5 is provided to improve the light shielding performance.

  The seventh to tenth embodiments described below are examples in which a fourth light-shielding film 16 having light absorptivity is provided between the TFT 31 and the third light-shielding film (black matrix film) 13. Even when the fourth light-shielding film 16 having light absorptivity is arranged on the TFT 31, the light that is multiply reflected can be reduced similarly to the case where the second light-shielding film 5 is provided, and the light shielding effect is improved. Is possible.

  FIG. 17 shows a schematic configuration of a TFT array substrate 30F according to the seventh embodiment of the present invention. FIGS. 17A and 17B are cross-sectional views of main parts taken along lines AA and BB in FIG. 1, respectively. On this substrate, a drive circuit portion is formed together with the pixel matrix portion (see FIG. 22), and the following description is about the TFT of the pixel matrix portion. The TFT of the drive circuit portion does not have the fourth light shielding film.

The TFT array substrate 30F of the seventh embodiment shown in FIG. 17 is obtained by removing the second light shielding film 5 and adding the fourth light shielding film 16 to the TFT array substrate 30 of the first embodiment shown in FIG. . Other configurations are the same as those of the TFT array substrate 30 of the first embodiment. In this TFT array substrate 30F, since the second light shielding film 5 is removed, the SiO ₂ film 4 or 6 can be omitted.

  The pattern of the fourth light shielding film 16 is the same as that of the second light shielding film 5 shown in FIG. 1 and covers almost the entire polysilicon film 7 that functions as the active layer of the TFT 31. The fourth light shielding film 16 does not cover the portion of the polysilicon film 7 near the contact hole 22.

  Here, the fourth light shielding film 16 is embedded in the first interlayer insulating film 10. Such a configuration can be easily realized as follows, for example. That is, the first interlayer insulating film 10 has a two-layer structure, and after the lower layer portion of the first interlayer insulating film 10 is formed, an amorphous silicon film for the fourth light shielding film 16 is formed. Then, when the amorphous silicon film is patterned, a fourth light shielding film 16 is obtained. Thereafter, an upper layer portion of the first interlayer insulating film 10 is formed thereon. However, the present invention is not limited to this configuration. For example, after the fourth light shielding film 16 is formed on the first interlayer insulating film 10, the fourth light shielding film 16 may be covered with another insulating film, and the second interlayer insulating film 12 may be formed thereon.

(Eighth embodiment)
FIG. 18 shows a schematic configuration of a TFT array substrate 30G of the eighth embodiment of the present invention. 18A and 18B are cross-sectional views of main parts taken along lines AA and BB in FIG. 1, respectively.

  The TFT array substrate 30G of the eighth embodiment shown in FIG. 18 is obtained by adding the fourth light shielding film 16 to the TFT array substrate 30 of the first embodiment shown in FIG. Other configurations are the same as those of the TFT array substrate 30 of the first embodiment. In other words, the TFT array substrate 30G is obtained by adding the second light shielding film 5 to the TFT array substrate 30F of the seventh embodiment shown in FIG.

  In the TFT array substrate 30G, since the fourth light shielding film 16 and the second light shielding film 5 are provided above and below the TFT 31, a light shielding effect can be obtained for light from both the upper and lower sides of the TFT 31. Therefore, there is an advantage that a higher light shielding effect can be obtained than in the case of the first embodiment or the seventh embodiment.

(Ninth embodiment)
FIG. 19 shows a schematic configuration of a TFT array substrate 30H according to the ninth embodiment of the present invention. FIGS. 19A and 19B are cross-sectional views of main parts taken along lines EE and FF in FIG. 12, respectively.

The TFT array substrate 30H of the ninth embodiment shown in FIG. 19 is obtained by removing the second light shielding film 5C and adding the fourth light shielding film 16 ′ to the TFT array substrate 30C of the fourth embodiment shown in FIG. is there. Other configurations are the same as those of the TFT array substrate 30C of the fourth embodiment. In the TFT array substrate 30H, since the second light shielding film 5 is removed, the SiO ₂ film 4 or 6 can be omitted.

  The pattern of the fourth light shielding film 16 ′ is the same as that of the second light shielding film 5 </ b> C shown in FIG. 12 and covers almost the entire polysilicon film 7 that functions as the active layer of the TFT 31. The fourth light shielding film 16 ′ does not cover a portion of the polysilicon film 7 near the contact hole 22.

  Here, the fourth light shielding film 16 ′ is embedded in the second interlayer insulating film 12. Such a configuration can be easily realized as follows, for example. That is, the second interlayer insulating film 12 has a two-layer structure, and after forming the lower layer portion of the second interlayer insulating film 12, an amorphous silicon film for the fourth light shielding film 16 'is formed. Then, when this amorphous silicon film is patterned, a fourth light shielding film 16 'is obtained. Thereafter, an upper layer portion of the second interlayer insulating film 12 is formed thereon. However, the present invention is not limited to this configuration. For example, after the fourth light shielding film 16 ′ is formed on the second interlayer insulating film 12, the fourth light shielding film 16 ′ is covered with another insulating film, and the third interlayer insulating film 14 is formed thereon. Good.

(10th Embodiment)
FIG. 20 shows a schematic configuration of the TFT array substrate 30I according to the tenth embodiment of the present invention. 20A and 20B are cross-sectional views of main parts taken along lines EE and FF in FIG. 12, respectively.

  A TFT array substrate 30I according to the tenth embodiment shown in FIG. 20 is obtained by adding a fourth light shielding film 16 'to the TFT array substrate 30C according to the fourth embodiment shown in FIG. Other configurations are the same as those of the TFT array substrate 30C of the fourth embodiment. In other words, the TFT array substrate 30I is obtained by adding the second light shielding film 5C to the TFT array substrate 30H of the ninth embodiment shown in FIG.

  In the TFT array substrate 30I, since the fourth light shielding film 16 'and the second light shielding film 5C are provided above and below the TFT 31, respectively, a light shielding effect can be obtained for light from both the upper and lower sides of the TFT 31. Therefore, there is an advantage that a higher light shielding effect can be obtained than in the case of the first embodiment or the seventh embodiment.

  FIG. 21 shows a light leakage current characteristic generated in the TFT 31 of the pixel matrix portion under a predetermined projection light irradiation condition in consideration of use as a light valve of a projection display device. This was obtained by a test conducted by the inventors.

  As is clear from FIG. 21, in the conventional TFT array substrate 100 having the first light shielding film and the third light shielding film (see FIGS. 23 and 24), the light leakage current was 4 pA, whereas the first In the TFT array substrate 30C (see FIGS. 12 and 13) of the fourth embodiment of the present invention having the second light shielding film in addition to the light shielding film and the third light shielding film, the polycrystalline silicon film functioning as the active layer and the second As the thickness of the insulating film between the two light-shielding films decreased from 500 nm, the light leakage current gradually decreased, and the maximum decreased to about １ ／ of the conventional example.

  The effect of reducing the light leakage current has a correlation with the thickness of the insulating film between the second light-shielding film and the active layer, and the effect became larger as the thickness of the insulating film was made thinner than 500 nm. . However, although not shown in FIG. 21, if the thickness of the insulating film is smaller than 100 nm, it affects the on characteristics of the TFT 31 and the crystallinity of the active layer (polycrystalline silicon) in the laser annealing process. As a result, the on-characteristics of the TFT 31 deteriorate and the normal operation cannot be performed. From this result, it was found that the thickness of the insulating film is suitably in the range of 500 nm to 100 nm.

  In the TFT array substrate 30I (see FIG. 20) of the tenth embodiment of the present invention having the second light-shielding film and the fourth light-shielding film in addition to the first light-shielding film and the third light-shielding film, the thickness of the insulating film When the thickness was 200 nm, the light leakage current could be reduced to about ½ that of the TFT array substrate 30C of the fourth embodiment. Accordingly, it was confirmed that a larger light leakage current reduction effect can be obtained by adding a fourth light shielding film in addition to the second light shielding film.

(Eleventh embodiment)
When an amorphous silicon film is irradiated with a laser beam to form a polycrystalline silicon film for an active layer, that is, when a polycrystalline silicon film is obtained from an amorphous silicon film by laser annealing, an amorphous silicon film is used. If there is a material with high thermal conductivity (high thermal conductivity film) directly underneath, the material (high thermal conductivity film) changes the heating / cooling process by laser light irradiation from the desired one. As a result, the amorphous silicon film becomes There is a problem of being affected when crystallizing. For this reason, conventionally, a material with high thermal conductivity (high thermal conductive film) is sufficient between the amorphous silicon film and the material with high thermal conductivity (high thermal conductive film) so that the heating / cooling process is not affected. Generally, an insulating film having a proper thickness is disposed.

  On the other hand, when the drive circuit unit 62 is integrally formed with the pixel matrix unit 61 on the same substrate as the TFT array substrate 60 shown in FIG. 22, the TFT of the drive circuit unit 62 needs to have transistor characteristics with high mobility. On the other hand, the TFT of the pixel matrix portion 61 does not require high mobility, but rather requires low leakage current. In particular, for light leakage current, silicon having a relatively large number of traps serving as recombination centers is preferable. For this reason, a polycrystalline silicon film having lower crystallinity than the TFT of the drive circuit unit 62 is desirable for the TFT of the pixel matrix unit 61.

Therefore, in the eleventh embodiment of the present invention, as the TFT of the pixel matrix portion 61, the TFT 31 having the second light-shielding film and / or the fourth light-shielding film as in the first to tenth embodiments described above is used. . As the TFT of the drive circuit unit 62, a TFT having no second light-shielding film or fourth light-shielding film or both is used. In this way, in the TFT of the pixel matrix portion 61, the heat due to laser light irradiation can be quickly transmitted to the surroundings by the second light shielding film and / or the fourth light shielding film. As a result, the pixel matrix portion 61 low about TFT only crystallinity of the polycrystalline silicon film is formed as the active layer 7 of the TFT. Thus, in addition to the suppression of the light leakage current due to the presence of the light shielding film, the light leakage current can also be reduced based on the degree of crystallinity of the polycrystalline silicon film.

(Modification)
In addition, the said 1st-11th embodiment shows the suitable example of this invention. It goes without saying that the present invention is not limited to these embodiments, and various modifications are possible.

For example, in the first to sixth embodiments, the first light shielding film 3 is provided on the translucent substrate 1 via the silicon oxide film 2, but the silicon oxide film is formed according to the material of the translucent substrate 1. The first light-shielding film 3 may be provided directly on the surface of the translucent substrate 1 without forming 2. In the third and sixth embodiments, an amorphous silicon film may be used as the second light shielding films 5B and 5E, and the voltage V _C may not be applied to the second light shielding films 5B and 5E. A polycrystalline silicon film can be used as the second light-shielding films 5 and 5C of the first and fourth embodiments, and the second light-shielding films 5A of the second, third, fifth, and sixth embodiments. An amorphous silicon film into which impurities are introduced can also be used as 5B, 5D, and 5E. These can be similarly applied to the seventh to eleventh embodiments.

  As materials for forming the second light-shielding film and the fourth light-shielding film, materials other than those used in the above embodiments can be used as long as they can absorb light.

It is a principal part top view which shows schematic structure of the thin-film transistor array substrate of 1st Embodiment of this invention. (A) is principal part sectional drawing along the AA line of FIG. 1, (b) is principal part sectional drawing along the BB line of FIG. FIG. 3 is a schematic cross-sectional view corresponding to FIG. 2A showing the light shielding effect of the thin film transistor array substrate of the first embodiment of the present invention. 2A and 2B show each step of the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention, in which FIG. 2A corresponds to FIG. 2A and FIG. 2B corresponds to FIG. It is principal part sectional drawing. 2A and 2B show each step of the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention, in which FIG. 2A corresponds to FIG. 2A and FIG. 2B corresponds to FIG. It is principal part sectional drawing and is a continuation of FIG. 2A and 2B show each step of the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention, in which FIG. 2A corresponds to FIG. 2A and FIG. 2B corresponds to FIG. It is principal part sectional drawing and is a continuation of FIG. 2A and 2B show each step of the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention, in which FIG. 2A corresponds to FIG. 2A and FIG. 2B corresponds to FIG. FIG. 6 is a cross-sectional view of the main part, continuing from FIG. 6. 2A and 2B show each step of the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention, in which FIG. 2A corresponds to FIG. 2A and FIG. 2B corresponds to FIG. It is principal part sectional drawing and is a continuation of FIG. It is a principal part top view which shows schematic structure of the thin-film transistor array substrate of 2nd Embodiment of this invention. (A) is principal part sectional drawing along CC line of FIG. 9, (b) is principal part sectional drawing along the DD line of FIG. It is a principal part top view which shows schematic structure of the thin-film transistor array substrate of 3rd Embodiment of this invention. It is a principal part top view which shows schematic structure of the thin-film transistor array substrate of 4th Embodiment of this invention. (A) is principal part sectional drawing along the EE line of FIG. 12, (b) is principal part sectional drawing along the FF line | wire of FIG. It is typical sectional drawing corresponding to Fig.13 (a) which shows the light-shielding effect of the thin-film transistor array substrate of 4th Embodiment of this invention. It is a principal part top view which shows schematic structure of the thin-film transistor array substrate of 5th Embodiment of this invention. It is a principal part top view which shows schematic structure of the thin-film transistor array substrate of 6th Embodiment of this invention. FIG. 9 shows a schematic configuration of a thin film transistor array substrate according to a seventh embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA in FIG. 1, and (b) is a line BB in FIG. It is principal part sectional drawing along line. FIG. 9 shows a schematic configuration of a thin film transistor array substrate according to an eighth embodiment of the present invention, where (a) is a cross-sectional view taken along line AA of FIG. 1, and (b) is a line BB of FIG. It is principal part sectional drawing along line. 9A and 9B show a schematic configuration of a thin film transistor array substrate according to a ninth embodiment of the present invention, in which FIG. 12A is a sectional view taken along the line EE in FIG. 12, and FIG. 12B is a line FF in FIG. It is principal part sectional drawing along line. FIGS. 10A and 10B show a schematic configuration of a thin film transistor array substrate according to a tenth embodiment of the present invention, in which FIG. 12A is a cross-sectional view taken along line EE in FIG. 12 and FIG. It is principal part sectional drawing along line. It is a graph which shows the light leak current characteristic which arises in TFT of a pixel matrix part under predetermined projection light irradiation conditions. It is a schematic plan view which shows the structure of the thin-film transistor array substrate of 11th Embodiment of this invention. It is a principal part top view which shows schematic structure of the conventional thin-film transistor array substrate. (A) is principal part sectional drawing along the GG line of FIG. 23, (b) is principal part sectional drawing along the HH line of FIG. It is typical sectional drawing corresponding to Fig.24 (a) which shows the light-shielding effect of the conventional thin-film transistor array substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Translucent substrate 2 Silicon oxide film 3, 3 '1st light shielding film 3a, 3a' 1st part of 1st light shielding film 3b, 3b '2nd part of 1st light shielding film 4 Silicon oxide film 5, 5A, 5B 5C, 5D, 5E Second light shielding film (high thermal conductive film)
5a, 5Aa, 5Ba, 5Ca, 5Da, 5Ea First portion of second light shielding film 5b, 5Ab, 5Bb, 5Cb, 5Db, 5Eb Second portion of second light shielding film 5Ec Third portion of second light shielding film 6 Silicon oxide Film 7, 7 'Polycrystalline silicon film 7a, 7a' Source region 7b, 7b ', 7d, 7d' LDD region 7c, 7c 'Channel region 7e, 7e' Drain region 8 Gate insulating film 9 Gate line 9a Gate electrode 10 First 1 interlayer insulating film 11 data line 12 2nd interlayer insulating film 13, 13 ′ black matrix film (third light shielding film)
14 Third interlayer insulating film 15 Pixel electrode 16, 16 ′ Fourth light shielding film 20 Pixel region 21, 22 Contact hole 30, 30 A Thin film transistor array substrate (TFT array substrate)
30B, 30C Thin film transistor array substrate (TFT array substrate)
30D, 30E Thin film transistor array substrate (TFT array substrate)
30F, 30G Thin film transistor array substrate (TFT array substrate)
30H, 30I Thin film transistor array substrate (TFT array substrate)
31 Thin film transistor (TFT)
41 Internal wiring 51 External terminal 60 Thin film transistor array substrate (TFT array substrate)
61 Pixel matrix 62 Drive circuit

Claims (10)

A thin film transistor array substrate having a pixel matrix portion including a plurality of thin film transistors arranged in a matrix and a driving circuit portion including a thin film transistor on a light-transmitting substrate,
Each of the plurality of thin film transistors in the pixel matrix portion includes at least the thin film transistor between the thin film transistor and the light transmissive substrate, on the opposite side of the light transmissive substrate from the thin film transistor, or both. It has a high thermal conductive film formed so as to overlap the active layer,
The thin film transistor of the drive circuit unit does not have the high thermal conductive film,
Each active layer of the thin film transistor in the pixel matrix portion and the drive circuit portion is formed of a semiconductor crystallized by laser irradiation,
The thin film transistor array substrate, wherein the high thermal conductive film has a thermal conductivity equivalent to that of silicon or a material containing silicon .   2. The thin film transistor array substrate according to claim 1, wherein the high thermal conductive film functions as a light shielding film that shields light directed toward an active layer of the corresponding thin film transistor.   2. The thin film transistor array substrate according to claim 1, wherein the high thermal conductive film functions as a light shielding film that shields light toward an active layer of the corresponding thin film transistor and can absorb the light.   4. The thin film transistor array substrate according to claim 1, wherein the high thermal conductive film is formed of a silicon film or a film of a material containing silicon.   4. The thin film transistor array substrate according to claim 1, wherein the high thermal conductive film is formed of a silicon film into which impurities are introduced.   6. The light-shielding film according to claim 1, further comprising a light-shielding film that is formed between the high thermal conductive film and the translucent substrate and shields light toward the active layer of the corresponding thin-film transistor. Thin film transistor array substrate.   The high thermal conductive film is between the corresponding thin film transistor and the translucent substrate, and the thickness of the insulating film existing between the high thermal conductive film and the active layer of the thin film transistor is in the range of 100 nm to 500 nm. The thin film transistor array substrate according to any one of claims 1 to 6.   The high thermal conductive film is between the corresponding thin film transistor and the translucent substrate, and the thickness of the insulating film existing between the high thermal conductive film and the active layer of the thin film transistor is in the range of 150 nm to 300 nm. The thin film transistor array substrate according to any one of claims 1 to 6. The thin film transistor array substrate according to any one of claims 1 to 8,
A counter substrate disposed to face the thin film transistor array substrate;
An active matrix type liquid crystal display device comprising a liquid crystal layer provided between the thin film transistor array substrate and the counter substrate. A method of manufacturing the thin film transistor array substrate according to claim 1,
Forming a semiconductor film for each active layer of the thin film transistor in the pixel matrix portion and the drive circuit portion;
For each of the plurality of thin film transistors in the pixel matrix portion, at least for the thin film transistor, between the thin film transistor and the light transmissive substrate, on the opposite side of the light transmissive substrate from the light transmissive substrate, or both. Forming the high thermal conductive film so as to overlap the semiconductor film of
Forming an active layer of each of the thin film transistors of the pixel matrix part and the drive circuit part by irradiating the semiconductor film of the pixel matrix part and the drive circuit part with laser light to cause crystallization. A method of manufacturing a thin film transistor array substrate, comprising:

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