KR100963415B1 - Liquid crystal display device and method for manufacturing using the same - Google Patents

Abstract

The present invention discloses a liquid crystal display device and a method of manufacturing the same, which are prevented from being disconnected by a step of a line formed at a lower portion by forming a slit pattern in an area where signal lines cross each other in an array substrate of the liquid crystal display device. . The disclosed invention includes a gate bus line and a data bus line vertically arranged to apply a driving signal and a data signal; A thin film transistor disposed on a region where the gate bus line and the data bus line cross each other and serving as a switching function; A pixel electrode disposed on a unit pixel region in which the gate bus lines and the data bus lines are cross-aligned and defined; And a slit pattern disposed on a region where the drain electrode and the gate electrode of the thin film transistor are arranged to cross each other and a region where the gate bus line and the data bus line are arranged to cross each other.

Here, two to three slit patterns are disposed between the drain electrode and the gate electrode, and the number of the slit patterns disposed between the gate bus line and the data bus line is at least two. It is characterized by.

Pixel, Slit, Pattern, Single Line, Intersecting, LCD

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING USING THE SAME}

1 is a plan view showing a pixel structure of a liquid crystal display device according to the prior art.

2 is an enlarged view of a thin film transistor region of a liquid crystal display according to the related art.

3A is a cross-sectional view taken along the line AA ′ of FIG. 2;

3B is a cross-sectional view taken along the line BB ′ in FIG. 2;

4 is a plan view showing a pixel structure of a liquid crystal display device according to the present invention;

5 is an enlarged view of a thin film transistor region of a liquid crystal display according to the present invention;

6A is a cross-sectional view taken along the line CC ′ in FIG. 5.

6B is a cross-sectional view taken along the line D-D 'of FIG. 5;

* Description of the symbols for the main parts of the drawings *

201a and 201b: gate bus lines 203a and 203b: data bus lines

205: gate electrodes 206a and 206b: source / drain electrodes

207: active layer 209a, 209b: pixel electrode

220: slit pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a method of manufacturing the same, and more particularly, to prevent line open by forming a slit pattern on a region where lines cross each other in an array substrate of the liquid crystal display. A liquid crystal display device and a manufacturing method thereof are provided.

In general, as the modern society changes to the information socialization, the importance of the liquid crystal display module, which is one of the information display devices, is gradually increasing. Cathode ray tube (CRT), which is widely used so far, has many advantages in terms of performance and cost, but has many disadvantages in terms of miniaturization or portability.

On the other hand, the liquid crystal display device is a little expensive in terms of price, but has been attracting attention as an alternative means to overcome the disadvantages of the CRT because it has advantages such as miniaturization, light weight, thinness, low power, consumption.

The liquid crystal display device has a structure in which an array substrate on which thin film transistors are arranged and a color filter substrate on which red, green, and blue color filter layers are formed are bonded to each other with a liquid crystal interposed therebetween.

As described above, the array substrate and the color filter are manufactured by depositing and patterning a metal film and an insulating film according to several mask processes.

Generally, 5, 6, 7, and 8 mask processes were used to manufacture an array substrate of a liquid crystal display device. However, an increase in the mask process causes an increase in the manufacturing cost of the liquid crystal display device. As research is actively conducted, a four-mask process for simultaneously forming a channel layer and a source / drain electrode is performed.

First, a metal film is deposited on a transparent glass substrate, and then etched to form a gate bus line and a gate electrode, followed by applying a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film, followed by source / drain A second mask process of simultaneously depositing a metal film and subsequently etching to form a source / drain electrode and a channel layer at the same time; a third process of applying a protective film to protect the device when the source / drain electrode is completed; A mask process and a mask process are performed by depositing and etching an ITO transparent metal film on the substrate on which the protective film is formed to form a pixel electrode.

In order to successfully perform the four-mask process as described above, there is a method of etching a photoresist film by halftone using a halftone mask that simultaneously forms the source drain electrode and the active layer region. When exposing a film, the method of etching using the mask which inserted the slit-type pattern below the resolution is used.

In the above description, the four mask process steps are described. In the 4, 5, 6, and 7 mask processes, the gate bus lines and the data bus lines formed on the array substrate are vertically intersected and overlapped with each other. A constant step occurs by the line.                         

Since the step causes the opening of the data bus line and the source / drain electrodes in the manufacturing process of the array substrate, the pixel structure by various methods is studied to prevent this step.

1 is a plan view illustrating an array substrate structure of a liquid crystal display according to the related art.

As illustrated in FIG. 1, a plurality of gate bus lines 101a and 101b and data bus lines 103a and 103b are vertically intersected on a transparent insulating substrate to define a unit pixel area.

A thin film transistor (TFT), which is a switching element, is formed on a region where the gate bus lines 101a and 101b and the data bus lines 103a and 103b vertically cross each other, and a transparency is formed on a unit pixel region. The pixel electrodes 109a and 109b formed of ITO (Indium-Tin-Oxide) metal are arranged.

The gate bus lines 101a and 101b and the data bus lines 103a and 103b overlap each other, and a gate insulating layer and an active layer 107 are interposed between the two lines, and the active layer 107 is interposed between the gate bus lines 101a and 101b. The data bus line 103a and the source / drain electrodes 106a and 106b are disposed on the top.

The active layer 107 is composed of an amorphous silicon film and an n + amorphous silicon film. The active layer 107 is formed of a channel layer and an ohmic contact layer during the TFT formation process.

A protective film is coated on the data bus line 103a and the source / drain electrodes 106a and 106b to protect the devices formed on the array substrate. In order to electrically connect the pixel electrodes 109a and 109b and the drain electrode 106b, a contact hole is formed on the passivation layer, and the drain electrode 106b and the pixel electrode 109a are formed along the contact hole. 109b) is electrically connected.

The structure of the array substrate illustrated in the drawing has a form in which the active layer 107 is exposed to a predetermined distance on both sides of the data bus lines 103a and 103b, which is a source / drain electrode by a manufacturing method using a four mask process. 106a and 106b and the channel layer 107 are formed at the same time.

The gate bus lines 101a and 101b and the gate electrode 105 disposed on the array substrate have the data bus lines 103a and 103b and the drain electrode 106b with the active layer 107 interposed therebetween. ), It has a constant step at the boundary of the overlap area.

As described above, the step in the overlap region causes the open of the data bus lines 103a and 103b or the open of the drain electrode 106b. Therefore, in order to prevent this, the gate bus lines 101a and 101b have a structure having a constant groove 110 in a boundary area overlapping the data bus lines 103a and 103b.

2 is an enlarged view of a thin film transistor region of a liquid crystal display according to the related art.

As shown in FIG. 2, a TFT device is disposed in a region where the data bus line 103a and the gate bus line 101a vertically cross each other. The TFT and the gate bus line 101a for applying a driving signal The gate electrode 105 of the TFT is integrally formed and disposed.

A gate insulating layer and an active layer 107 are disposed on the gate electrode 105, and source / drain electrodes 106a and 106b overlap a portion of the gate electrode 105 on the active layer 107. It is arranged to be.

Particularly, when the drain electrode 106b overlaps the gate electrode 105 and contacts the pixel electrode 109a, a constant step exists due to the gate electrode 101a positioned below the drain electrode 106b. .

Similarly, even in a region where the gate bus line 101a and the data bus line 103a vertically intersect, the gate bus line 101a has a constant step between the gate insulating film and the active layer 107.

As shown in the figure, the reason why the predetermined groove 110 is formed in a region where the gate bus line 101a and the data bus line 103a overlap is that the data bus line 103a overlaps with the region. This is to minimize the step difference of the gate bus line 101a to prevent the data bus line 103a from being opened.

That is, when the metal film on which the data bus line 103a is formed overlaps with each other by forming a constant groove in the gate bus line 101a, the step is reduced in the groove formed in the gate bus line 101a so as to be deposited slowly. It is.

However, in the pixel structure of the liquid crystal display device having the above structure, even if a groove is formed on the gate bus line in the data bus line region overlapping with the gate bus line, the metal of the data bus line is deposited. There is a problem that is open by the step (open).

In particular, the array substrate manufactured by the four mask process has a lower active layer (Active) than the width of the source / drain electrodes and data bus lines of the thin film transistor, unlike the five mask process. There is a problem that causes a line break because the step difference is much larger.

FIG. 3A is a cross-sectional view taken along the line AA ′ of FIG. 2 and illustrates lower cross-sections of the source / drain electrodes 106a and 106b of the thin film transistor formed on the array substrate of the liquid crystal display.

A gate electrode 105 is formed on the transparent insulating substrate 100, and an active layer including a gate insulating film 102, an amorphous silicon film 107a, and a doped silicon film 107b is formed on the gate electrode 105. 107 are stacked in this order, and the drain electrode 106b is formed on the doped silicon film 107b.

The drain electrode 106b is formed to have a predetermined inclination by the gate electrode 105 formed at a lower portion, and such a step causes a problem of disconnecting the drain electrode 106b formed at the upper portion.

FIG. 3B is a cross-sectional view of the B-B ′ region of FIG. 2 vertically cut, and illustrates a region in which the gate bus line 101a and the data bus line 103a vertically cross each other.                         

A gate bus line 101a is formed on the transparent insulating substrate 100, and a gate insulating film 104 and an active layer 107 are sequentially deposited on the gate bus line 101a.

A data bus line 103a is formed along the active layer 107. The data bus line 103a is formed along the gate bus line 101a by the gate insulating layer 104 and the active layer 107. It can be seen that line 103a is disposed.

When the data bus lines 103a are also vertically intersected while overlapping the gate bus lines 101a, the data bus lines 103a are constant along the steps formed by the gate bus lines 101a when viewed in cross section. Slope causes line defects.

That is, as shown in FIG. 3B, even in a region where the gate bus lines and the data bus lines are vertically intersected, line disconnection occurs due to the step difference between the lines of the upper and lower layers.

As described above, when manufactured by the 4, 5, 6 mask process inevitably occurs in the upper and lower steps, the data bus line and the TFT electrode is very small width has a problem that the disconnection caused by the step.

According to the present invention, a slit pattern is formed between a region where a gate bus line and a data bus line intersect in a pixel structure of a liquid crystal display device, and a region where a source / drain electrode and a gate electrode of a thin film transistor intersect, thereby preventing disconnection defect due to a step difference. It is an object of the present invention to provide a liquid crystal display device and a method of manufacturing the same that can be prevented.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a gate bus line and a data bus line vertically arranged to apply a driving signal and a data signal; A thin film transistor disposed on a region where the gate bus line and the data bus line cross each other and serving as a switching function; A pixel electrode disposed on a unit pixel region in which the gate bus lines and the data bus lines are cross-aligned and defined; And a slit pattern disposed in an area between the gate electrode and the pixel electrode where the drain electrode and the gate electrode of the thin film transistor intersect, and an area where the gate bus line and the data bus line cross each other.
In addition, the liquid crystal display device manufacturing method of the present invention comprises the steps of depositing a metal film on a transparent insulating substrate and then forming a gate bus line, a gate electrode and a slit pattern by a photo process; A gate insulating film, an amorphous silicon film, a doped amorphous silicon film, and a source / drain electrode metal film are sequentially deposited on the substrate on which the gate bus line, the gate electrode, and the slit pattern are formed, and then etched to form a source / drain electrode and a data bus line. Forming a; Forming a contact hole by applying a protective film on the substrate on which the source / drain electrode and the data bus line are formed and then etching; And forming a pixel electrode by depositing and etching a transparent metal film on the substrate on which the contact hole is formed, wherein the slit pattern includes a region between the gate electrode and the pixel electrode where the drain electrode and the gate electrode of the thin film transistor intersect with each other; And are formed in regions where the gate bus lines and the data bus lines cross each other.
According to the present invention, when a gate bus line and a gate electrode are formed on a glass substrate of a liquid crystal panel, a disconnection defect due to a step between the gate bus line and the data bus line is formed by forming a slit pattern in the data bus line and the TFT electrode formation region. There is an advantage that can be prevented.

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Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view illustrating a pixel structure of a liquid crystal display device according to the present invention.

As illustrated in FIG. 4, a plurality of gate bus lines 201a and 201b and data bus lines 203a and 203b are vertically intersected on the transparent insulating substrate to define a unit pixel area.

In addition, a TFT, which is a switching element, is formed and disposed on a region where the gate bus lines 201a and 201b and the data bus lines 203a and 203b are vertically intersected, and the drain electrode 206b of the thin film transistor is formed. The slit pattern 220 is disposed between the gate electrode 205 and the pixel electrodes 209a and 209b in the region where the gate electrode 205 intersects.

In addition, a predetermined groove 210 is formed in the gate bus lines 201a and 201b in a region where the data bus lines 203a and 203b and the gate bus lines 201a and 201b cross each other. The data bus lines 203a and 203b cross the gate lines 201a and 201b through the grooves 210 formed in the gate bus lines 201a and 201b.
In the present invention, the slit pattern 220 is disposed in the groove 210, and the data lines 203a and 203b are disposed to overlap the groove 210 and the slit pattern 220. The pixel electrodes 209a and 209b made of transparent indium tin oxide (ITO) metal are arranged on the unit pixel region.

A gate insulating film and an active layer 207 are formed on the gate bus line 201a, and the data bus line 203a and source / drain electrodes 206a and 206b are disposed on the active layer 207. .

The active layer 207 is composed of an amorphous silicon film and an n ⁺ amorphous silicon film to form a channel layer and an ohmic contact layer.

When the data bus lines 203a and 203b and the source / drain electrodes 206a and 206b are formed, a protective film is coated to protect devices formed on the array substrate. A contact hole was formed on the passivation layer to electrically connect the pixel electrodes 209a and 209b to the drain electrode 206b, and then the drain electrode 206b and the pixel electrodes 209a and 209b were electrically connected to each other.

The structure of the array substrate shown in the drawing has a form in which the active layer 207 is exposed to both sides of the data bus lines 203a and 203b at a predetermined distance, which is the source / drain electrodes 206a and 206b in a four mask process. This is because the channel layer is formed simultaneously.

In the 4 mask process and the 5 mask process of the liquid crystal display device, a gate insulating film and an active layer 207 are interposed between the gate electrode 205 and the drain electrode 206b. Similarly, the gate bus line 201a and the data bus line ( In the region where the gate insulating film and the active layer 207 are interposed between 203a, a constant step is formed.

The slit pattern 220 is formed by simultaneously patterning the gate electrode 205 and the gate bus lines 201a and 201b on the transparent insulating substrate with respect to the crossing regions. As shown in the figure, the slit pattern 220 is disposed between the gate electrode 205 and the pixel electrodes 209a and 209b, and the drain electrode 206b crosses the slit pattern 220. In addition, the slit pattern 220 is disposed in the groove 210 region formed in the gate bus lines 201a and 201b crossing the data bus lines 203a and 203b so that the data bus lines 203a and 203b are grooved. Intersecting the slit pattern 220 formed in the (210) region.

The slit pattern 220 smoothes the stepped slope generated by the gate bus line 201a and the gate electrode 205, thereby preventing disconnection of the data bus lines 203a and 203b and the drain electrode 206b. .

When the drain electrode 206b and the pixel electrode 209 of the thin film transistor are contacted, the drain electrode 206b is disconnected due to the step of the lower gate electrode 205. The slit pattern 220 When the drain electrode 206b is formed, it has a gentle inclination to prevent the drain electrode 206b from being disconnected.

In addition, in FIG. 4, only one number of the slit patterns 220 is disposed in the intersection area, but in some cases, two or more slit patterns may be arranged at regular intervals. That is, a plurality of slit patterns 220 are formed along the data bus lines 203a and 203b intersecting the groove 210 regions formed in the gate bus lines 201a and 201b, or the gate electrode 205 and the pixel electrode ( A plurality of slit patterns 220 may be formed to overlap the drain electrode 206b between the 209a and 209b.

By forming and arranging a plurality of the slit patterns 220, the angle of inclination that is sharply inclined in the intersection region of the gate bus lines 201a and 201b or the gate electrode 205 can be maintained gently, thereby preventing line breakage. have.

However, when only one slit pattern 220 is formed and disposed, the slope of the slit pattern 220 may be adjusted to smoothly maintain the inclination in the cross region.

FIG. 5 is an enlarged view of the thin film transistor region of FIG. 4.

As shown in FIG. 5, the slit pattern 220 vertically crosses the lower portion of the data bus line 203a in a region where the gate bus line 201a and the data bus line 203a intersect. Doing.

The slit pattern 220 is disposed in an area in which the groove 210 of the gate bus line 201a is formed in order to reduce the step in the conventional pixel structure. However, the slit pattern 220 is formed along the line crossing the data bus line 203a. It may be disposed outside the region where the 210 is formed.

In the same manner, the slit pattern 220 is disposed in the region where the drain electrode crosses between the gate electrode 205 and the pixel electrode 209 so as to vertically cross the drain electrode 206b.

The slit pattern 220 is formed by simultaneously patterning the gate bus line 201a and the gate electrode 205 on the substrate.

In the drawing, the signal lines are centered around the pixel area, but in the overlapping and overlapping lines among the lines formed on the liquid crystal panel, a slit pattern may be formed and disposed to prevent disconnection.

FIG. 6A is a cross-sectional view of the CC ′ region of FIG. 5 vertically cut and crosses the drain electrode 206b of the thin film transistor when the gate electrode 205 is formed on the transparent insulating substrate 200. The slit pattern 220 was formed on the region to be formed.

A gate insulating film 202, an amorphous silicon film 207a, and a doped silicon film 207b are sequentially stacked on the substrate 200 on which the gate electrode 205 and the slit pattern 220 are formed. The source / drain electrodes 206a and 206b are formed on the silicon film 207b.

Since the active layer 207 is also present in the lower region of the drain electrode 206b edge region, the active layer 207 is removed in the five mask process.

The drain electrode 206b has a constant inclination due to the step of the gate electrode 205 formed below, but the inclined layer is smooth by the slit pattern 220 disposed to be spaced apart from the gate electrode 205 by a predetermined distance. You can see the dissolution.

As such, since the drain electrode 206b intersecting the gate electrode 205 is formed with a gentle inclination by the slit pattern 220, disconnection can be prevented.

Similarly, FIG. 6B is a cross-sectional view of the DD ′ region of FIG. 5 vertically separated from the gate bus line 201a in a region where the gate bus line 201a and the data bus line 203a are vertically intersected. The slit pattern 220 is formed in the region.

A gate insulating film 202 was formed on the substrate 200 on which the slit pattern 220 was formed, and active layers 207: 207a and 207b were sequentially formed on the gate insulating film 202. When the data bus line 203a is formed to be arranged to intersect with the gate bus line 201a, the data bus line 201a has a predetermined inclination due to the step of the gate bus line 201a, but is intersected by the slit pattern 220. The slope at is significantly reduced.

That is, since the slit pattern 220 serves as a buffer, the data bus line 203a is deposited along a gentle slope to prevent line disconnection.

In the present invention, since the array substrate of the liquid crystal display device overlaps the signal lines in a stacked form according to several mask processes, line breaks can be prevented by reducing the step by forming a slit pattern in the overlapping region.

As described in detail above, the present invention forms a slit pattern on an area where a gate bus line and a data bus line intersect among the lines layered on the array substrate of the liquid crystal display device, thereby preventing line disconnection. It works.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (8)

A gate bus line and a data bus line vertically intersecting to apply a driving signal and a data signal; A thin film transistor disposed on a region where the gate bus line and the data bus line cross each other and serving as a switching function; A pixel electrode disposed on a unit pixel region in which the gate bus lines and the data bus lines are cross-aligned and defined; And And a slit pattern disposed in an area between the gate electrode and the pixel electrode where the drain electrode and the gate electrode of the thin film transistor intersect, and an area where the gate bus line and the data bus line cross each other. Device. The liquid crystal display of claim 1, wherein at least two slit patterns are disposed in a region between the gate electrode and the pixel electrode. The liquid crystal display of claim 1, wherein at least two slit patterns are disposed in an area where the gate bus line and the data bus line cross each other. The liquid crystal display of claim 1, wherein the slit patterns are arranged to be alternately arranged on the drain electrode and the data bus line. Depositing a metal film on the transparent insulating substrate and then forming a gate bus line, a gate electrode, and a slit pattern by a photo process; A gate insulating film, an amorphous silicon film, a doped amorphous silicon film, and a source / drain electrode metal film are sequentially deposited on the substrate on which the gate bus line, the gate electrode, and the slit pattern are formed, and then etched to etch the source / drain electrode and the data bus line. Forming a; Forming a contact hole by applying a protective film on the substrate on which the source / drain electrode and the data bus line are formed and then etching; And Forming a pixel electrode by depositing and etching a transparent metal film on the substrate on which the contact hole is formed, Wherein the slit pattern is formed in an area between the gate electrode and the pixel electrode where the drain electrode and the gate electrode cross each other, and an area where the gate bus line and the data bus line cross each other. . delete 6. The method of claim 5, wherein at least two slit patterns are formed in an area between the gate electrode and the pixel electrode and an area where the gate bus line and the data bus line cross each other. The method of claim 5, wherein the slit pattern is formed to vertically overlap the drain electrode and the data bus line.

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