CN112164701A - Array substrate and display panel - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 239000010409 thin film Substances 0.000 claims abstract description 55
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000008358 core component Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229920002430 Fibre-reinforced plastic Polymers 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000011151 fibre-reinforced plastic Substances 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The application discloses an array substrate and a display panel, and relates to the technical field of display, wherein the array substrate comprises a substrate and a plurality of thin film transistors; the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer comprises a channel region, a first region and a second region which are respectively connected with two ends of the channel region in the length direction of the channel; at least one insulating layer is arranged between the source electrode and the active layer, the drain electrode and the active layer along the direction vertical to the substrate base plate, and the source electrode and the drain electrode are respectively connected with the first region and the second region through via holes penetrating through the insulating layers; and the dimension of the via hole in the width direction of the channel region adjacent to the via hole is larger than the channel width dimension of the channel region. Due to the fact that the via hole is stretched in the channel width direction, arc-shaped boundaries caused by the fact that the aperture is enlarged after the via hole is exposed are avoided, and therefore the problem that the channel length of a channel region fluctuates is solved; in addition, after the contact area of the via hole and the active layer is increased, the contact resistance is reduced, and the problem of current heating is solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In display technology, a TFT (Thin Film Transistor) is a core component of a display panel, and is generally fabricated on an array substrate, and includes: a gate, a source, a drain and an active layer; the source and the drain are respectively connected with the active layer through the via holes. When voltage is applied to the grid electrode, an electric field is formed between the grid electrode and the active layer, current carriers in the active layer start to move under the action of the electric field to generate current, and when the channel region reaches saturated current, the thin film transistor is started to realize conduction between the source electrode and the drain electrode.
Since the performance of the thin film transistor is closely related to the display effect, how to improve the TFT performance becomes a problem to be solved at present.
Disclosure of Invention
The invention provides an array substrate and a display panel, which can reduce the fluctuation of the channel length of a channel region in a TFT (thin film transistor), thereby improving the current heating phenomenon while ensuring the uniformity of the TFT.
In a first aspect, the present application provides an array substrate, including a substrate and a plurality of thin film transistors located on one side of the substrate; the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer comprises a channel region, a first region and a second region which are respectively connected with two ends of the channel region in the length direction of the channel;
at least one insulating layer is arranged between the source electrode and the active layer and between the drain electrode and the active layer along a direction vertical to the substrate base plate, and the source electrode and the drain electrode are respectively connected with the first region and the second region through via holes penetrating through the insulating layers; wherein the dimension of the via hole in the width direction of the channel region adjacent to the via hole is larger than the channel width dimension of the channel region.
In a second aspect, the present application further provides a display panel, including the array substrate provided in the first aspect.
Compared with the prior art, the array substrate and the display panel provided by the application at least realize the following beneficial effects:
in the array substrate and the display panel provided by the application, the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected with the active layer through via holes respectively. Because the size of the via hole in the width direction of the adjacent channel region is larger than the width of the channel region, namely, the via hole is stretched in the channel width direction of the channel region, the design mode can avoid the phenomenon that the aperture is enlarged to form a circular via hole after over-control exposure, thereby eliminating the fluctuation of the channel length of the channel region caused by a circular boundary and effectively improving the uniformity of each TFT. In addition, after the via hole is stretched along the width direction of the channel, the contact area between the via hole and the active layer is increased, the contact resistance is reduced, the problem of current heating is solved, and the device characteristics of the TFT are ensured.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a top view of a thin film transistor provided during the inventors' research;
fig. 2 is a film structure diagram of a thin film transistor according to an embodiment of the present disclosure;
FIG. 3 is a top view of the TFT of FIG. 2;
FIG. 4 is another top view of the TFT of the embodiment of FIG. 2;
fig. 5 is another top view of a thin film transistor provided during the inventors' research;
FIG. 6 is another top view of the TFT of the embodiment of FIG. 2;
FIG. 7 is another top view of the TFT of the embodiment of FIG. 2;
FIG. 8 is another top view of the TFT of the embodiment of FIG. 2;
fig. 9 is another top view of the tft provided in the embodiment of fig. 2;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a top view of a thin film transistor provided in the course of the inventors' study. Referring to fig. 1, as a core component in a display panel, a thin film transistor includes: the active layer T4 'includes a first region 01', a second region 02', and a channel region GD', and the source and drain electrodes are electrically connected to the first region 01 'and the second region 02' of the active layer T4 'through a via O'. However, the inventor has found that the aperture of the via hole O 'is enlarged after exposure treatment in the process of manufacturing the TFT, the via hole O' originally designed to be rectangular is actually manufactured to be close to a circle, and the circular boundary causes the channel length L 'of the channel region GD' to fluctuate, which affects the uniformity of the TFT. On the other hand, under the condition that the sizes of the first area 01 'and the second area 02' are not changed, the contact resistance at the via hole O 'is in negative correlation with the aperture of the via hole O', namely the smaller the aperture of the via hole O ', the larger the contact resistance at the via hole O'; therefore, when the aperture of the via hole O 'is small, current flowing through the via hole O' may have a risk of heat generation and may adversely affect device characteristics of the TFT.
In view of the foregoing, the present application provides an array substrate and a display panel, which can reduce fluctuation of a channel length of a channel region in a TFT, thereby improving a current heating phenomenon while ensuring uniformity of the TFT.
The following detailed description is to be read in connection with the drawings and the detailed description.
Fig. 2 is a film structure diagram of a thin film transistor according to an embodiment of the present disclosure, and fig. 3 is a top view of the thin film transistor according to the embodiment of fig. 2. Referring to fig. 2 and 3, the present application provides an array substrate 10, which includes a substrate 101 and a plurality of thin film transistors T disposed on one side of the substrate 101; the thin film transistor T includes an active layer T1, a gate electrode T2, a source electrode T3, and a drain electrode T4, and the active layer T1 includes a channel region GD and first and second regions 01 and 02 connected to both ends of the channel region GD in a channel length direction Y, respectively;
at least one insulating layer 102 is included between the source and drain electrodes T3 and T4 and the active layer T1 in a direction perpendicular to the base substrate 101, and the source and drain electrodes T3 and T4 are connected to the first and second regions 01 and 02, respectively, through vias o penetrating through the insulating layer 102; a dimension W1 of the via hole O in the width direction X of the adjacent channel region GD is larger than a channel width dimension W of the channel region GD.
In the present embodiment, the array substrate 10 includes a substrate 101 and a plurality of thin film transistors T located at one side of the substrate 101, and the substrate 101 may be formed of a polymer material, such as glass, Polyimide (PI), Polycarbonate (PC), or glass Fiber Reinforced Plastic (FRP), which may be transparent, translucent, or opaque; the thin film transistor T is generally divided into a top gate structure and a bottom gate structure according to the position of the gate electrode T2, and the present embodiment will be described by taking a thin film transistor of a bottom gate structure as an example.
Specifically, the thin film transistor T includes an active layer T1, a gate electrode T2, a source electrode T3, and a drain electrode T4, and the active layer T1 includes a channel region GD, which is a region overlapping with the gate electrode T2 in the active layer T1, and first and second regions 01 and 02 connected to both ends of the channel region GD in a channel length direction Y, respectively. At least one insulating layer 102 is included between the source and drain electrodes T3 and T4 and the active layer T1 in a direction perpendicular to the base substrate 101, i.e., a Z direction shown in fig. 2, and the source and drain electrodes are electrically connected to the first and second regions 01 and 02, respectively, through vias O penetrating the insulating layer 102. When a voltage is applied to the gate T2, an electric field is formed between the gate T2 and the active layer T1, carriers in the active layer T1 start to move under the action of the electric field to generate a current, and when the channel region GD reaches a saturation current, the thin film transistor T is turned on, so that conduction between the source T3 and the drain T4 is achieved.
It should be understood that although the active layer T1 described above may include the first region 01, the second region 02 and the channel region GD, the first region 01, the second region 02 and the channel region GD are an integral part of the active layer T1, and adjacent regions are not substantially separated from each other. In this embodiment, the active layer T1 may be made of a low temperature polysilicon material or an oxide semiconductor material, the low temperature polysilicon thin film transistor has the advantages of high switching speed and low power consumption, and the oxide semiconductor thin film transistor has a low off-state current, which is beneficial to reducing the storage capacitance and reducing the power consumption.
It should be noted that the film structure of the thin film transistor shown in fig. 2 is only an example, and in some other embodiments of the present application, the array substrate 10 may further include other films, which is not specifically limited in this application.
Further, as shown in fig. 3, a dimension W1 of the via hole O in the width direction X of the channel region GD adjacent thereto is larger than a channel width dimension W of the channel region GD. It should be understood that the channel length L of the channel region GD is a length in a direction connecting the first and second regions 01 and 02, and the channel width W of the channel region GD is a length of the channel region GD in a direction in which the gate T2 extends in fig. 3.
Since the corner positions of the via hole in the related art are rounded to form an arc during actual manufacturing, the edges of the via hole are no longer straight lines, so that the distance between the edge L1 of the via hole O adjacent to the channel region GD and the channel region GD is not equal everywhere, but the present embodiment ensures that the distance between the edge L1 and the channel region GD is equal everywhere by stretching the via hole O into a long strip shape. Specifically, in the present embodiment, the dimension W1 of the via hole O in the width direction X of the adjacent channel region GD is greater than the channel width dimension W of the channel region GD, which is equivalent to stretching the via hole O in the width direction X of the channel region GD, and this design method can avoid the aperture from being enlarged after exposure to form a circular via hole, thereby eliminating the fluctuation of the channel length L of the channel region GD caused by the arc boundary, and effectively improving the uniformity of each TFT. On the other hand, under the condition that the sizes of the first region 01 and the second region 02 are not changed, the contact resistance at the via hole O is in negative correlation with the aperture of the via hole O, that is, the smaller the aperture of the via hole O is, the larger the contact resistance at the via hole O is, and in this embodiment, after the via hole O is stretched in the channel width direction X, the larger the aperture thereof is, and the contact area with the active layer T1 is also increased, so that the contact resistance is reduced, thereby solving the problem of current heating, and being beneficial to ensuring the device characteristics of the TFT.
Of course, the channel region GD of the thin film transistor T in the array substrate 10 may have various shapes, fig. 3 only illustrates a case where the channel region GD is rectangular, but in some other embodiments of the present application, the channel region GD may also be U-shaped or S-shaped, and the present application does not limit the specific shape of the channel region GD, but the determination manner of the width and the length of the channel region GD with other shapes is similar to that in fig. 3, and is not repeated here.
In a direction perpendicular to the substrate base plate 101, the via hole O includes a first end surface S1 and a second end surface S2 which are oppositely disposed, the second end surface S2 is located on a side of the first end surface S1 away from the substrate base plate 101, and a dimension of the via hole O in the width direction X of the channel region GD adjacent thereto is a dimension of the first end surface S1 in the width direction X of the channel region GD adjacent thereto.
Specifically, referring to fig. 2 and 3, the via O connecting the source, the drain and the active layer T1 along a direction perpendicular to the substrate base 101 includes a first end surface S1 and a second end surface S2 disposed opposite to each other, the first end surface S1 is located on a side of the second end surface S2 close to the substrate base 101, that is, the first end surface S1 of the via O contacts the active layer T1. Due to the limitation of the manufacturing process, the sizes of the first end surface S1 and the second end surface S2 may be different, and the shape of the first end surface S1 may affect the channel length L of the channel region GD. For example, if the aperture of the via hole O is enlarged after exposure, and the edge of the first end surface S1 near the channel region GD is curved, the edge of the channel region GD is also curved, which results in different channel lengths L at different positions of the channel region GD. Therefore, in the present embodiment, the dimension of the first end surface S1 in the width direction X of the channel region GD is defined as the dimension of the via hole O in the width direction X of the channel region GD adjacent thereto, and the first end surface S1 of the via hole O is stretched in the channel width direction X of the channel region GD, so that, even if the via hole O is exposed during the process of manufacturing the thin film transistor T, the first end surface S1 is not rounded due to the enlargement of the aperture, and the channel length L of the channel region GD is not fluctuated due to the rounded boundary of the first end surface S1, thereby improving the uniformity of the thin film transistor T.
Fig. 4 is another top view of the tft provided in the embodiment of fig. 2. Referring to fig. 3 and 4, the orthogonal projection of the via O on the active layer T1 along the direction perpendicular to the substrate base 101 is rectangular or rounded rectangular.
In this embodiment, an orthogonal projection of the first end surface S1 of the via hole O on the active layer T1 in a direction perpendicular to the substrate base 101 may be a long strip shape, that is, the first end surface S1 may be stretched into a long strip shape along the width direction X of the channel region GD, where the long strip shape includes a rectangle or a rounded rectangle. It can be understood that, in the channel length direction Y of the channel region GD, the first end surface S1 includes a first edge L1 disposed adjacent to the channel region GD, the channel region GD includes a second edge L2 adjacent to the first edge L1, and when the first end surface S1 is rectangular or rounded rectangular, the first edges L1 on both sides of the channel region GD are both straight and parallel to the second edge L2 of the channel region GD, so that it can be ensured that the first edge L1 does not expand into an arc shape after exposure, thereby further ensuring the uniformity of the thin film transistor T.
Optionally, with continued reference to fig. 3, a dimension W1 of the via O in the width direction X of the adjacent channel region GD is greater than or equal to 2 times a dimension W2 of the via O in the length direction Y of the adjacent channel region GD.
It should be appreciated that via sizes are currently not amenable to refinement and miniaturization due to design, exposure, and etching processes. Specifically, in the process of manufacturing the via hole, the size of the light transmission area of the mask plate can only be larger than or equal to the resolution of the exposure machine, incident light in the exposure process can be diffracted at the edge of the light transmission area of the mask plate, and the diffracted light is expanded to the exposure edge position of the photoresist, so that the exposure size of the photoresist is larger, and the gradient of the exposure edge is too gentle. Further, when the etching process is performed, not only the insulating layer needs to be etched to form the via hole, but also a portion of the photoresist needs to be etched, so that the size of the via hole is further increased. In this embodiment, if the dimension W1 of the via hole O in the channel region width direction X adjacent to the via hole O is closer to the dimension W2 of the via hole O in the channel region length direction Y adjacent to the via hole O, a circular via hole with a larger dimension is formed after the exposure process, and the channel length of the channel region GD changes due to the circular boundary.
Therefore, in this embodiment, the dimension W1 of the via hole O in the width direction X of the adjacent channel region is greater than or equal to 2 times the dimension W2 of the via hole O in the length direction Y of the adjacent channel region, and by increasing the length-width ratio of the aperture of the via hole O, the arc-shaped boundary of the strip-shaped via hole O after exposure does not appear, so that the channel lengths of the channel regions GD are equal everywhere, and the uniformity of the thin film transistor T is improved.
Alternatively, referring to fig. 3, a projection of the via hole O along the length direction Y of the channel region GD adjacent to the via hole O covers an end portion D of the channel region GD adjacent to the via hole O, which is the end portion D of the channel region in the length direction Y.
Specifically, in the present embodiment, the projection of the via hole O in the length direction Y of the adjacent channel region GD covers the end portion D of the adjacent channel region GD, in other words, any straight line passing through the channel region GD in the length direction Y of the channel region GD also passes through the via holes O on both sides of the channel region GD.
Fig. 5 shows another top view of a thin film transistor provided during the inventors' research. As shown in fig. 5, the inventors found in the research process that if the projection of the via hole O along the length direction Y of the adjacent channel region GD only partially overlaps the end portion D of the adjacent channel region GD, the channel length of the channel region GD corresponding to the overlapped portion may be smaller than the channel length of the channel region GD corresponding to the non-overlapped portion as the size of the via hole O is enlarged in the exposure process, which seriously affects the uniformity of the thin film transistor T. Therefore, in the present embodiment, by enabling the projection of the via hole O along the length direction Y of the channel region GD adjacent to the via hole O to cover the end portion D of the channel region GD adjacent to the via hole O, it is ensured that the exposed via hole O does not cause the channel length L of the channel region GD at the overlapped portion and the non-overlapped portion to be different, so as to solve the problem of poor uniformity of the TFT channel length.
In addition, it should be understood that the source, drain and active layers T1 located at different layers are electrically connected to the active layer T1 through a via hole O formed in the insulating layer 102, and the projection of the via hole O along the length direction Y of the channel region GD adjacent to the via hole O covers the end D of the channel region GD adjacent to the via hole O, which is also beneficial to ensure effective conduction between the source and drain. Optionally, as shown in fig. 2, the via hole O is formed in the etching stopper layer ESL, and the etching stopper layer ESL completely covers a side of the channel region GD away from the substrate 101, so that the channel region GD is not electrically conducted when the first region 01 and the second region 02 are electrically conducted, and the influence of external environmental factors and etching damage of the source and drain electrodes on the channel can be effectively reduced, and particularly when the active layer T1 is made of a metal oxide, the stability of the oxide TFT can be greatly improved by the etching stopper layer ESL.
Optionally, with continued reference to fig. 3, the first region 01 and the second region 02 are arranged along a first direction and respectively extend along a second direction, the channel region GD extends along the first direction and is located between the first region 01 and the second region 02, and a dimension W3 of the first region 01 and the second region 02 along the second direction is greater than a dimension W of the channel region GD along the second direction;
the first direction is a channel length direction Y of the channel region GD, and the second direction is a channel width direction X of the channel region GD.
In this embodiment, the active layer T1 may be an i-shaped design with two wide ends and a narrow middle portion. Specifically, the channel region GD in the active layer T1 extends in a first direction, the first and second regions 01 and 02 are arranged side by side in the first direction and both extend in a second direction, and the active layer T1 is located between the first and second regions 01 and 02. On the one hand, in the embodiment, after the first region 01 and the second region 02 on the two sides of the channel region GD are stretched along the channel width direction X of the channel region GD, the width of the first region 01 and the second region 02 in the second direction is greater than the channel width W, so that the via hole O with the first end surface S1 being a long strip is conveniently formed, and the problem of inconsistent channel length L caused by the aperture expansion of the via hole O during exposure is avoided. On the other hand, the width W of the channel region GD often depends on the application scenario of the TFT device, for example, in a logic application, the channel width W is usually designed to be narrow, and in this case, if the width W3 of the first region 01 and the second region 02 is also reduced to the same width as the channel region GD, a limitation is imposed on the contact area between the source and the drain and the first region 01 and the second region 02, and the performance of the thin film transistor T is greatly affected. Therefore, in the embodiment, by adopting the i-shaped design, the problem of poor uniformity of the GD channel length of the channel region is solved, and the contact areas of the source and the drain with the first region 01 and the second region 02 are increased, so that the contact resistance is reduced, the starting voltage is reduced, the current heating phenomenon is avoided, the reliability and the yield of the thin film transistor T are effectively improved, and the application scenes of the TFT device are further widened.
In addition, the dimension W3 of the first region 01 and the second region 02 in the second direction is greater than the dimension W of the channel region GD in the second direction, so that the first end surface S1 of the via hole O can be ensured to completely fall into the first region 01/second region 02, over-etching caused by the fact that the via hole O exceeds the first region 01/second region 02 is avoided, the risk of short circuit is reduced, and the performance of the thin film transistor is further optimized.
In this embodiment, as shown in fig. 3, the second region 02 has the same size in the second direction as the first region 01. Obviously, by providing the first and second regions 01 and 02 to have the same size in the width direction X of the channel region GD, it is not only advantageous to improve the uniformity of the thin film transistor T, but also to simplify the manufacturing process of the active layer T1, thereby further simplifying the manufacturing process of the thin film transistor T.
Alternatively, as shown in fig. 3, a projection of the first zone 01 in the longitudinal direction Y of the channel zone GD coincides with a projection of the second zone 02 in the longitudinal direction Y of the channel zone GD.
In this embodiment, a projection of the first region 01 along the length direction Y of the channel region GD coincides with a projection of the second region 02 along the length direction Y of the channel region GD, that is, in the width direction X of the channel region GD, the first region 01 and the second region 02 have the same size, and two opposite edges of the first region 01 are aligned with two opposite edges of the second region 02, so that the design further improves the uniformity of the thin film transistor T.
Further, the two vias O are symmetrical with respect to the channel region GD in the present embodiment.
Specifically, along the width direction X and the length direction Y of the channel region GD, the first via hole O1 and the second via hole O2 on both sides of the channel region GD have the same size, that is, the contact areas of the first via hole O1 and the second via hole O2 are the same as those of the first region 01 and the second region 02 in the active layer T1, and the contact impedances are also the same, so that not only is good electrical contact performance between the source and drain T4 and the active layer T1 ensured, but also symmetry of the thin film transistor T structure is further realized.
Fig. 6 is another top view of the tft provided in the embodiment of fig. 2. Alternatively, as shown in fig. 6, a projection of the first region 01 in the longitudinal direction Y of the channel region GD and a projection of the second region 02 in the longitudinal direction Y of the channel region GD overlap each other, and the two vias O are offset in the width direction X of the channel region GD.
Specifically, the via hole O includes a first via hole O1 and a second via hole O2 disposed on two sides of the channel region GD, a projection of the first region 01 along the length direction Y of the channel region GD coincides with a projection of the second region 02 along the length direction Y of the channel region GD, and the first via hole O1 and the second via hole O2 are arranged in a staggered manner in the width direction X of the channel region GD. In this embodiment, the staggered arrangement of the first via O1 and the second via O2 means: along the length direction Y of the channel region GD, a projection of one end D of the first/second via O1/O2 is located between two ends D of the second/first via O. On one hand, the first via hole O1 and the second via hole O2 are arranged in a staggered mode, so that the wiring difficulty of the source and drain electrodes T4 can be reduced, and the intervals among all the wirings are increased; on the other hand, the alignment of the ends D of the first and second regions 01 and 02 of the active layer T1 allows the thin film transistor T to have a symmetrical structure.
In order to ensure effective conduction between the source and the drain, projections of the first via O1 and the second via O2 in the longitudinal direction Y of the adjacent channel region GD in the present embodiment cover the end D of the channel region GD.
Fig. 7 is another top view of the tft provided in the embodiment of fig. 2. Alternatively, as shown in fig. 7, the first region 01 and the second region 02 are offset in the width direction X of the channel region GD, and the two vias O are offset in the width direction X of the channel region GD.
In this embodiment, the first region 01 and the second region 02 on both sides of the channel region GD are dislocated in the width direction X of the channel region GD, that is, along the length direction Y of the channel region GD, the projection of one end D of the first region 01/the second region 02 is located between the two ends D of the second region 02/the first region 01, so that the wiring space of the source/drain T4 can be increased; meanwhile, the first via hole O1 and the second via hole O2 are also arranged in a staggered manner in the width direction X of the channel region GD, so that the wiring space of the source and the drain is further increased, and the undersize of the distance between the wires is avoided.
Fig. 8 is another top view of the tft provided in the embodiment of fig. 2. In this embodiment, as shown in fig. 8, the first region 01 and the second region 02 are arranged along a first direction and respectively extend along a second direction, and the channel region GD extends along a third direction and is located between the first region 01 and the second region 02; the first direction intersects the second direction, and the third direction intersects the width direction of the channel region and is not perpendicular to the width direction.
Optionally, in this embodiment, the second direction is a width direction X of the channel region GD, and the first direction H is perpendicular to the second direction.
Specifically, in an embodiment of the present application, the channel region GD may be obliquely disposed between the first region 01 and the second region 02, and the first region 01 and the second region 02 are still arranged along the first direction and respectively extend along the second direction, so that the overlapping length of the active region and the gate electrode T2 is increased, that is, the effective channel length of the channel region GD is increased, and thus, the performance of the thin film transistor is improved.
Optionally, with continued reference to fig. 8, the via O includes a first via O1 and a second via O2, the drain T4 is connected to the first region 01 through the first via O1, and the source T3 is connected to the second region 02 through the second via O2;
the first via O1 is offset from the second via O2 in the a direction, and the channel region GD is inclined in the a direction along the direction in which the second via O2 points to the first via O1, and the a direction is parallel to the width direction X of the channel region GD.
In this embodiment, in the direction in which the second via O2 points to the first via O1, the channel region GD is inclined in the a direction, and the first via O1 and the second via O2 located on both sides of the channel region GD are disposed in a staggered manner, at this time, among a plurality of straight lines that pass through the first region 01 in the length direction Y of the channel region GD, at least one straight line that does not pass through the second region 02 exists, and among a plurality of straight lines that pass through the first via O1 in the length direction Y of the channel region GD, at least one straight line that does not pass through the second via O2 exists, and optionally, the first via O1 is displaced in the a direction with respect to the second via O2. By the design, the effective length of the channel region GD can be increased under the condition that the distance between the first region 01 and the second region 02 is not changed, and meanwhile, the wiring space of the source and drain electrodes T4 is also increased.
Of course, the a direction may be the one shown in fig. 8, or another direction opposite to the one shown in fig. 8 may be the a direction. In this embodiment, projections of the first via hole O1 and the second via hole O2 along the length direction Y of the channel region GD cover the end portion D of the channel region GD, and details thereof are omitted.
Fig. 9 is another top view of the tft provided in the embodiment of fig. 2. Optionally, as shown in fig. 9, the via hole O includes a first via hole O1 and a second via hole O2, the drain T4 is connected to the first region 01 through the first via hole O1, and the source T3 is connected to the second region through the second via hole O2;
the first via O1 is offset in the a direction with respect to the second via O2, and the channel region GD is inclined in the b direction along the direction in which the second via O2 points to the first via O1, the a direction is parallel to the width direction X of the channel region, the b direction is parallel to the width direction X of the channel region, and the a direction is opposite to the b direction.
Compared with the embodiment shown in fig. 8, the difference between the embodiment shown in fig. 9 and the embodiment shown in fig. 8 is that the offset direction of the first via O1 with respect to the second via O2 is different from the inclination direction of the channel region GD, and this design can not only increase the effective length of the channel region GD without changing the distance between the first region 01 and the second region 02, but also increase the wiring space of the source/drain T4. In addition, in this embodiment, the first via hole O1/the second via hole O2 and the first region 01/the second region 02 are stretched and lengthened along the width direction X of the channel region GD, so that the channel region GD can be obliquely arranged, and when different requirements are required for the size of the channel region GD, different channel lengths and widths can be realized by adjusting the inclination angle of the channel region GD. For example, when it is necessary to increase the width-to-length ratio of the channel region GD, the channel width W may be increased, and the inclination of the channel region GD may be decreased, where decreasing the inclination of the channel region GD means increasing the angle α between the channel region length direction Y and the channel region width direction X, where α is an acute angle.
Alternatively, referring to fig. 2 and fig. 3, along the direction perpendicular to the substrate base plate 101, the area of the orthogonal projection of the via hole O on the active layer T1 is a1, and the areas of the first region 01 and the second region 02 are a2, wherein,
in the present embodiment, the via hole O includes a first end surface S1 and a second end surface S2 disposed opposite to each other in a direction perpendicular to the substrate base plate 101, wherein the first end surface S1 near the active layer T1 side is in contact with the first region 01/the second region 02. Since the source and the drain are made of metal materials, the active layer T1 is made of a semiconductor material, and the semiconductor material is generally a non-metal material, when the source and the drain T4 and the active layer T1 located in different film layers are connected through the via hole O, a contact resistance exists at a contact surface (i.e., a position of the first end surface S1) between the source and the drain and the active layer T1. As can be seen from the formula I — U/R, when the voltage is constant, the current decreases with the increase of the resistance, so that it is required to reduce the contact resistance between the source/drain T4 and the active layer T1 as much as possible to obtain a larger on-current at a lower Vds.
It should be understood that the area of the positive projection of the via hole O on the active layer T1, that is, the area of the first end face S1, is kept constant in the area S2 of the first region 01/second region 02, and the area of the first end face a1 in the via hole O is negatively related to the contact resistance, that is, the smaller a1/a2 is, the larger the contact resistance is. Therefore, in order to form good contact between the source T3 and the drain T4 and the active layer T1, in this embodiment, a1/a2 > 2/3 is provided to enhance the characteristics of the contact region between the source T4 and the active layer T1, ensure the effectiveness of the thin film transistor T, and improve the display effect of the display panel.
Illustratively, increasing the area ratio of the first end surface S1 to the first region 01/the second region 02 can be achieved by increasing the area a1 of the first end surface S1, and the problem of current heating can be solved by reducing the contact resistance of the source and drain electrodes T4 and the active layer T1, so that the service life of the TFT device is prolonged.
In this embodiment, please refer to FIG. 3, the channel width of the channel region GD is w, and the channel length of the channel region GD is l, wherein w/l is greater than or equal to 1/2.
The width-to-length ratio w/l of the channel region GD is one of important parameters of the thin film transistor T, and may be implemented by adjusting the width of the channel region GD, or adjusting the length of the channel region GD, or adjusting both the width and the length of the channel region GD. On the one hand, the smaller the width-to-length ratio W/l, the larger the forward current of the thin film transistor T, so when the thin film transistor T is used as a driving tube in a pixel circuit, the width-to-length ratio is usually increased by increasing the channel width W or decreasing the channel length, but the leakage current of the thin film transistor T increases with the decrease of the channel length, and the channel resistance of the thin film transistor T increases with the increase of the channel width W. In the embodiment, w/l is not less than 1/2, so that the on-current of the thin film transistor T when the thin film transistor T is conducted can be reduced, and the driving capability of the thin film transistor T is ensured, thereby optimizing the performance of the thin film transistor T.
Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 10, the display panel 100 provided in this embodiment includes the array substrate 10 provided in the above embodiment. The embodiment of fig. 10 only takes a mobile phone as an example to describe the display panel 100, and it should be understood that the display panel 100 provided in the embodiment of the present invention may be a display panel 100 with other display functions, such as a computer, a television, a vehicle-mounted display device, etc., and the present invention is not limited thereto. The display panel 100 provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the array substrate 10 in the foregoing embodiments, which is not repeated herein.
According to the embodiments, the array substrate and the display panel provided by the application at least achieve the following beneficial effects:
in the array substrate and the display panel provided by the application, the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected with the active layer through via holes respectively. Because the size of the via hole in the width direction of the adjacent channel region is larger than the width of the channel region, namely, the via hole is stretched in the channel width direction of the channel region, the design mode can avoid the phenomenon that the aperture is enlarged to form a circular via hole after over-control exposure, thereby eliminating the fluctuation of the channel length of the channel region caused by a circular boundary and effectively improving the uniformity of each TFT. In addition, after the via hole is stretched along the width direction of the channel, the contact area between the via hole and the active layer is increased, the contact resistance is reduced, the problem of current heating is solved, and the device characteristics of the TFT are ensured.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (17)
1. The array substrate is characterized by comprising a substrate base plate and a plurality of thin film transistors positioned on one side of the substrate base plate; the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer comprises a channel region, a first region and a second region which are respectively connected with two ends of the channel region in the length direction of the channel;
at least one insulating layer is arranged between the source electrode and the active layer and between the drain electrode and the active layer along a direction vertical to the substrate base plate, and the source electrode and the drain electrode are respectively connected with the first region and the second region through via holes penetrating through the insulating layers; wherein the dimension of the via hole in the width direction of the channel region adjacent to the via hole is larger than the channel width dimension of the channel region.
2. The array substrate of claim 1, wherein the via hole comprises a first end face and a second end face which are oppositely arranged along a direction perpendicular to the substrate base plate, the second end face is located on a side of the first end face away from the substrate base plate, and a dimension of the via hole in a width direction of the channel region adjacent to the via hole is a dimension of the first end face in a width direction of the channel region adjacent to the via hole.
3. The array substrate of claim 1, wherein an orthographic projection of the via hole on the active layer is rectangular or rounded rectangular along a direction perpendicular to the substrate.
4. The array substrate of claim 3, wherein the dimension of the via in the channel region width direction adjacent to the via is greater than or equal to 2 times the dimension of the via in the channel region length direction adjacent to the via.
5. The array substrate of claim 1, wherein the projection of the via hole along the length direction of the channel region adjacent to the via hole covers the end of the channel region adjacent to the via hole, and the end is the end of the channel region in the length direction.
6. The array substrate of claim 1, wherein the first region and the second region are arranged along a first direction and respectively extend along a second direction, the channel region extends along the first direction and is located between the first region and the second region, and a dimension of the first region and the second region along the second direction is larger than a dimension of the channel region along the second direction;
the first direction is a channel length direction of the channel region, and the second direction is a channel width direction of the channel region.
7. The array substrate of claim 6, wherein the second region has a dimension along the second direction that is equal to a dimension of the first region along the second direction.
8. The array substrate of claim 7, wherein a projection of the first region along a length direction of the channel region coincides with a projection of the second region along a length direction of the channel region.
9. The array substrate of claim 1, wherein two of the vias are symmetric about the channel region.
10. The array substrate of claim 1, wherein a projection of the first region along the length direction of the channel region coincides with a projection of the second region along the length direction of the channel region, and the two vias are offset in the width direction of the channel region.
11. The array substrate of claim 1, wherein the first region and the second region are offset in a width direction of the channel region, and wherein the two vias are offset in the width direction of the channel region.
12. The array substrate of claim 1, wherein the first region and the second region are arranged along a first direction and respectively extend along a second direction, and the channel region extends along a third direction and is located between the first region and the second region; wherein the first direction crosses the second direction, and the third direction crosses the width direction of the channel region and is not perpendicular to the width direction.
13. The array substrate of claim 1, wherein the via comprises a first via and a second via, the drain is connected to the first region through the first via, and the source is connected to the second region through the second via;
the first via hole is staggered relative to the second via hole in the direction a, the channel region inclines to the direction a along the direction in which the second via hole points to the first via hole, and the direction a is parallel to the width direction of the channel region.
14. The array substrate of claim 1, wherein the via comprises a first via and a second via, the drain is connected to the first region through the first via, and the source is connected to the second region through the second via;
the first via hole is staggered in the direction a relative to the second via hole, the channel region inclines towards the direction b along the direction in which the second via hole points to the first via hole, the direction a is parallel to the width direction of the channel region, the direction b is parallel to the width direction of the channel region, and the direction a is opposite to the direction b.
15. The array substrate of claim 1, wherein an area of an orthographic projection of the via hole on the active layer is A1, and an area of the first region and the second region is A2, in a direction perpendicular to the substrate, wherein,
16. the array substrate of claim 1, wherein the channel width dimension of the channel region is w, the channel length dimension of the channel region is l, and w/l is greater than or equal to 1/2.
17. A display panel comprising the array substrate of any one of claims 1 to 16.
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