US20100038803A9 - Low fabrication cost, high performance, high reliability chip scale package - Google Patents

Low fabrication cost, high performance, high reliability chip scale package Download PDF

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Publication number
US20100038803A9
US20100038803A9 US11/930,210 US93021007A US2010038803A9 US 20100038803 A9 US20100038803 A9 US 20100038803A9 US 93021007 A US93021007 A US 93021007A US 2010038803 A9 US2010038803 A9 US 2010038803A9
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United States
Prior art keywords
layer
copper pillar
surface
metal
pad
Prior art date
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Granted
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US11/930,210
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US20080099928A1 (en
US8178967B2 (en
Inventor
Jin-Yuan Lee
Ming-Ta Lei
Ching-Cheng Huang
Chuen-Jye Lin
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Qualcomm Inc
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Megica Corp
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Publication date
Priority to US09/953,525 priority Critical patent/US6642136B1/en
Priority to US10/638,454 priority patent/US6917119B2/en
Priority to US11/136,650 priority patent/US7338890B2/en
Application filed by Megica Corp filed Critical Megica Corp
Priority to US11/930,210 priority patent/US8178967B2/en
Assigned to MEGICA CORPORATION reassignment MEGICA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, CHING-CHENG, LEE, JIN-YUAN, LEI, MING-TA, LIN, CHUEN-JYE
Publication of US20080099928A1 publication Critical patent/US20080099928A1/en
Publication of US20100038803A9 publication Critical patent/US20100038803A9/en
Publication of US8178967B2 publication Critical patent/US8178967B2/en
Application granted granted Critical
Assigned to MEGIT ACQUISITION CORP. reassignment MEGIT ACQUISITION CORP. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: MEGICA CORPORATION
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEGIT ACQUISITION CORP.
Application status is Active legal-status Critical
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    • H05K2203/05Patterning and lithography; Masks; Details of resist
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    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Description

  • This application is a continuation of application Ser. No. 10/136,650, filed on May 24, 2005, now pending, which is a division of application Ser. No. 10/638,454, filed on Aug. 11, 2003, now U.S. Pat. No. 6,917,119, which is a division of application Ser. No. 09/953,525, filed on Sep. 17, 2001, now U.S. Pat. No. 6,642,136.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for semiconductor devices.
  • 2. Description of the Prior Art
  • The creation of semiconductor devices, also referred to as Integrated Circuits (IC) has been made possible by the rapid development of supporting technologies such as photolithography and methods of etching. Most of these technologies have over the years had to address concerns created by a continued decrease in device dimensions and increase in device densities. This effort of creating improved performance devices does is not limited in its impact on the device itself but extends into the methods and packages that are used to further interconnect semiconductor devices and to protect these devices from environmental damage. This latter issue has created a packaging technology that is also driven by continuing demands of device miniaturization and denser packaging of devices, this at no penalty to device performance and in a cost-effective manner.
  • Semiconductor device packaging typically mounts a device on a substrate, such as semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support. Such a substrate can be a relative complex structure, having multiple payers of interconnect metal distributed throughout the height of the substrate in addition to having interconnect traces created on one or both surfaces of the substrate. In addition, in order to enable the mounting of semiconductor over the surface of the substrate, contact pads such as bond pads are typically provided over at least one of the surfaces of a substrate. For more complex packages, several levels of packaging may be applied whereby a semiconductor device is mounted on a substrate and connected to interconnect metal that is part of the substrate, the first level substrate may be further mounted over the surface of a larger substrate from which the device is interconnected to surrounding circuitry or electrical components. Limitations that are imposed on this method of packaging are typically limitations of electrical performance that is imposed on the device by the packaging interface. For instance, of key concerns are RC delays in the transmission of signals over the various interconnect traces. This places a restraint of size and therefore packaging density on the package. Also of concern are considerations of parasitic capacitance and inductance that are introduced by the package since these parameters have a negative impact on device performance, a more serious impact on high frequency device performance. These parasitic components must therefore be minimized or suppressed to the maximum extent possible.
  • One or the more conventional methods of connecting a semiconductor device to surrounding points of interconnect is the use of a solder bump. Typically a semiconductor device will be provided on the active surface of the device with points of electrical interconnect which electrically access the device. To connect these points of interconnect to for instance a printer circuit board, solder bumps are provided on the surface of the circuit board that align with the points of electrical contact of the device. The creation of this interface is also subject to requirements imposed by electrical performance of the completed package, by requirements of package miniaturization, reliability, cost performance and the like. The invention provides a package that addresses these packaging concerns in addition to others.
  • U.S. Pat. No. 6,181,569 (Charkravorty) shows a solder bump process and structure that includes trace formation and bump plating.
  • U.S. Pat. No. 6,107,180 (Munroe et al.) shows a bump process using UBM and solder bumps.
  • U.S. Pat. No. 5,879,964 (Paik et al.) shows a related bump and interconnect process.
  • SUMMARY OF THE INVENTION
  • A principle objective of the invention is to provide a high-pillar solder bump that sustains a high stand-off of the complete solder bump while maintaining high bump reliability and minimizing damage caused by mismatching of thermal stress factors between the interfacing surfaces.
  • Another objective of the invention is to provide a method that further improves bump reliability by reducing mechanical and thermal stress.
  • Yet another objective of the invention is to provide re-distribution bumps which enable the creation of a flip-chip package without requiring a change in the design of the Integrated Circuit and without modifying the pad pitch, the performance of the package is improved and the package size does not need to be modified.
  • A still further objective of the invention is to provide a chip scale package using one UBM layer of metal, significantly reducing costs of fabrication and materials.
  • A still further objective of the invention is to provide a chip scale package whereby the solder ball is removed from the semiconductor device, eliminating the need for low-alpha solder, thus reducing fabrication cost and concerns of soft-error occurrence.
  • In accordance with the objectives of the invention a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point and the surface of the substrate are protected by a layer of passivation, the contact point is exposed through an opening created in the layer of passivation. A layer of polymer or elastomer is deposited over the layer of passivation, an opening is created through the layer of polymer or elastomer that aligns with the contact point (contact pad), exposing the contact pad. A barrier/seed layer is deposited over the surface of the layer of polymer or elastomer, including the inside surfaces of the opening created through the layer of polymer or elastomer and the exposed surface of the contact pad. A first photoresist mask is created over the surface of the barrier/seed layer, the first photoresist mask exposes the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer, a second photoresist mask is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The second photoresist mask defines that solder bump. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a cross section of a conventional mini-BGA package.
  • FIG. 2 shows a cross section of a conventional re-routing bump.
  • FIGS. 3 through 8 detail the process flow of the invention, as follows:
  • FIG. 3 shows a cross section of a silicon substrate, a top metal contact pad has been provided, a layer of passivation and a layer of polymer or elastomer have been deposited and patterned over the surface of the BGA substrate.
  • FIG. 4 shows a cross section after a barrier/seed layer has been deposited.
  • FIG. 5 shows a cross section after a first photoresist mask has been created over the surface of the barrier/seed layer, electroplating has been applied for the deposition of metal for the formation of interconnect traces.
  • FIG. 6 shows a cross section after the first photoresist mask has been removed from the surface of the barrier/seed layer.
  • FIG. 7 shows a cross section after a second photoresist mask has been created over the surface of the barrier/seed layer, including the surface of the electroplated interconnect metal; the second photoresist mask defines the solder bump.
  • FIG. 8 shows a cross section after the solder bump has been electroplated in accordance with the second photoresist mask.
  • FIG. 9 shows a cross section after removal of the second photoresist mask, exposing the surface of the barrier/seed layer and the electroplated interconnect metal.
  • FIG. 10 shows a cross section after the barrier/seed layer has been etched in accordance with the layer of interconnect metal.
  • FIG. 11 shows a cross section of the package of the invention with a molding compound as encapsulant.
  • FIG. 12 shows a cross section of the package of the invention with underfill as encapsulant.
  • FIG. 13 shows a cross section of the package of the invention using both molding and an underfill.
  • FIG. 14 shows a cross section of the package of the invention as a bare die that can be directly attached to a next level substrate.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Two prior art applications are shown in the cross sections of FIGS. 1 and 2, specifically in the cross section of FIG. 1 are shown:
      • 11, a BGA substrate such as a printed circuit board and the like
      • 12, a semiconductor device or die
      • 14, a molding compound that is used to encapsulate the die 12
      • 16, solder balls that form the electrical interface between the package shown in cross section in FIG. 1 and surrounding circuitry; these solder balls can for instance be further connected to contact pads on the surface of a Printed Circuit Board (PCB)
      • 18, bond wires used to connect points of electrical contact (not shown) on the active surface of die 12 with contact pads (not shown) on the second or upper surface of BGA substrate 11.
  • FIG. 2 shows a cross section of a conventional re-routing bump, the re-routing applies since the solder bump that is shown in cross section in FIG. 2 does not align with the contact pad with which the solder bump is connected. The elements that are highlighted in the cross section of FIG. 2 are the following:
      • 10, a device supporting silicon substrate
      • 20, a solder ball
      • 22, top metal contact point
      • 24, a layer of passivation, applied for the protection of the underlying surface and the surface of the layer 22 of top metal
      • 26, a layer of dielectric material
      • 28, a layer of passivation, applied for the protection of the underlying layer 26 of dielectric and the surface of the layer 32 of re-routing metal
      • 30, a seed and/or barrier layer
      • 32, a patterned layer of re-routing metal
      • 33, a seed layer, and
      • 34, a layer of UBM metal.
  • FIGS. 3 through 9 will now be used to describe the invention. Referring specifically to the cross section that is shown in FIG. 3, there is shown:
      • 10, a semiconductor supporting surface such as the surface of a silicon substrate
      • 40, a contact pad or top metal pad that has been provided in or on the surface of the substrate layer 10
      • 42, a layer of passivation deposited over the surface of layer 10; the layer 42 of passivation has been patterned and etched, creating on opening 41 through the layer 42 of passivation that aligns with the contact pad 40
      • 44, a layer of polymer or elastomer that has been deposited over the surface of the layer 42 of passivation; the layer 44 of polymer or elastomer has been patterned and etched, creating on opening 41 through the layer 42 of polymer or elastomer that aligns with the contact pad 40. Contact pad 40 can comprise aluminum or copper or a compound thereof.
  • As materials that can be used as a polymer for the deposition of layer 44 can be cited polyimide, parylene or teflon, electron resist, solid organics or inorganics, BCB (bisbenzocyclobutene), PMMA (poly-methyl-methacrylate), teflon which is a polymer made from PTFE (polytetrafluoroethylene), also polycarbonate (PC), polysterene (PS), polyoxide (PO) and poly polooxide (PPO).
  • The semiconductor supporting surface 10 can be semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support, whereby the semiconductor substrate can selected from the group of substrates consisting of semiconductor substrates, ceramic substrates, glass substrates, gallium arsenide substrates, silicon on insulator (SOI) substrates and silicon on sapphire (SOS) substrates.
  • FIG. 4 shows a cross section of the semiconductor substrate after a layer 46 of barrier/seed material has been deposited over the surface of layer 44 of polymer or elastomer; inside surface of opening 41 have also been covered with the layer 46 of barrier/seed material.
  • A typical barrier layer 46 is deposited using rf. sputtering of titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN. The barrier layer 46 can also be used to improve the adhesion of a subsequent overlying metal layers. A barrier layer is preferably about 100 and 1000 angstrom thick.
  • To further enhance the adhesion of a copper interconnect line to the surrounding layer of dielectric or insulation, a seed layer is deposited over the barrier layer. A seed layer can be deposited using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr, using copper or a copper alloy as the source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas. The minimum thickness of a seed layer is about 5,000 Angstrom, this thickness is required achieve a reliable gap fill.
  • FIG. 5 shows a cross section after:
      • 48, a first photoresist mask has been formed over the surface of barrier/seed layer 46, exposing the surface of the barrier/seed layer 46, and
      • 50, a layer 50 of metal has been over the exposed surface of the barrier/seed layer 46 in accordance with the opening 43 created in the first photoresist mask.
  • The process of deposition and patterning a layer of photoresist uses conventional methods of photolithography and masking. Layer 48 of photoresist can be etched by applying O2 plasma and then wet stripping by using H2SO4, H2O2 and NH4OH solution. Sulfuric acid (H2SO4) and mixtures of H2SO4 with other oxidizing agents such as hydrogen peroxide (H2O2) are widely used in stripping photoresist after the photoresist has been stripped by other means. Wafers to be stripped can be immersed in the mixture at a temperature between about 100 degrees C. and about 150 degrees C. for 5 to 10 minutes and then subjected to a thorough cleaning with deionized water and dried by dry nitrogen. Inorganic resist strippers, such as the sulfuric acid mixtures, are very effective in the residual free removal of highly postbaked resist. They are more effective than organic strippers and the longer the immersion time, the cleaner and more residue free wafer surface can be obtained. The opening 43 that is in this manner created in the layer 48 of photoresist exposes the surface of the layer 44 of barrier/seed material over a surface area where re-routing metal has to be created.
  • Removal of the first photoresist mask 48 from the surface of the barrier/seed layer 46 results in the cross section that is shown in FIG. 6.
  • The invention continues with the cross section that is shown in FIG. 7, shown are:
      • 52, a second photoresist mask is created over the surface of the barrier/seed layer 46, including the surface of the interconnect metal layer 50, and
      • 51 opening created in the second layer 52 of photoresist, exposing the surface of layer 50 of interconnect metal; opening 51 defined the location and size (diameter) of the to be created solder bump.
  • The cross section that is shown in FIG. 8 is after the opening 51 created in the second layer of dielectric has been filled with solder bump material. These materials can be selected as:
      • layer 54 being a first layer of metal, typically comprising copper, deposited to a thickness between about 10 and 100 μm, and more preferably to a thickness of about 50 μm
      • layer 56 being an UBM layer, typically comprising nickel, deposited to a thickness between about 1 and 10 μm, and more preferably to a thickness of about 5 μm, forming an integral part of the pedestal of the to be created interconnect bump, and
      • layer 58 is a layer of solder compound, deposited to a thickness between about 10 and 100 μm, and more preferably to a thickness of about 50 μm.
  • With the completion of the electroplating of these three layers, the solder bump is essentially complete. The second solder mask 52, FIG. 8, is therefore removed from the surface of the barrier/seed layer 46 and the surface of the interconnect metal 50, see FIG. 9, exposing the barrier/seed layer 46 and the interconnect metal 50, a pattern of barrier/seed material overlying the barrier/seed layer 46.
  • It is good practice and can be of benefit in the creation of the layers 54, 56 and 58 of metal to perform, prior to the electroplating of these layers of metal, an in-situ sputter clean of the exposed surface (exposed through opening 51) of the layer 50 of re-routing metal.
  • The barrier/seed layer 46 can now be etched using the patterned layer 50 of interconnect metal as a mask, which leads to the cross section that is shown in FIG. 10.
  • It is further good practice to oxidize the surface of the UBM and pillar metal by chemical or thermal oxidation. The chemical oxidation could be an H2O2 oxidation process, at a temperature in excess of about 150 degrees C. These processing steps can further help prevent wetting of the solder bump to the metal traces.
  • Reflow can optionally be applied the layer 58 of solder compound, creating a spherical layer 58 of solder which forms the solder bump (not shown). It must be noted in the cross section that is shown in FIG. 10 that the diameter of the UBM layer 54 is, during and as a consequence of the etching of the barrier/seed layer 46, reduced in diameter. This allows the solder ball 58 to be removed from the surface of the substrate by a relatively large distance. From this follows the advantage that it is no longer required that low-alpha solder is used for the solder compound of solder ball 58 reducing manufacturing cost in addition to reducing concerns of memory soft-error conditions.
  • Layer 56 of UBM may contain multiple layers of metal such as a layer of chrome, followed by a layer of copper, followed by a layer of gold. From the latter it is apparent that layer 56 of UBM may comprise several layers of metal that are successively deposited.
  • Examples of the application of the package of the invention are shown in cross section in FIGS. 11 and 12. Highlighted in FIG. 11 are:
      • 60, a polymer or elastomer layer provided by the invention, similar to layer 44 of FIG. 3 e.a.
      • 62, a BGA substrate over which a semiconductor device is to be mounted
      • 64, a semiconductor device
      • 66, a molding compound applied to encapsulate the device 64
      • 68, contact balls to the package of the invention
      • 70, pillar metal, similar to layers 54 and 56 of FIG. 8 e.a., and
      • 72, a solder bump, similar to layer 58 of FIG. 8 after thermal reflow has been applied to this layer.
  • Shown in cross section in FIG. 12 is another application of the invention. The elements that have been applied above under FIG. 11 are valid for the cross section shown in FIG. 12 with the exception of element 74, which in the cross section of FIG. 12 is an underfill that has been applied under semiconductor device 64 and that replaces layer 66 of molding compound in FIG. 11 as the means for encapsulating the device 64.
  • FIGS. 13 and 14 show additional applications of the invention with FIG. 13 showing a cross section of the package of the invention using both molding and an underfill while FIG. 14 shows a cross section of the package of the invention as a bare die that can be directly attached to a next level substrate. All elements of the cross sections that are shown in FIGS. 13 and 14 have previously been described and need therefore not been further highlighted at this time.
  • In order to better highlight the differences between the prior art solder bump, as shown in cross section in FIG. 2, and the solder bump of the invention, as shown in the cross section of FIG. 10, the processing steps to create these two solder bumps are listed below. These steps are easier to follow if it is realized that both methods require and apply two metal fill plating steps, the first of these two step is to create a patterned layer of re-routing metal, the second is to create the solder bump. The processing sequences are as follows:
    • 1. the prior art starts with a device support substrate, a contact pad has been created over the surface of the substrate, layers of passivation and dielectric have been deposited over the surface of the substrate and patterned to expose the contact pad; the invention starts with the same structure
    • 2. the prior art deposits a first seed layer over the surface of the layer of dielectric; the invention does the same
    • 3. the prior art performs a first metal fill over the first seed layer by creating a layer of metal that serves as re-routing metal; the invention does the same
    • 4. the prior art etches the first seed layer; the instant invention does not perform this step at this time
    • 5. the prior art deposits and patterns a layer of passivation, exposing the surface of the layer of re-routing metal, the patterned second layer of passivation serves as a mask for the reflow of the solder bump; the instant invention does not perform this step because the solder bump structure will not wet to the re-routing metal
    • 6. the prior art deposits a second seed layer over the surface of the layer of passivation; the instant invention does not deposit a second seed layer
    • 7. the prior art plates a layer of UBM over which a layer of solder compound is plated; the instant invention deposits a layer of UBM and two metal plating steps, the first metal plating step plating a layer of metal, such as copper or nickel that forms an integral part of the pedestal of the to be created interconnect bump, the second metal plating step depositing a solder compound
    • 8. the prior art performs reflow of the solder compound; the instant invention does the same
    • 9. the prior art etches the second seed layer using the solder ball as a mask; the instant invention etches the first seed layer using the patterned re-routing metal as a mask.
  • The essential differences between the prior art and the instant invention is provided by the two plating steps and can, for easy reference be summarized as follows:
    Prior Art Instant Invention
    First plating step
    1st seed layer dep. 1st seed layer dep.
    plate re-routing metal plate re-routing metal
    etch 1st seed layer (no equivalent step)
    Second plating step
    2st seed layer dep. (no equivalent step)
    plate UBM + solder plate UBM + metal + solder
    etch 2st seed layer etch 1st seed layer
  • The advantages of the instant invention can be summarized as follows:
    • 1. the height of the metal pillar (layers 54 and 56, FIG. 10) allows for high stand-off between the surface of substrate 10, thereby reducing impact of mismatching of thermal fatigue between interfacing surfaces such as the surface of the substrate 10 and the layers of metal that are part of the solder bump
    • 2. the layer 44 has been highlighted as being a layer of or polymer or elastomer and is selected for its ability to provide stress release between overlying surfaces and thus to enhance solder bump reliability
    • 3. the re-distribution solder bump of the invention allows for creating a flip-chip package without the need for semiconductor device redesign or changes in the pitch of the contact points of the package (the pitch of contact balls 72 and 68, FIGS. 11 and 12); the package size can also remain constant while still being able to package die of different dimensions (due to the flexibility of the routing of the re-routing metal layer 50, FIG. 50, FIG. 10)
    • 4. the method of creating the solder pillar and the solder bump, that is plating a layer of UBM over which metal is plated twice, contributes a significant cost saving in both materials used and in the manufacturing cost; the need for separate UBM plating and etching, for separate plating and etching the pillar metal and for separate plating and etching the solder compound is reduced to using one photoresist mask that is applied for all three steps
    • 5. by creating a relatively high layer of pillar metal, the solder ball is removed from the surface of the substrate; from this follows that low-alpha solder is no longer required as a solder compound for the solder bump, reducing manufacturing costs; from this further follows that soft-error concerns that typically apply to memory chip designs are less valid using the solder bump of the invention
    • 6. by creating a relatively high layer of pillar metal, the solder ball of the instant invention will not wet to the re-routing metal trace. Thus, the second layer of passivation material, which typically serves as a solder mask, is no longer required and, consequently, processing cost is reduced.
  • In sum: the invention provides a method to create a solder bump having a high metal pillar and a solder ball. Seed/barrier layer deposition is limited to one deposition, a first metal plating step defines the re-routing metal, a second metal plating step creates the solder bump. The need for additional layers of passivation or solder mask has been removed.
  • Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.

Claims (20)

1. A chip package comprising:
a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;
a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, and a pad exposed by an opening in said passivation layer and in said polymer layer;
a copper pillar between said semiconductor device and said first surface, wherein said copper pillar is connected to said pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;
a nickel layer between said copper pillar and said first surface, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a sidewall recessed from that of said nickel layer, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;
a solder metal between said nickel layer and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;
an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and
a contact ball on said second surface.
2. The chip package of claim 1, wherein said polymer layer comprises polyimide.
3. The chip package of claim 1, wherein said polymer layer comprises bisbenzocyclobutene (BCB).
4. The chip package of claim 1, wherein said pad comprises copper.
5. The chip package of claim 1, wherein said pad comprises aluminum.
6. A chip package comprising:
a substrate;
a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, and a pad exposed by an opening in said passivation layer and in said polymer layer;
a copper pillar between said semiconductor device and said substrate, wherein said copper pillar is connected to said pad through said opening, and wherein said copper pillar has a thickness between 10 and 100 micrometers;
a nickel layer between said copper pillar and said substrate, wherein said nickel layer has a height between 1 and 10 micrometers and greater than a transverse dimension of said copper pillar, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a sidewall recessed from that of said nickel layer, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;
a solder metal between said nickel layer and said substrate, wherein said solder metal is joined with said substrate; and
an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal.
7. The chip package of claim 6, wherein said polymer layer comprises polyimide.
8. The chip package of claim 6, wherein said polymer layer comprises bisbenzocyclobutene (BCB).
9. The chip package of claim 6, wherein said pad comprises copper.
10. The chip package of claim 6, wherein said pad comprises aluminum.
11. A chip package comprising:
a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;
a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, a first pad exposed by an opening in said passivation layer and in said polymer layer, and a metal interconnect on said polymer layer, wherein said metal interconnect comprises a second pad connected to said first pad, wherein the position of said second pad from a top view is different from that of said first pad;
a copper pillar between said second pad and said first surface, wherein said copper pillar is connected to said first pad through said opening and said metal interconnect, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;
a nickel layer between said copper pillar and said first surface, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a sidewall recessed from that of said nickel layer, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;
a solder metal between said nickel layer and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;
an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and
a contact ball on said second surface.
12. The chip package of claim 11, wherein said polymer layer comprises polyimide.
13. The chip package of claim 11, wherein said metal interconnect comprises titanium and copper.
14. The chip package of claim 11, wherein said first pad comprises copper.
15. The chip package of claim 11, wherein said metal interconnect comprises a first metal layer comprising sputtered titanium-containing material and sputtered copper and a second metal layer comprising an electroplated metal on said first metal layer.
16. A chip package comprising:
a substrate;
a semiconductor device comprising a passivation layer, a polymer layer on said passivation layer, a first pad exposed by an opening in said passivation layer and in said polymer layer, and a metal interconnect on said polymer layer, wherein said metal interconnect comprises a second pad connected to said first pad, wherein the position of said second pad from a top view is different from that of said first pad;
a copper pillar between said second pad and said substrate, wherein said copper pillar is connected to said first pad through said opening and said metal interconnect, and wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar;
a nickel layer between said copper pillar and said substrate, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a transverse dimension smaller than that of said nickel layer, wherein said copper pillar has a sidewall recessed from that of said nickel layer, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar;
a solder metal between said nickel layer and said substrate, wherein said solder metal is joined with said substrate; and
an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal.
17. The chip package of claim 16, wherein said polymer layer comprises polyimide.
18. The chip package of claim 16, wherein said metal interconnect comprises titanium and copper.
19. The chip package of claim 16, wherein said first pad comprises copper.
20. The chip package of claim 16, wherein said metal interconnect comprises a first metal layer comprising sputtered titanium-containing material and sputtered copper and a second metal layer comprising an electroplated metal on said first metal layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030010B2 (en) * 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US20150235071A1 (en) * 2014-02-17 2015-08-20 J-Metrics Technology Co., Ltd. Biometrics Sensor Having Flat Contact Surface Formed by Signal Extending Structure and Method of Manufacturing Such Sensor

Families Citing this family (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870272B2 (en) 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
US6284563B1 (en) 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
EP1915040A3 (en) * 2001-09-28 2008-04-30 Ibiden Co., Ltd. Printed wiring board and printed wiring board manufacturing method
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
KR100476301B1 (en) * 2002-07-27 2005-03-15 한국과학기술원 Fabrication Method of multilayer UBM by Electroplating for Flip chip Interconnections
US20040040855A1 (en) * 2002-08-28 2004-03-04 Victor Batinovich Method for low-cost redistribution and under-bump metallization for flip-chip and wafer-level BGA silicon device packages
US7115998B2 (en) * 2002-08-29 2006-10-03 Micron Technology, Inc. Multi-component integrated circuit contacts
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
TWI225280B (en) * 2003-06-30 2004-12-11 Advanced Semiconductor Eng Bumping process
DE10337569B4 (en) * 2003-08-14 2008-12-11 Infineon Technologies Ag Integrated terminal assembly and manufacturing processes
JP2005070360A (en) * 2003-08-22 2005-03-17 Sony Corp Electric circuit board
US7462942B2 (en) * 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US7394161B2 (en) 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
TWI273664B (en) * 2004-03-26 2007-02-11 Advanced Semiconductor Eng Bumping process, bump structure, packaging process and package structure
KR100511926B1 (en) * 2004-04-29 2005-08-25 주식회사 하이닉스반도체 Semiconductor chip package and method for forming the same
TWI230989B (en) * 2004-05-05 2005-04-11 Megic Corp Chip bonding method
TWI331370B (en) * 2004-06-18 2010-10-01 Megica Corp Connection between two circuitry components
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7122458B2 (en) 2004-07-22 2006-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating pad redistribution layer
TWI244152B (en) * 2004-10-22 2005-11-21 Advanced Semiconductor Eng Bumping process and structure thereof
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP4843229B2 (en) * 2005-02-23 2011-12-21 株式会社東芝 A method of manufacturing a semiconductor device
US7999379B2 (en) * 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7468545B2 (en) 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
CN1901163B (en) 2005-07-22 2011-04-13 米辑电子股份有限公司 Method for fabricating a circuitry component by continuous electroplating and circuitry component structure
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
TWI294151B (en) * 2005-11-15 2008-03-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
TWI283916B (en) * 2005-12-08 2007-07-11 Taiwan Solutions Systems Corp Manufacturing method of chip package structure
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
TWI277190B (en) * 2006-03-07 2007-03-21 Ind Tech Res Inst Package structure for electronic device
US7582966B2 (en) * 2006-09-06 2009-09-01 Megica Corporation Semiconductor chip and method for fabricating the same
US7749886B2 (en) * 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
CN101226889B (en) * 2007-01-15 2010-05-19 百慕达南茂科技股份有限公司 Reconfiguration line structure and manufacturing method thereof
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
JP2009081153A (en) * 2007-09-25 2009-04-16 Taiyo Yuden Co Ltd Semiconductor device and circuit device mounting the same
SG152101A1 (en) 2007-11-06 2009-05-29 Agency Science Tech & Res An interconnect structure and a method of fabricating the same
JP5113544B2 (en) * 2008-01-30 2013-01-09 新光電気工業株式会社 A method for manufacturing a wiring board
US8276269B2 (en) 2008-06-20 2012-10-02 Intel Corporation Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same
KR101036388B1 (en) * 2008-08-19 2011-05-23 삼성전기주식회사 Printed circuit board and method for manufacturing the same
US9331096B2 (en) * 2009-09-04 2016-05-03 Luxtera, Inc. Method and system for hybrid integration of optical communication systems
US20100295168A1 (en) * 2009-05-21 2010-11-25 Chien-Te Feng Semiconductor package using conductive plug to replace solder ball
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8377816B2 (en) * 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8569897B2 (en) * 2009-09-14 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for preventing UBM layer from chemical attack and oxidation
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
TWI445147B (en) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng Semiconductor device
US8609526B2 (en) * 2009-10-20 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Preventing UBM oxidation in bump formation processes
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
US9024431B2 (en) * 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US8569887B2 (en) * 2009-11-05 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect with oxidation prevention layer
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8304919B2 (en) * 2010-03-26 2012-11-06 Stats Chippac Ltd. Integrated circuit system with stress redistribution layer and method of manufacture thereof
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
TWI419284B (en) * 2010-05-26 2013-12-11 Chipmos Technologies Inc Chip bump structure and method for forming chip bump structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8922004B2 (en) 2010-06-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump structures having sidewall protection layers
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US20130105329A1 (en) * 2010-08-02 2013-05-02 Atotech Deutschland Gmbh Method to form solder deposits and non-melting bump structures on substrates
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
TWI478303B (en) 2010-09-27 2015-03-21 Advanced Semiconductor Eng Chip having metal pillar and package having the same
TWI451546B (en) 2010-10-29 2014-09-01 Advanced Semiconductor Eng Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package
US20120267779A1 (en) * 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
JP2012231096A (en) * 2011-04-27 2012-11-22 Elpida Memory Inc Semiconductor device and manufacturing method of the same
US8610285B2 (en) 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
US8716858B2 (en) 2011-06-24 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure with barrier layer on post-passivation interconnect
FR2978296A1 (en) 2011-07-20 2013-01-25 St Microelectronics Crolles 2 Electronic chip comprising connection pillars, and method for making
US8431478B2 (en) * 2011-09-16 2013-04-30 Chipmos Technologies, Inc. Solder cap bump in semiconductor package and method of manufacturing the same
US8581400B2 (en) 2011-10-13 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure
US9978656B2 (en) 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
US9613914B2 (en) 2011-12-07 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure
US9385076B2 (en) 2011-12-07 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with bump structure on an interconncet structure
US9324667B2 (en) 2012-01-13 2016-04-26 Freescale Semiconductor, Inc. Semiconductor devices with compliant interconnects
US20130234317A1 (en) * 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9263412B2 (en) 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
DE102012102021A1 (en) * 2012-03-09 2013-09-12 Epcos Ag A micromechanical sensing element and method for manufacturing a micromechanical sensing element
JP5880283B2 (en) * 2012-05-29 2016-03-08 富士通セミコンダクター株式会社 A method of manufacturing a semiconductor device
US9190348B2 (en) 2012-05-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US9472521B2 (en) 2012-05-30 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8912087B2 (en) * 2012-08-01 2014-12-16 Infineon Technologies Ag Method of fabricating a chip package
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
KR101835566B1 (en) * 2012-10-08 2018-03-07 삼성전기주식회사 Package structure and method for manufacturing package structure
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
US9082870B2 (en) * 2013-03-13 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging semiconductor devices
CN104619119B (en) * 2013-11-05 2017-10-24 南昌欧菲光电技术有限公司 Circuit boards and the camera module
US9570342B1 (en) 2014-01-17 2017-02-14 Altera Corporation Via structure and method for its fabrication
WO2015157124A1 (en) * 2014-04-07 2015-10-15 Flir Systems, Inc. Method and systems for coupling semiconductor substrates
US9608403B2 (en) * 2014-11-03 2017-03-28 International Business Machines Corporation Dual bond pad structure for photonics
US10163661B2 (en) * 2015-06-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
JP2018006398A (en) * 2016-06-28 2018-01-11 住友電工デバイス・イノベーション株式会社 Method of manufacturing semiconductor device

Citations (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668484A (en) * 1970-10-28 1972-06-06 Rca Corp Semiconductor device with multi-level metalization and method of making the same
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
US4726991A (en) * 1986-07-10 1988-02-23 Eos Technologies Inc. Electrical overstress protection material and process
US4811237A (en) * 1987-06-19 1989-03-07 General Electric Company Structured design method for generating a mesh power bus structure in high density layout of VLSI chips
US4825276A (en) * 1986-06-19 1989-04-25 Nec Corporation Integrated circuit semiconductor device having improved wiring structure
US5108950A (en) * 1987-11-18 1992-04-28 Casio Computer Co., Ltd. Method for forming a bump electrode for a semiconductor device
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US5137845A (en) * 1990-07-31 1992-08-11 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
US5326709A (en) * 1991-12-19 1994-07-05 Samsung Electronics Co., Ltd. Wafer testing process of a semiconductor device comprising a redundancy circuit
US5418186A (en) * 1993-07-15 1995-05-23 Samsung Electronics Co., Ltd. Method for manufacturing a bump on a semiconductor chip
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5534465A (en) * 1995-01-10 1996-07-09 At&T Corp. Method for making multichip circuits using active semiconductor substrates
US5598348A (en) * 1994-09-22 1997-01-28 Sun Microsystems, Inc. Method and apparatus for analyzing the power network of a VLSI circuit
US5600180A (en) * 1994-07-22 1997-02-04 Nec Corporation Sealing structure for bumps on a semiconductor integrated circuit chip
US5629241A (en) * 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5631499A (en) * 1994-04-28 1997-05-20 Kabushiki Kaisha Toshiba Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics
US5656863A (en) * 1993-02-18 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Resin seal semiconductor package
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US5756370A (en) * 1996-02-08 1998-05-26 Micron Technology, Inc. Compliant contact system with alignment structure for testing unpackaged semiconductor dice
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US5780925A (en) * 1992-10-28 1998-07-14 International Business Machines Corporation Lead frame package for electronic devices
US5866949A (en) * 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5874781A (en) * 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5877078A (en) * 1997-04-08 1999-03-02 Sony Corporation Method of manufacturing a semiconductor device
US5883435A (en) * 1996-07-25 1999-03-16 International Business Machines Corporation Personalization structure for semiconductor devices
US5882957A (en) * 1997-06-09 1999-03-16 Compeq Manufacturing Company Limited Ball grid array packaging method for an integrated circuit and structure realized by the method
US5898222A (en) * 1995-05-12 1999-04-27 International Business Machines Corporation Capped copper electrical interconnects
US5903343A (en) * 1997-12-23 1999-05-11 Siemens Aktiengesellschaft Method for detecting under-etched vias
US5933358A (en) * 1997-09-30 1999-08-03 Synopsys, Inc. Method and system of performing voltage drop analysis for power supply networks of VLSI circuits
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US5946590A (en) * 1996-12-10 1999-08-31 Citizen Watch Co., Ltd. Method for making bumps
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US6028363A (en) * 1997-06-04 2000-02-22 Taiwan Semiconductor Manufacturing Company Vertical via/contact
US6043672A (en) * 1998-05-13 2000-03-28 Lsi Logic Corporation Selectable power supply lines for isolating defects in integrated circuits
US6051450A (en) * 1997-07-01 2000-04-18 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US6077726A (en) * 1998-07-30 2000-06-20 Motorola, Inc. Method and apparatus for stress relief in solder bump formation on a semiconductor device
US6177731B1 (en) * 1998-01-19 2001-01-23 Citizen Watch Co., Ltd. Semiconductor package
US6187680B1 (en) * 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
US6194309B1 (en) * 1998-08-10 2001-02-27 Samsung Electronics Co., Ltd. Method for forming contact
US6198619B1 (en) * 1998-04-24 2001-03-06 Mitsubishi Denki Kabushiki Kaisha Capacitor network
US6197613B1 (en) * 1999-03-23 2001-03-06 Industrial Technology Research Institute Wafer level packaging method and devices formed
US6207467B1 (en) * 1999-08-17 2001-03-27 Micron Technology, Inc. Multi-chip module with stacked dice
US6229220B1 (en) * 1995-06-27 2001-05-08 International Business Machines Corporation Bump structure, bump forming method and package connecting body
US6229711B1 (en) * 1998-08-31 2001-05-08 Shinko Electric Industries Co., Ltd. Flip-chip mount board and flip-chip mount structure with improved mounting reliability
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US6268662B1 (en) * 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
US6271107B1 (en) * 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
US6348401B1 (en) * 2000-11-10 2002-02-19 Siliconware Precision Industries Co., Ltd. Method of fabricating solder bumps with high coplanarity for flip-chip application
US6372622B1 (en) * 1999-10-26 2002-04-16 Motorola, Inc. Fine pitch bumping with improved device standoff and bump volume
US20020043723A1 (en) * 2000-10-16 2002-04-18 Hironobu Shimizu Semiconductor device and manufacturing method thereof
US6405357B1 (en) * 2000-05-02 2002-06-11 Advanced Semiconductor Engineering, Inc. Method for positioning bond pads in a semiconductor die
US6406967B1 (en) * 1999-08-06 2002-06-18 Samsung Electronics Co., Ltd. Method for manufacturing cylindrical storage electrode of semiconductor device
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
US6518651B2 (en) * 1997-01-17 2003-02-11 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US6518092B2 (en) * 2000-07-13 2003-02-11 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing
US6523154B2 (en) * 2000-12-14 2003-02-18 International Business Machines Corporation Method for supply voltage drop analysis during placement phase of chip design
US6538331B2 (en) * 2000-01-31 2003-03-25 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6541847B1 (en) * 2002-02-04 2003-04-01 International Business Machines Corporation Packaging for multi-processor shared-memory system
US6558978B1 (en) * 2000-01-21 2003-05-06 Lsi Logic Corporation Chip-over-chip integrated circuit package
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US20030151047A1 (en) * 1995-11-17 2003-08-14 Corbett Tim J. Semiconductor reliability test chip
US6675139B1 (en) * 1999-03-16 2004-01-06 Lsi Logic Corporation Floor plan-based power bus analysis and design tool for integrated circuits
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US6683380B2 (en) * 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6709985B1 (en) * 1999-08-26 2004-03-23 Advanced Micro Devices, Inc. Arrangement and method for providing an imaging path using a silicon-crystal damaging laser
US20040088443A1 (en) * 2002-10-29 2004-05-06 Broadcom Corporation Multipurpose and programmable pad ring for an integrated circuit
US6756664B2 (en) * 2002-11-22 2004-06-29 Via Technologies, Inc. Noise eliminating system on chip and method of making same
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
US6765299B2 (en) * 2000-03-09 2004-07-20 Oki Electric Industry Co., Ltd. Semiconductor device and the method for manufacturing the same
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US6861742B2 (en) * 2001-01-18 2005-03-01 Renesas Technology Corp. Wafer level chip size package having rerouting layers
US20050050502A1 (en) * 2003-08-27 2005-03-03 Fujitsu Limited Method and apparatus for designing semiconductor integrated circuit
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
US20050090916A1 (en) * 2003-08-25 2005-04-28 Majid Aghababazadeh Intra-chip power and test signal generation for use with test structures on wafers
US6917119B2 (en) * 2001-09-17 2005-07-12 Megic Corporation Low fabrication cost, high performance, high reliability chip scale package
US6991961B2 (en) * 2003-06-18 2006-01-31 Medtronic, Inc. Method of forming a high-voltage/high-power die package
US20060080630A1 (en) * 2003-11-02 2006-04-13 Mentor Graphics Corp. Power/ground wire routing correction and optimization
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US7043389B2 (en) * 2004-02-18 2006-05-09 James Francis Plusquellic Method and system for identifying and locating defects in an integrated circuit
US7045899B2 (en) * 2002-10-15 2006-05-16 Oki Electric Industry Co., Ltd. Semiconductor device and fabrication method of the same
US7074050B1 (en) * 2005-11-17 2006-07-11 International Business Machines Corporation Socket assembly with incorporated memory structure
US7220657B2 (en) * 1999-01-27 2007-05-22 Shinko Electric Industries, Co., Ltd. Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
US7224056B2 (en) * 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US7246432B2 (en) * 2005-06-28 2007-07-24 Seiko Epson Corporation Method of manufacturing semiconductor device
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7479398B2 (en) * 2003-07-03 2009-01-20 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7505284B2 (en) * 2005-05-12 2009-03-17 International Business Machines Corporation System for assembling electronic components of an electronic system

Family Cites Families (132)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179802A (en) 1978-03-27 1979-12-25 International Business Machines Corporation Studded chip attachment process
US4652336A (en) 1984-09-20 1987-03-24 Siemens Aktiengesellschaft Method of producing copper platforms for integrated circuits
JPH01214141A (en) 1988-02-23 1989-08-28 Nec Corp Flip-chip type semiconductor device
US5061985A (en) 1988-06-13 1991-10-29 Hitachi, Ltd. Semiconductor integrated circuit device and process for producing the same
US4880708A (en) 1988-07-05 1989-11-14 Motorola, Inc. Metallization scheme providing adhesion and barrier properties
JP2785338B2 (en) 1989-06-19 1998-08-13 日本電気株式会社 A method of manufacturing a semiconductor device
US5244833A (en) 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5071518A (en) 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
US5083187A (en) 1990-05-16 1992-01-21 Texas Instruments Incorporated Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof
US5261155A (en) 1991-08-12 1993-11-16 International Business Machines Corporation Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using different solders
US5268072A (en) 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
US5300461A (en) 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
JP3258740B2 (en) 1993-01-29 2002-02-18 三菱電機株式会社 The method of manufacturing a semiconductor device having a protruding electrode
US5554940A (en) 1994-07-05 1996-09-10 Motorola, Inc. Bumped semiconductor device and method for probing the same
KR960015869A (en) 1994-10-03 1996-05-22 The semiconductor package and a method of manufacturing the integrated semiconductor chip
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
US5468984A (en) 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
US5872952A (en) 1995-04-17 1999-02-16 Synopsys, Inc. Integrated circuit power net analysis through simulation
US5541135A (en) 1995-05-30 1996-07-30 Motorola, Inc. Method of fabricating a flip chip semiconductor device having an inductor
KR100327442B1 (en) 1995-07-14 2002-02-22 구본준, 론 위라하디락사 Bump structure of semiconductor device and fabricating method thereof
US6042953A (en) 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
US5726502A (en) 1996-04-26 1998-03-10 Motorola, Inc. Bumped semiconductor device with alignment features and method for making the same
US5808900A (en) 1996-04-30 1998-09-15 Lsi Logic Corporation Memory having direct strap connection to power supply
JP3201957B2 (en) 1996-06-27 2001-08-27 インターナショナル・ビジネス・マシーンズ・コーポレーション Metal bumps, a method of manufacturing a metal bump, a connection structure
KR100213209B1 (en) * 1996-07-29 1999-08-02 윤종용 Manufacturing method of semiconductor devices
US5664642A (en) 1996-08-26 1997-09-09 Williams; Bernard Fire evacuation kit
TW397933B (en) 1997-05-09 2000-07-11 Ind Tech Res Inst Surface screen print
JP3611948B2 (en) 1997-05-16 2005-01-19 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
US6144100A (en) 1997-06-05 2000-11-07 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6013571A (en) 1997-06-16 2000-01-11 Motorola, Inc. Microelectronic assembly including columnar interconnections and method for forming same
US6082610A (en) 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US5891756A (en) 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
KR100253116B1 (en) 1997-07-07 2000-04-15 윤덕용 Method of manufacturing chip size package using the method
US6002589A (en) 1997-07-21 1999-12-14 Rambus Inc. Integrated circuit package for coupling to a printed circuit board
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
JPH11219984A (en) 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor
US6162652A (en) 1997-12-31 2000-12-19 Intel Corporation Process for sort testing C4 bumped wafers
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US5977632A (en) 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
WO1999050907A1 (en) * 1998-03-27 1999-10-07 Seiko Epson Corporation Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus
US6057169A (en) 1998-04-17 2000-05-02 Lsi Logic Corporation Method for I/O device layout during integrated circuit design
SG75841A1 (en) 1998-05-02 2000-10-24 Eriston Invest Pte Ltd Flip chip assembly with via interconnection
US5985765A (en) 1998-05-11 1999-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
TW396419B (en) 1998-06-30 2000-07-01 Tsmc Acer Semiconductor Mfg Co A method of manufacturing resistors with high ESD resistance and salicide CMOS transistor
JP3420703B2 (en) * 1998-07-16 2003-06-30 株式会社東芝 A method of manufacturing a semiconductor device
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6998711B1 (en) * 1998-08-14 2006-02-14 Micron Technology, Inc. Method of forming a micro solder ball for use in C4 bonding process
JP3577419B2 (en) * 1998-12-17 2004-10-13 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US6383916B1 (en) 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
SG93278A1 (en) 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
US6479900B1 (en) * 1998-12-22 2002-11-12 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
JP2000260803A (en) 1999-01-05 2000-09-22 Citizen Watch Co Ltd Semiconductor device and manufacture thereof
JP3346320B2 (en) 1999-02-03 2002-11-18 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP3483490B2 (en) 1999-02-16 2004-01-06 シャープ株式会社 A method of manufacturing a semiconductor device
US6707159B1 (en) * 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
TW418470B (en) 1999-03-30 2001-01-11 Ind Tech Res Inst Method for forming solder bumps on flip chips and devices formed
JP3446825B2 (en) 1999-04-06 2003-09-16 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
US6332988B1 (en) 1999-06-02 2001-12-25 International Business Machines Corporation Rework process
US6181569B1 (en) 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6166444A (en) * 1999-06-21 2000-12-26 United Microelectronics Corp. Cascade-type chip module
TW419764B (en) 1999-09-03 2001-01-21 Ind Tech Res Inst Manufacturing method and structure of wafer size packaging
TW419765B (en) 1999-09-30 2001-01-21 Taiwan Semiconductor Mfg Manufacturing method of flip chip solder bumps
JP3287346B2 (en) 1999-11-29 2002-06-04 カシオ計算機株式会社 Semiconductor device
TW434857B (en) 1999-12-01 2001-05-16 Huang Jr Gung Chip scale package
JP3409759B2 (en) 1999-12-09 2003-05-26 カシオ計算機株式会社 A method of manufacturing a semiconductor device
US6331227B1 (en) 1999-12-14 2001-12-18 Epion Corporation Enhanced etching/smoothing of dielectric surfaces
KR20010064907A (en) 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
US6446245B1 (en) 2000-01-05 2002-09-03 Sun Microsystems, Inc. Method and apparatus for performing power routing in ASIC design
KR100386081B1 (en) 2000-01-05 2003-06-09 주식회사 하이닉스반도체 Semiconductor package and fabricating method thereof
JP3629178B2 (en) * 2000-02-21 2005-03-16 Necエレクトロニクス株式会社 Flip-chip type semiconductor device and a manufacturing method thereof
JP3548082B2 (en) * 2000-03-30 2004-07-28 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP3446826B2 (en) 2000-04-06 2003-09-16 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
US6732913B2 (en) 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
JP3535804B2 (en) 2000-04-28 2004-06-07 Necマイクロシステム株式会社 Design method for flip chip type semiconductor device
JP3968554B2 (en) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 Method for manufacturing a bump forming method and a semiconductor device
US6362087B1 (en) 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
JP2002016096A (en) 2000-06-27 2002-01-18 Citizen Watch Co Ltd Semiconductor device and its manufacturing method
US6521996B1 (en) 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
TW464927B (en) 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
TW452950B (en) 2000-09-19 2001-09-01 Siliconware Prec Ind Co Ltd Packaging structure of bonding pad with increased space height
TW449813B (en) 2000-10-13 2001-08-11 Advanced Semiconductor Eng Semiconductor device with bump electrode
US6462426B1 (en) 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
TW577152B (en) 2000-12-18 2004-02-21 Hitachi Ltd Semiconductor integrated circuit device
US6319846B1 (en) * 2001-01-05 2001-11-20 Taiwan Semiconductor Manufacturing Company, Ltd Method for removing solder bodies from a semiconductor wafer
JP2002222823A (en) 2001-01-29 2002-08-09 Sharp Corp Semiconductor integrated device and its manufacturing method
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6495397B2 (en) 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection
US6653563B2 (en) 2001-03-30 2003-11-25 Intel Corporation Alternate bump metallurgy bars for power and ground routing
JP4092890B2 (en) 2001-05-31 2008-05-28 株式会社日立製作所 Multi-chip module
KR100456064B1 (en) 2001-07-06 2004-11-08 한국과학기술원 Anisotropic conductive film for ultra-fine pitch COG application
US20030020163A1 (en) 2001-07-25 2003-01-30 Cheng-Yu Hung Bonding pad structure for copper/low-k dielectric material BEOL process
US6372619B1 (en) * 2001-07-30 2002-04-16 Taiwan Semiconductor Manufacturing Company, Ltd Method for fabricating wafer level chip scale package with discrete package encapsulation
US6734568B2 (en) 2001-08-29 2004-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP3850261B2 (en) 2001-10-25 2006-11-29 イビデン株式会社 Semiconductor chip
EP1306898A1 (en) 2001-10-29 2003-05-02 Dialog Semiconductor GmbH Sub-milliohm on-chip interconnection
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6774475B2 (en) 2002-01-24 2004-08-10 International Business Machines Corporation Vertically stacked memory chips in FBGA packages
JP3829325B2 (en) 2002-02-07 2006-10-04 日本電気株式会社 The method of manufacturing a semiconductor device and a manufacturing method and a semiconductor device
JP3759909B2 (en) 2002-02-22 2006-03-29 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP3603890B2 (en) 2002-03-06 2004-12-22 セイコーエプソン株式会社 Electronic device and method of manufacturing the same, and electronic apparatus
KR20040111395A (en) 2002-03-12 2004-12-31 페어차일드 세미컨덕터 코포레이션 Wafer-level coated copper stud bumps
JP3856304B2 (en) 2002-03-25 2006-12-13 株式会社リコー Semiconductor device including a resistive element and csp in Csp
US6617655B1 (en) 2002-04-05 2003-09-09 Fairchild Semiconductor Corporation MOSFET device with multiple gate contacts offset from gate contact area and over source area
US6740577B2 (en) 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US20030218246A1 (en) 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
US6661100B1 (en) 2002-07-30 2003-12-09 International Business Machines Corporation Low impedance power distribution structure for a semiconductor chip package
US6750133B2 (en) 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
JP3969295B2 (en) 2002-12-02 2007-09-05 セイコーエプソン株式会社 Semiconductor device and manufacturing method and a circuit board and an electro-optical device, and electronic equipment
US7111265B1 (en) 2002-12-23 2006-09-19 Altera Corporation I/O pin placement for a programmable logic device
US6907589B2 (en) 2003-02-19 2005-06-14 Hewlett-Packard Development Company, L.P. System and method for evaluating vias per pad in a package design
US7008867B2 (en) 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
JPWO2004077556A1 (en) 2003-02-26 2006-06-08 三洋電機株式会社 The semiconductor integrated circuit device and method the power supply wiring
JP4318935B2 (en) 2003-03-05 2009-08-26 綜研化学株式会社 Obtained by using the manufacturing method and a manufacturing method thereof of the color display member reflective type color image display device
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
US7203916B2 (en) 2003-06-24 2007-04-10 International Business Machines Corporation System, method and program product for positioning I/O pads on a chip
US6977435B2 (en) 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
US7462942B2 (en) 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
EP1536469A1 (en) 2003-11-28 2005-06-01 EM Microelectronic-Marin SA Semiconductor device with connecting bumps
JP3973624B2 (en) 2003-12-24 2007-09-12 富士通株式会社 High-frequency devices
JP4278543B2 (en) 2004-03-19 2009-06-17 マルホン工業株式会社 Game machine
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4119866B2 (en) 2004-05-12 2008-07-16 富士通株式会社 Semiconductor device
JP2006128662A (en) 2004-09-30 2006-05-18 Taiyo Yuden Co Ltd Semiconductor and its mounting body
JP2006147810A (en) 2004-11-19 2006-06-08 Casio Comput Co Ltd Semiconductor device and method of manufacturing the same
US7135766B1 (en) 2004-11-30 2006-11-14 Rf Micro Devices, Inc. Integrated power devices and signal isolation structure
US7119002B2 (en) 2004-12-14 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump composition for flip chip
US7084660B1 (en) 2005-04-04 2006-08-01 International Business Machines Corporation System and method for accelerated detection of transient particle induced soft error rates in integrated circuits
JP4774248B2 (en) 2005-07-22 2011-09-14 Okiセミコンダクタ株式会社 Semiconductor device
US7335536B2 (en) 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US20080284037A1 (en) 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668484A (en) * 1970-10-28 1972-06-06 Rca Corp Semiconductor device with multi-level metalization and method of making the same
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
US4825276A (en) * 1986-06-19 1989-04-25 Nec Corporation Integrated circuit semiconductor device having improved wiring structure
US4726991A (en) * 1986-07-10 1988-02-23 Eos Technologies Inc. Electrical overstress protection material and process
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4811237A (en) * 1987-06-19 1989-03-07 General Electric Company Structured design method for generating a mesh power bus structure in high density layout of VLSI chips
US5108950A (en) * 1987-11-18 1992-04-28 Casio Computer Co., Ltd. Method for forming a bump electrode for a semiconductor device
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
US5137845A (en) * 1990-07-31 1992-08-11 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
US5326709A (en) * 1991-12-19 1994-07-05 Samsung Electronics Co., Ltd. Wafer testing process of a semiconductor device comprising a redundancy circuit
US5780925A (en) * 1992-10-28 1998-07-14 International Business Machines Corporation Lead frame package for electronic devices
US5656863A (en) * 1993-02-18 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Resin seal semiconductor package
US5418186A (en) * 1993-07-15 1995-05-23 Samsung Electronics Co., Ltd. Method for manufacturing a bump on a semiconductor chip
US5631499A (en) * 1994-04-28 1997-05-20 Kabushiki Kaisha Toshiba Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5600180A (en) * 1994-07-22 1997-02-04 Nec Corporation Sealing structure for bumps on a semiconductor integrated circuit chip
US5598348A (en) * 1994-09-22 1997-01-28 Sun Microsystems, Inc. Method and apparatus for analyzing the power network of a VLSI circuit
US5534465A (en) * 1995-01-10 1996-07-09 At&T Corp. Method for making multichip circuits using active semiconductor substrates
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US5898222A (en) * 1995-05-12 1999-04-27 International Business Machines Corporation Capped copper electrical interconnects
US6229220B1 (en) * 1995-06-27 2001-05-08 International Business Machines Corporation Bump structure, bump forming method and package connecting body
US5757074A (en) * 1995-07-07 1998-05-26 Hughes Electronics Corporation Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements
US5629241A (en) * 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5874781A (en) * 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US20030151047A1 (en) * 1995-11-17 2003-08-14 Corbett Tim J. Semiconductor reliability test chip
US5756370A (en) * 1996-02-08 1998-05-26 Micron Technology, Inc. Compliant contact system with alignment structure for testing unpackaged semiconductor dice
US5883435A (en) * 1996-07-25 1999-03-16 International Business Machines Corporation Personalization structure for semiconductor devices
US5866949A (en) * 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5946590A (en) * 1996-12-10 1999-08-31 Citizen Watch Co., Ltd. Method for making bumps
US6518651B2 (en) * 1997-01-17 2003-02-11 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US5877078A (en) * 1997-04-08 1999-03-02 Sony Corporation Method of manufacturing a semiconductor device
US6028363A (en) * 1997-06-04 2000-02-22 Taiwan Semiconductor Manufacturing Company Vertical via/contact
US5882957A (en) * 1997-06-09 1999-03-16 Compeq Manufacturing Company Limited Ball grid array packaging method for an integrated circuit and structure realized by the method
US6051450A (en) * 1997-07-01 2000-04-18 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US5933358A (en) * 1997-09-30 1999-08-03 Synopsys, Inc. Method and system of performing voltage drop analysis for power supply networks of VLSI circuits
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US5903343A (en) * 1997-12-23 1999-05-11 Siemens Aktiengesellschaft Method for detecting under-etched vias
US6177731B1 (en) * 1998-01-19 2001-01-23 Citizen Watch Co., Ltd. Semiconductor package
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US7338890B2 (en) * 1998-03-31 2008-03-04 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US6198619B1 (en) * 1998-04-24 2001-03-06 Mitsubishi Denki Kabushiki Kaisha Capacitor network
US6043672A (en) * 1998-05-13 2000-03-28 Lsi Logic Corporation Selectable power supply lines for isolating defects in integrated circuits
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US6077726A (en) * 1998-07-30 2000-06-20 Motorola, Inc. Method and apparatus for stress relief in solder bump formation on a semiconductor device
US6194309B1 (en) * 1998-08-10 2001-02-27 Samsung Electronics Co., Ltd. Method for forming contact
US6229711B1 (en) * 1998-08-31 2001-05-08 Shinko Electric Industries Co., Ltd. Flip-chip mount board and flip-chip mount structure with improved mounting reliability
US6187680B1 (en) * 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
US6268662B1 (en) * 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
US7220657B2 (en) * 1999-01-27 2007-05-22 Shinko Electric Industries, Co., Ltd. Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
US6675139B1 (en) * 1999-03-16 2004-01-06 Lsi Logic Corporation Floor plan-based power bus analysis and design tool for integrated circuits
US6197613B1 (en) * 1999-03-23 2001-03-06 Industrial Technology Research Institute Wafer level packaging method and devices formed
US6271107B1 (en) * 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
US6406967B1 (en) * 1999-08-06 2002-06-18 Samsung Electronics Co., Ltd. Method for manufacturing cylindrical storage electrode of semiconductor device
US6207467B1 (en) * 1999-08-17 2001-03-27 Micron Technology, Inc. Multi-chip module with stacked dice
US6709985B1 (en) * 1999-08-26 2004-03-23 Advanced Micro Devices, Inc. Arrangement and method for providing an imaging path using a silicon-crystal damaging laser
US6372622B1 (en) * 1999-10-26 2002-04-16 Motorola, Inc. Fine pitch bumping with improved device standoff and bump volume
US6558978B1 (en) * 2000-01-21 2003-05-06 Lsi Logic Corporation Chip-over-chip integrated circuit package
US6538331B2 (en) * 2000-01-31 2003-03-25 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6765299B2 (en) * 2000-03-09 2004-07-20 Oki Electric Industry Co., Ltd. Semiconductor device and the method for manufacturing the same
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6405357B1 (en) * 2000-05-02 2002-06-11 Advanced Semiconductor Engineering, Inc. Method for positioning bond pads in a semiconductor die
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6683380B2 (en) * 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6518092B2 (en) * 2000-07-13 2003-02-11 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US20020043723A1 (en) * 2000-10-16 2002-04-18 Hironobu Shimizu Semiconductor device and manufacturing method thereof
US6348401B1 (en) * 2000-11-10 2002-02-19 Siliconware Precision Industries Co., Ltd. Method of fabricating solder bumps with high coplanarity for flip-chip application
US6523154B2 (en) * 2000-12-14 2003-02-18 International Business Machines Corporation Method for supply voltage drop analysis during placement phase of chip design
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
US6861742B2 (en) * 2001-01-18 2005-03-01 Renesas Technology Corp. Wafer level chip size package having rerouting layers
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
US6917119B2 (en) * 2001-09-17 2005-07-12 Megic Corporation Low fabrication cost, high performance, high reliability chip scale package
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
US6541847B1 (en) * 2002-02-04 2003-04-01 International Business Machines Corporation Packaging for multi-processor shared-memory system
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US7045899B2 (en) * 2002-10-15 2006-05-16 Oki Electric Industry Co., Ltd. Semiconductor device and fabrication method of the same
US20040088443A1 (en) * 2002-10-29 2004-05-06 Broadcom Corporation Multipurpose and programmable pad ring for an integrated circuit
US6756664B2 (en) * 2002-11-22 2004-06-29 Via Technologies, Inc. Noise eliminating system on chip and method of making same
US6991961B2 (en) * 2003-06-18 2006-01-31 Medtronic, Inc. Method of forming a high-voltage/high-power die package
US7495341B2 (en) * 2003-07-03 2009-02-24 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7479398B2 (en) * 2003-07-03 2009-01-20 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US20050090916A1 (en) * 2003-08-25 2005-04-28 Majid Aghababazadeh Intra-chip power and test signal generation for use with test structures on wafers
US20050050502A1 (en) * 2003-08-27 2005-03-03 Fujitsu Limited Method and apparatus for designing semiconductor integrated circuit
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
US7224056B2 (en) * 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US20060080630A1 (en) * 2003-11-02 2006-04-13 Mentor Graphics Corp. Power/ground wire routing correction and optimization
US7043389B2 (en) * 2004-02-18 2006-05-09 James Francis Plusquellic Method and system for identifying and locating defects in an integrated circuit
US7505284B2 (en) * 2005-05-12 2009-03-17 International Business Machines Corporation System for assembling electronic components of an electronic system
US7246432B2 (en) * 2005-06-28 2007-07-24 Seiko Epson Corporation Method of manufacturing semiconductor device
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7074050B1 (en) * 2005-11-17 2006-07-11 International Business Machines Corporation Socket assembly with incorporated memory structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030010B2 (en) * 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US9653418B2 (en) 2012-09-20 2017-05-16 Taiwan Semiconductor Manufacturing Company Packaging devices and methods
US10079200B2 (en) 2012-09-20 2018-09-18 Taiwan Semiconductor Manufacturing Company Packaging devices and methods
US20150235071A1 (en) * 2014-02-17 2015-08-20 J-Metrics Technology Co., Ltd. Biometrics Sensor Having Flat Contact Surface Formed by Signal Extending Structure and Method of Manufacturing Such Sensor

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