TW419764B - Manufacturing method and structure of wafer size packaging - Google Patents

Abstract

The present invention provides a manufacturing method and structure of wafer size packaging. The characteristic of the process is: by using techniques such as printing, coating or adhering technology, etc. to deposit one layer of plastic material on top of the passivation layer to form a plurality of separated islands of which the thickness is less than 100 mu m, and then rearrange the process via I/O to form the leads to connect the above mentioned islands and the bonding pad on the wafer surface so that the bonding pads can be connected with the islands one-by-one, then deposit an organic material on top of the lead to isolate the lead on top of the islands which is exposed as mentioned above, and then form an UBM layer on top of the lead which is on top of the exposed islands, and set suitable solder ball with proper size by one of the electroplating, printing or ball setting technology to finish the wafer size packaging.

Description

419764 V. Description of the invention (1) [Scope of the invention] The present invention relates to a manufacturing method and structure of a wafer size structure, and particularly to a method for packaging all the dies on a wafer at the same time. A manufacturing method of cutting each die to reduce the packaging cost of the integrated circuit. [Background of the Invention] In the current semiconductor device manufacturing technology, most of the high-density semiconductor devices are obtained by increasing the circuit density of the semiconductor device or reducing the size of the device. However, as a result, due to the reduction in the size and density of the device, Leading to increasingly stringent requirements for packaging and interconnecting technology. 'One of the methods used to package the chip is Flip-Chip Interconnection M ethod. This flip-chip bonding The technology is to replace the lead frame with a metal conductor, that is, to connect the bare crystal to the substrate with the surface facing down. The metal conductor can be metal bumps, tape-tape bonding (Tape- (Automated Bonding), Anisotropic Conductive Adhesives, Polymer Bump, etc., among which metal bumps are the mainstream of flip-chip bonding technology, and the material of metal bumps is tin-lead alloy. Mainly, therefore, metal bumps made of tin-lead alloy are also called tin-lead bumps, which use the method of tin-lead bumps to join First, a tin bump bump is formed on the surface of the semiconductor die, and then the aluminum pad (A 1 Bonding Pad) of the wafer is bonded to the substrate circuit by melting the tin-lead bump to complete the assembly. Lead & block contacts are arranged in an area array on the surface of the die, which can increase the

Page 4 419764 V. Description of the invention (2) Pitch ‘to improve manufacturing yield’. At present, methods for producing tin-lead bumps include evaporation, electroplating, and printing. In addition to the above-mentioned technologies, there are still other technologies that can grow tin fault & blocks on various substrates, such as one of the solder-paste screening methods commonly used in 8 11-inch wafer packaging. ), However, with the reduction in component size and the reduction of the pitch of tin-lead bumps, solder paste printing becomes more impractical when applied to fine-pitch products due to the following reasons, The first point is that since solder paste is formed by flux and solder alloy particles, it is one thing to control the composition and uniformity of the solder paste compound when the volume of tin-lead bumps is reduced. It is very difficult. In view of this point, the conventional method has disclosed a kind of fine particles with uniform particle size to improve the above disadvantages. However, this will inevitably increase the production cost. The second point is when using this tin When the printing technology is used to manufacture Nanchao semiconductor devices, the spacing between two tin and four blocks becomes very limited. This is because when tin changes from a flowing state to a solid state, its volume will be greatly reduced, which makes the The result is that the diameter of the solder paste printing holes (Screen Ho 1 es) will become larger than the actual tin-lead bumps. 'The significant reduction in the volume of the above-mentioned solder bumps will also cause solder paste printing technology to produce high Difficulties for density components. Other technologies that can produce tin bumps include C4 (Controlled Collapse Chip Connection Technique) and Thin Film Electrodeposition Technique. Both have also been applied to the manufacture of semiconductor components in recent years, of which C4 technology is limited. Yu Zai

419764 V. Description of the invention (3) —-— Molybdenum mask core sk must be used in the process of clothing to define the pattern size of the layer and the tin-lead bumps, because the accuracy of the alignment of the molybdenum mask is not high, so It is difficult to make fine pitches (that is, pitches <15 ° tin-lead bumps) using C4 technology. Similarly, thin film plating technology is also limited by the need to deposit a UBM layer and coat it on the process. Thick photoresistor, because of its poor accuracy in alignment, it also has the disadvantage of being unable to make fine-pitch tin-lead bumps with the same. Among them, the manufacturing flow chart of thin film electroplating technology used to make tin tin balls is known. As shown in "Figures 1A to 1F". One of the conventional semiconductor structures is shown in Figure A. This semiconductor structure 10 is built on a silicon substrate 12 'Its manufacturing method is to first form a bond pad 14 on the top surface 16 of the silicon substrate 12' to be used as the electrical connection between the silicon substrate 12 and the outer substrate circuit 'The solder pad 14 is made of conductive metal ( Such as any of aluminum, copper 'aluminum alloy, or copper alloy) Then, a lithography technique is used to open a window 22 on the bonding pad 14 for electrical connection, and at the same time, a protection layer 20 is deposited on the silicon substrate 12 to protect the bonding pad 14, which is a compliance layer The 20 is made of an insulating material, and the insulating material may be an oxide, a nitride, or an organic material. Next, a welding gold is deposited on the top surface 24 of the protective layer 20 and the top surface 18 exposed by the bonding pad 14. Phase layer (Under Bump Metallurgy, this UBM layer can also be called BLM layer 'Ball Limiting Metallurgy layer) 26 (as shown in Figure 1B), this UBM layer 26 is composed of an adhesion / diffusion barrier layer (Adhesion / Diffusion Barrier Layer ) 3 0 and a wetting layer (also known as a tin layer) 28, in which

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V. Description of the invention (4) The barrier layer 30 may be made of titanium (Ti), titanium nitride (TiN), chromium (cr), or a metal material thereof, and the wet layer 28 may be made of copper (cu) or nickel (Ni: ^ is made of one of the materials, among which the above-mentioned UBM layer 26 is mainly used to improve the adhesion relationship between the tin-lead ball to be formed # and the top surface 18 of the pad 14.。 As shown in Figure ic Indicating 'In this step, a photoresist layer 34 is deposited on the surface of the UBM layer 26, and then the method of exposure and development is used to define a window opening 38 for the tin ball to be long, and then The electrical redundancy method forms a tin-lead bump 40 in the window opening 38, and the thickness of the aforementioned photoresist layer 34 is generally maintained between 3 0 // m ~ 8 0 &quot; m, and preferably maintained at 5 The thickness of this photoresist layer 34 is related to whether a fine-pitch tin-lead bump 40 can be made. When the photoresist layer 34 is thicker, the alignment accuracy is worse. The fine-pitch tin-lead bump 40 is made, but because the thickness of the photoresist layer 34 is proportional to the height of the tin-lead bump 40, the photoresist layer 34 must have a certain thickness, so it must be carefully The thickness of the photoresist layer 34 is selected, and in this step, a sufficiently thick photoresist layer 34 is used to make a mushroom-shaped tin boat bump 40. As shown in FIG. 1E, when a tin-lead bump is formed After block 40, the photoresist layer 34 is removed by a wet stripping process. At this time, the fragrant tin-lead bump 40 and the UBM layer 26 are maintained in the original state, and then the next step is performed. 'As shown in FIG. 1F, in this step, the tin-lead bump 40 is used as an etch-blocking mask, and the excess υβΜ layer 26 is etched clean using a wet etching process.' Then, a heavy-flow process (R ef 1 〇WP r 〇cess) Heat the tin-lead bump 40 at a temperature higher than the melting point of the tin boat bump 40, so that the tin-lead bump 40 changes from a solid state to a liquid state. Finally, the tin-lead bump is made during the cooling process. 4〇 Cohesion by itself

419764 V. Description of the invention (5) p 'force to form a spherical tin-lead ball 42. At this step, the manufacture of the tin-lead ball 42 is completed. In recent years, "Chip Scale Packages (CSP) have been used to manufacture high-capacity integrated circuit wafers." This-wafer size packaging is a low-cost packaging technology, one of which is Proposed by Tessera Company, they also call this technology

micro-BGA (Ball Grid Array) packaging method, this kind of micro-BGA packaging method is a high-density packaging method, and it combines the advantages of flip-chip assembly and surface-adhesive packaging, using the chip size packaging technology to package the entire The chip does not need to form a tin-lead ball for a special bonding process like a traditional flip-chip package. In addition, the chip size package can provide a larger number of input / output contacts than the traditional Quad Flat Package technology. / Output Terminal). The difference between this wafer size structure and other structure technologies is that it has an intermediate poser (Inter poser Layer). The intermediate poser is made of a flexible and flexible material. The intermediate poser Not only can absorb the mechanical stress generated in the packaging step, but also allow the thermal expansion caused by the different thermal expansion coefficient when the die is bonded to the substrate, that is, the role of the interposer here is a stress buffer layer and thermal expansion relief In addition, the chip size structure also has other features, that is, the same as the micro-BGA package, which can be used for surface mounting technology (SMT) process and circuit board assembly work. In a typical micro-BGA package, a flexible interposer (which may contain circuits) is used to bond the solder on the surface of the integrated circuit chip.

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41 9764 V. Description of the invention (7)), a plurality of integrated circuit dies 46 ′ are formed on the top surface of the aforementioned silicon wafer, and each integrated circuit die 46 has at least one formed on the first insulating layer 50 The first I / O pad 4 8 is then deposited on the surface of the wafer-a second insulating layer 5 4 ′ and defines the second insulating layer to form a columnar opening, and the conductive material is injected into the columnar opening. A conductive metal pillar 52 is formed, and then a conductive metal layer 56 is deposited on top of the second insulating layer 54. This conductive metal layer 56 will be defined in the subsequent process to form a conductive wire 58. The I / O is welded by the extension of the conductive wire 58塾 This extends from the periphery of the integrated circuit die to the center of the die, and is arranged on the die surface in the form of a face matrix. A third insulating layer 60 is deposited on top of the wire 5 8 and defines the third insulating layer. 60 so that the end of the wire 58 can be exposed to form a second I / O pad; a UBM layer 62 is deposited on the aforementioned second 1 / () solder pad and a solder ball 66 is formed on the top surface 64 of the UBM layer 62 The shore, in the process described, is a method of providing a stress buffering layer for the solder ball 66. The total 呷 Ϊ = layer of the integrated circuit die 46, but considering the aforementioned elastic material layer will be consumed along with the price problem, so if a structural stress buffer layer can be provided and its construction cost is lower The wafer size table is necessary. [Objective and Summary of the Invention] The main purpose of the system is to provide a wafer size structure to improve the conventional structure method. The purpose of the method is to provide a manufacturing method of wafer size structure without coating the entire surface of the wafer with an elastic material layer.

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V. Description of the invention (6) = Tin-lead bumps on the surface of the flexible circuit board (nexiMe CircuH). The thickness of the medium flexible circuit board is about 25 Ren m, which is made of a high-knife 9 ^ material such as Juya Poliminide is made with a thickness of approx. Shixi · Rubber elastic 丨 Siiicone £ iast〇meric Layer is made by bonding · This ... The silicone elastomer layer can provide flexibility in three directions and can be used The flexibility j reduces the stress generated during the manufacturing process and the thermal expansion caused by the loss of the die-substrate cooperation. In order to further reduce the cost of packaging integrated circuit components, it is possible to package the dies on a round surface at the same time. 'After the packaging is completed, the dies are cut to 1J.' This not only has the advantages of chip packaging, but also It can further reduce the packaging cost of integrated circuit die. At present, most integrated circuit chips (IC Chips) are designed to have I / O pads arranged in a peripheral matrix (Periphera 〖Array). For today's local density semiconductor components, the The pitch is constantly shrinking. Therefore, in order to improve the size of the I / 〇 pads, an I / O pad redistribution process is often used to enable the I / O pads to pass from the periphery. The matrix is arranged into an area array (Area Array), and in the process of I / O welding pad redistribution, the I / O welding pad is often extended from the periphery of the die to the middle of the die by a metal wire. 'In order to determine the reliability of the wafer, a stress buffer layer is formed under the metal line to buffer the stress generated during the manufacturing process. In the conventional method for forming a wafer size structure, each integrated circuit die is accompanied by an I / 〇 reallocation, and its structure is shown in "Figure 2". The manufacturing method of the wafer size structure 44 includes Yes: First provide a silicon wafer (not

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Another object of the present invention is to provide a crystal method ', which can package all the dies on the wafer at the same time = sacrificial slicing to reduce the packaging cost of the integrated circuit. Then, the mother crystal is another object of the present invention to provide a wafer sizing method, which is printed on the top of the wafer with an elastic material: = islands (Us — Slands), each island === Solder balls will form during the subsequent process. The top 4 is another aspect of the present invention to provide a wafer size configuration method. An elastic material layer is printed on the top of the wafer to separate islands, and then redistributed through the I / 〇 process. Shape the aforementioned islands and welding pads. &quot; Another object of the present invention is to provide a manufacturing method of wafer size structure. A stress buffer layer composed of an elastic material is formed on the bottom of the solder ball. S Moduies / less than 6MPa 'thickness is not more than 100. Another object of the present invention is to provide a wafer size structure, the structure includes a plurality of wafers formed on the surface of the wafer and formed of an elastic material. A plurality of separated islands and enable the ball to be recorded on the described islands in the subsequent process. 'The foregoing islands are used as a stress buffer layer to achieve the desired stress buffering effect. The final purpose is to provide a wafer-size package. This package is formed with a protective layer, an elastic layer, an I / 0 redistribution metal layer, an organic material layer, a UBM layer, and a UBM layer. Solder ball on top ^

Page 11 419764 V. Description of the invention (9)-'1 ·' 'In order to achieve the above-mentioned purpose' The manufacturing method of the wafer size structure disclosed in the present invention includes at least the following steps: Crystal: The top of the wafer described in the above f has at least two pads; a round top that protects Zhan Yuhai is deposited and the top surface of the pad is exposed; a layer of elastic material is printed on top of the 4 protective layer to Forming a plurality of separated islands; forming / 〇 reallocating wires between the pads and the islands so that 2 of the pads can form an electrical connection with one of the islands; forming A f-machine material layer is on the top of the wafer, and the tops of the islands are exposed. A plutonium wire to form a pbM layer on top of the wire and the islands exposed; and implanting a plurality of solder balls on top of the UBM layer so that the solder ball can pass through the islands The material provides a stress buffering effect. ^ In the above method, the method further includes the following steps: depositing a protective layer composed of an insulating material, such as silicon oxide (Si 1 icone 〇xlde) or silicon nitride (Si} icone Nitnde); printing a An elastic material layer composed of a material having sufficient stress buffering properties; and printing an elastic material layer having a lower Young's modulus (&lt; 6 MPa). The above method may further include the following steps: forming a plurality of islands having a thickness of not more than 00 A m, and the habitability of the aforementioned islands is preferably not more than 5Q. The manufacturing method of the wafer size structure may further include the following steps: depositing a protective layer composed of an insulating material such as silicon oxide or silicon nitride; depositing a photoresist layer on top of the aforementioned protective layer; patterning The photoresist layer; and developing the photoresist layer to expose at least two pads. And this method may further include a step of printing a layer of elastic material. The aforementioned printing method may be achieved by stencil printing or screen printing.

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Η Page 12, ί 419764 V. Description of the invention (10) In addition to the above steps, this method is a step (S p u 1: t r i n g T e c h n i q u e) or wire step, the aforementioned wire is composed of one or a mixture of aluminum alloys. The detail includes an I / 0 redistribution conductor, copper, Shao alloy, copper alloy or Shao copper formed by electroplating technology and electroplating technology. In the above process, the detail includes the following steps: A metal layer composed of an alloy, a copper alloy, or an oil alloy; depositing a photoresist layer on the top surface of the metal layer; defining the photoresist layer to form an I / O redistribution wire; and etching 1/0 redistribution wire to make the foregoing The wires can connect the pads to the plurality of islands, and the organic material layer can be made of a light-sensitive material, so that the organic material layer can be patterned in a subsequent process to expose the wires on the top of the islands. This method further includes the steps of forming a UBM layer by one of techniques such as electroless plating, electroplating, or ore reduction. More specifically, this method further includes the following steps: forming a UBM layer on a crystal A round surface, forming a photoresist layer on the surface of the aforementioned ϋBM layer, and a mask define and etch away a portion of the UBM layer, so that the UBM layer covers only a plurality of islands. This method further includes a step of solder balls by electroplating, printing or pick and implantation. According to the above manufacturing steps, the wafer size structure is formed. The package includes at least: a pre-processed wafer having at least two pads on top of the wafer; a protective layer 'formed on top of the wafer and exposing the top surface of the pads; a plurality of separate Islands 'the aforementioned islands are made of an elastic material and are formed on top of the aforementioned protective layer; at least two 丨 / 〇 redistribution wires' are used to connect the aforementioned islands and pads so that the islands versus

419764 V. Description of the invention (11) The pads can be electrically connected in a one-to-one manner; ~ On the surface of the aforementioned wafer, so that the island-shaped organic material layer is covered to form electrical insulation; a UBM layer is formed on The energy part of the area other than the wire, and a plurality of ball balls are formed on the top of the wire of the front island. In the crystal size structure, the protective layer is composed of insulating materials such as = top two V '. Elastic material composed of a plurality of separated compounds or silicified compounds, and the poplars are made of low Young's thickness ㈣ ... and; any of gold, copper alloys or aluminum-copper alloys: aluminum The ancient aluminum alloy is made of concentric materials, so as to facilitate the subsequent definition and lithography steps. The purpose, characteristics and advantages of the aluminum alloy can be more clearly and easily understood as follows: '+ 实 ％ 例' [Brief description of the figure] Section U is a flow chart of the conventional Lidian technology; $ 幻 衣 w Figure 2 is a cross-sectional view of a conventional wafer size structure, which is shown on the entire surface of the wafer to be deposited. An elastic material layer; FIG. 3 shows the formation of a plurality of separation islands according to the present invention Flow chart of the object and the implantation of solder balls on the aforementioned islands; &quot; Sections 4A to 4G are cross-sectional views of each step of the wafer size fabrication method of the present invention; and / 'FIG. 5, This is a cross-sectional view of the wafer size structure of the present invention, which shows ΗΓΗ Page 14 4l ^ re4 5. Description of the invention (2) Two separated integrated circuit die are connected to each other by drawing lines. [Example [Explanation] According to the manufacturing method of the wafer size structure disclosed in the present invention, an integrated circuit die having a pad and a protective layer is provided first, and then printed on a steel plate on the top of the protective layer (also can be screened) Plate printing) method to form a plurality of separate islands composed of elastic materials, and then implant 2 balls on the top of the islands, where the aforementioned islands can provide sufficient stress buffering effect, and the steel of the aforementioned elastic material layer The lithographic printing process is not only easy to achieve, but because it does not require lithography in the process steps, it can reduce costs and form multiple points by using an elastic material with a low Young's modulus (whose Young's modulus is less than 6 MPa). Of the island , Depositing and forming I / 0 redistribution wires on top of integrated circuit die 'to connect pads and islands, then on top of integrated circuit = build an organic material layer' and define the aforementioned organic material layer to expose The wire located at the top of the + island is deposited on top of the island line, and a BM layer is deposited on the top of the island line, and a solder ball is implanted in the aforementioned μ part by one of the plating or printing technology. A wafer size structure is provided. The structure has a plurality of solder balls with a round surface at 0, where the solder balls are formed on the top of an island formed by physical stress and punching material. The aforementioned island shape &lt;: = provides the desired stress buffering effect; at the same time, according to the d two-core method disclosed in the present invention, all the dies on the wafer can be packaged at the same time, and then: BB particles are cut to reduce the product The cost of the body circuit is a low-cost construction method. ° Refer to Figure 3 ", which is a flowchart of the process of the present invention

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Five 'Invention Explanation (13) Reason a ^ 3, not in step 72' is provided first-the wafer has been pre-determined whether it is defective; later, technologies such as steel reel printing or screen printing will- !! The raw material is formed on the surface of the wafer, and a plurality of separated islands will be formed in the foregoing bombs. 1 front ^ back, the process 秌 inn „The thickness of this island is not much 100 &quot;, preferably No more than 50 &quot; Then proceed to the second step and define the aforementioned thin metal layer through lithography technology: the wire formed by forming a redistribution wire is used to connect the welding pad and the island; Yu Island An insulating organic material is deposited on the top surface of the object. This is the fourth step 78. The aforementioned organic material is preferably light sensitive, so that it can be patterned and defined in the subsequent process to expose the top of the island and the location of the island. The wire above the island; then a fifth step 80 is performed, a UBM layer is deposited on top of the aforementioned wire; and in a sixth step 82, a solder ball is implanted on top of the aforementioned UBM layer to complete the wafer size The above flow chart is an introduction to the manufacturing method of the wafer size structure disclosed in the present invention, and the detailed steps in the process are matched with each step of the wafer size structure method shown in "Figure 4A ~ 4G". The sectional view is explained below. First, please refer to “FIG. 4A”, which is a cross-sectional view of one integrated circuit die on the wafer surface. As shown in FIG. 4A, this integrated circuit die 84 has at least two formed in integrated circuits. The pad 86 on the top surface 88 of the die 84, as shown in "Fig. 4B", deposits a dielectric layer (or protective layer) 90 on the wafer surface and is defined by a mask. A portion of the dielectric layer 90 is removed by etching, and the top surface of the bonding pad 86 is exposed. The foregoing bonding pad 86 is formed of a conductor, such as copper, copper, iS alloy, copper alloy, or copper alloy.

Page 16 419764 V. Description of the invention (14) Describe the top of the dielectric layer 90. In the subsequent process, screen printing or Stencil printing can be used to print a flexible film. Material layer, the elastic material layer includes a plurality of separated islands 92, and the material of the elastic material layer is preferably Silicone Rubber or Fluorosilicone

Rubber), and it is best to choose a low Young's coefficient ^ ⑽㈣,

Modules) elastic materials, the Young's coefficient is preferably less than 20-3, more preferably 10MPa, and most preferably less than 6Mpa. And the thickness of the aforementioned island 92

The degree is preferably not more than 100 μm, and more preferably not more than 50 ° m, as shown in "Figure 4C", but it should be noted here that the appearance of the island 92 is not limited to the shape shown in "Figure 4C," It can also be semi-circular, semi-elliptical, or other shapes. As shown in Figure 4D, it is deposited and the metal layer is deposited on the wafer surface in the next step. It mask defines the aforementioned thin metal layer to form the wire 94, The method of depositing a thin metal layer as used for the redistribution of O / O is not limited, and the user may select an appropriate method. The aforementioned wire 94 is used to connect the island 92 and the bonding pad 86. The "4D image" is shown and the second line is composed of aluminum, copper or UBM layer material. # 4 After the wire 94 is formed: continue to deposit an organic material layer 96 on: (Ph as 1; 4E. :: ": λ This organic material layer is preferably made of light-sensitive: 〇 (Photsensentlve) To facilitate the subsequent use of the lithography technique to expose the conductive wire 94 on the island 92, and the material of the basin material layer 96 may be polyimide (benzene). You have ene ⑸⑺ ⑸⑺ ❹ "吡 ❹: ^ ^ 匸 ... or other polymer materials

4ί9764 V. Description of the invention () 5) One --- The method for depositing the organic material layer 96 can be applied by spin coating (Spin

Coating), printing (pr_jnting) or bonding process; wherein when the aforementioned organic material is a photo-sensitive material, it is not necessary to deposit a photoresist material on top of the organic material layer in the subsequent lithographic process. · After the organic material layer 96 is deposited, a UBM layer is deposited on the wafer surface, and the aforementioned υβM layer is defined by lithography and part of the UBM layer is removed by etching, leaving only the aforementioned wires 94 and islands. The top ⑽μ layer 98 is shown in "Fig. 4F". Then proceed to the last step, as shown in the "Figure 4G", the solder ball 100 is implanted on top of the aforementioned UBM layer 98. The solder ball can be implanted by plating, printing or ball implantation. Achieved, and the diameter of the solder ball is at least 60 μm. According to the manufacturing steps of "Figures 3 ~ 4G", a wafer size structure can be produced. The structure of this structure 102 is shown in "Figure 5", where the structure contains two integrated circuit dies (84, 104) 'The two integrated circuit dies (84, 104) can be cut by the Scribe Line 106 to obtain two separate integrated circuit dies, but before the cutting step / It must be confirmed whether the die on the surface of the wafer has been completely packaged after the wafer size configuration is completed. Of course, in this embodiment, two integrated circuit die (84, 104) are used as an example. The facts The surface of the previous wafer (such as an eight-inch wafer) contained hundreds of dies. ^ [Effects of the invention] According to the wafer size assembly method disclosed in the present invention, the dies on the wafer surface can be packaged at the same time, and the dies are cut to 0Θ after the package is completed.

Page 18 V. Description of the invention (16) Cutting. In this way, not only can the problems caused by conventional die packaging be improved, but the packaging cost of integrated circuit die can be greatly reduced. At the same time, the invention forms a layer of elastic material on the surface of the wafer by printing (such as steel plate or screen printing) to form a plurality of separate guides to provide sufficient stress buffering effect, unlike It is conventionally known that an elastic material layer needs to be deposited on the entire surface of the wafer, and because the printing process of the present invention is easy to implement, and lithography technology is not required in subsequent processes, packaging costs can be effectively reduced. [Explanation of Schematic Symbols] 10 .................. Semiconductor Structure 12 ............. Stone Evening substrate 14 ............................... 16 ........ Top surface 18 ............. Top surface 2 0 ............. Protective layer 22. ..... window 24....... 26 top surface ... ..._ layer 28 ........ wet layer 30 ........ ........ adhesion / diffusion barrier layer 34 ........ photoresist layer 38 .............. ........ window opening 40 ............ tin-lead bump 42 ............. ... Tin Shot

Page 19, 419764 V. Description of the invention (17) 4 4 ....... Wafer size configuration 46 .............. .... Integrated Circuit Die 48 ....... First I / O Pad — 50 .............. .... First Insulation Layer-5 2 ........ Conductive Metal Post 54 ....... .Second insulation layer 56 ..... conductive metal layer 58 ......... conductor 60 .................. the third insulation layer 62 ........ UBM layer 6 4 .. ................... TOP 66 ....................... Ball Ball 70 ..... ............ Flowchart 72 ............ First Step 7 4 ............. ..... second step 76 ......... third step 78 ......... ....... Fourth step 8 0 ......... Fifth step 82 ............ ..... The sixth step 84.... ..Pad 90 ........ dielectric layer 92 ........ island 94 ..................... 'line

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Claims (1)

6. Scope of Patent Application 1. A manufacturing method of wafer size structure, including at least the following steps: providing a pre-processed wafer, wherein the wafer has at least two pads on the top; 'depositing a protective layer on the The top of the wafer, and the top-side of the pad is exposed; a layer of elastic material is printed on top of the protective layer to form a plurality of separated islands; I / 0 redistribution wires are formed on the pad and the pads Between the islands, so that one of the pads can form an electrical connection with one of the islands; forming an organic material layer on the top of the wafer, and exposing the wires formed on the tops of the islands Forming a UBM layer on top of the wires and the islands exposed to the outside; and implanting a plurality of solder balls on top of the UBM layer so that the solder balls can provide stress through the islands Buffer effect. 2. The manufacturing method of the wafer size structure as described in item 1 of the scope of the patent application, wherein the method further includes a step of depositing the protective layer composed of an insulating material such as a stone oxide or a stone nitride. 3. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the method further includes a step of printing the elastic material layer composed of a material having sufficient stress buffering characteristics. 4. The manufacturing method of wafer size structure as described in item 1 of the scope of patent application, wherein the method further includes a printing method with a Young's coefficient of less than 10 Μ P a Page 22 419764 6. The steps of the elastic material layer composed of the materials covered by the patent application. 5. The manufacturing method of wafer size structure as described in item 1 of the scope of the patent application, wherein the method further includes a step of forming a plurality of islands having a thickness of less than or equal to ′ 1 0 0 // m. 6. The manufacturing method of wafer size structure as described in item 1 of the scope of the patent application, wherein the method further includes a step of forming a plurality of islands having a thickness of less than or equal to 50 a m. 7. The manufacturing method of the wafer size structure as described in item 6 of the patent application scope, wherein the method further includes the following steps: depositing a protective layer on the surface of the wafer, wherein the protective layer is made of silicon oxide or Composed of an insulating material such as silicon nitride; depositing a photoresist layer on top of the protective layer; patterning the photoresist layer; and developing the photoresist layer to expose the bonding pad. 8. The manufacturing method of wafer size structure as described in item 1 of the scope of patent application, wherein the method further includes printing the elasticity by one of techniques such as stencil printing, screen printing, coating or gluing. Steps in the material layer. 9. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the method further includes a step of forming the I / 0 redistribution wire by a sputtering technique. 10. The method for fabricating a wafer size structure as described in item 1 of the scope of the patent application, wherein the method further includes a step of forming the I / 0 redistribution wires by electroplating technology. Page 23 41 9 7 64 VI. Patent application scope 11. The manufacturing method of the wafer size structure as described in item 1 of the patent application scope, wherein the method further includes a method of forming aluminum, copper, aluminum alloy, and copper alloy. Or the I / 0 redistribution step of the copper alloy. -1 2. The manufacturing method of wafer size structure as described in item 1 of the patent application scope, wherein the method further comprises the following steps: depositing a layer composed of aluminum, copper, aluminum alloy, copper alloy or aluminum-copper alloy A metal layer; depositing a photoresist layer on top of the metal layer; defining the photoresist layer to form the I / 0 redistribution wire; and etching a portion of the I / 0 redistribution wire and redistributing the I / 0 The wire can electrically connect the bonding pad and the islands 15 1 3. The manufacturing method of the wafer size structure as described in item 1 of the scope of patent application, wherein the organic material layer can be made of a light-sensitive material, So that the organic material layer can be defined in subsequent processes to expose the wires formed on top of the islands. 14. The manufacturing method of wafer size structure as described in item 1 of the scope of patent application, wherein the method further comprises forming the UBM layer by one of techniques such as electroless plating, electroplating, or sputtering. 15. The method for fabricating a wafer size structure as described in item 1 of the scope of patent application, wherein the method further includes the following steps: forming the UBM layer on top of the wafer; forming a photoresist layer on the UB Layer M; and defining the UBM layer so that the UBM layer covers only the islands. Page 24 6. Scope of patent application 1 6. The manufacturing method of the wafer size structure as described in item i of the declared patent scope, wherein the method further includes a technique such as plating, printing or ball-implanting-implanting the solder Steps to the ball. 17. A wafer-sized structure that includes at least:-a pre-processed wafer with at least two pads on the top of the wafer; a protective layer formed on the top of the wafer and exposed Out of the pad ;: a number of separated islands' the islands are made of an elastic wooden jacket and formed on the top of the protective layer; ^ at least two I / O redistribution wires for Connect the objects /, pads' to make the islands and the way to form an electrical connection; Ping U to one, an organic material layer, covering &amp; The β-round table forms an electrical insulation from the β-lead wire region; and a layer is formed on top of the wires of the islands; 18 19 衩 several balls are formed on the top of the UBM layer a The wafer θ 谌 ° described in the scope of application patent No. 丨 7 wherein the protective layer is composed of a silicon oxide or a wonderful structure. & 4% of related substances as the scope of patent application! The wafer size structure described in item 7 wherein the islands are bombarded by a Young's modulus lower than i 0. Alas, the material is formed. &lt; drop material 419764 6. The scope of the patent application 20, the structure of the wafer size structure as described in item 17 of the scope of the patent application, wherein the thickness of the formed islands is less than or equal to 50 μm. 2 1. The structure of the wafer size structure as described in item 17 of the scope of the patent application, where the I / 0 redistribution wire can be made of aluminum, copper, aluminum alloy, copper-gold or Ming copper alloy. One formed. 2 2. The wafer size structure described in item 17 of the scope of the patent application, wherein the organic material layer may be formed of a light-sensitive material so that it can be defined and formed in a subsequent lithography process. Page 26