JP3856304B2 - Resistance element in CSP and semiconductor device having CSP - Google Patents

Resistance element in CSP and semiconductor device having CSP Download PDF

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Publication number
JP3856304B2
JP3856304B2 JP2002084243A JP2002084243A JP3856304B2 JP 3856304 B2 JP3856304 B2 JP 3856304B2 JP 2002084243 A JP2002084243 A JP 2002084243A JP 2002084243 A JP2002084243 A JP 2002084243A JP 3856304 B2 JP3856304 B2 JP 3856304B2
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barrier metal
resistance
metal layer
resistance element
semiconductor chip
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JP2003282788A (en
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正巳 高井
桂一 木村
聡 神埜
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Ricoh Co Ltd
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Ricoh Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、チップサイズパッケージ（ＣＳＰ；Chip Size Package）における抵抗素子およびＣＳＰを備えた半導体装置に係り、特にＣＳＰ内における再配線を利用することにより回路設計の柔軟性を高めることが可能な半導体装置に関する。本発明は、特にＣＳＰに実装されたボルテージレギュレータの位相補償回路やＣＳＰに実装されたＬｉ二次電池保護用ＩＣ、充電制御ＩＣ、電源ＩＣ、その他の各種のアナログ回路に適用可能である。
【０００２】
【従来の技術】
ＬＳＩチップのパッケージには多くの種類が知られているが、近年、パッケージのより一層の小型化を図るために、チップとほぼ同サイズのパッケージ、すなわちチップサイズパッケージ（ＣＳＰ；Chip Size Package）が開発されている。
【０００３】
図８は、従来の各種ＣＳＰの製造工程を示す図であり、同図（ａ）はリードフレームパッケージの製造工程、同図（ｂ）はＦＢＧＡ（Fine-pitch Ball Grid Array）の製造工程、同図（ｃ）はウェハーレベルＣＳＰの製造工程を示している。
【０００４】
図８（ａ）のリードフレームパッケージと図８（ｂ）のＦＢＧＡは、基本的に従来と同じ工程（チップに切断Ａ１、ダイボンディングＡ２、ワイヤボンディングＡ３、封止Ａ４、リード形成Ａ５／リード表面処理固片化Ａ６または電子処理固片化Ａ７）、すなわち前処理を終わったウェハーから個々のチップをダイシングにより切り出して、それをパッケージに組み立てるものであるが、本発明に係るウェハーレベルＣＳＰは、図８（ｃ）に示すように、前処理の終わったウェハーに直接パッケージ処理（Ｐｉ膜形成Ａ１１、再配線処理Ａ１２、ポスト形成Ａ１３、封止Ａ１４、研削端子処理Ａ１５）を行い、その後で個々のチップに切り分ける（ダイシングＡ１６）ものである。
【０００５】
従来のウエハーレベルＣＳＰでは、ＩＣのパッドおよびその上に設けられたアルミ電極と銅ポストおよびハンダバンプとは、できるだけ抵抗の小さい再配線により１対１の関係で接続されるのが前提とされていた。
【０００６】
本出願人は、先に再配線に所望の抵抗値を持たせた半導体装置を提案した（特願２００１−２７２０８９号、特願平２００１−２７２０９１号）。図９は、上記特願２００１−２７２０８９号にかかるボルテージレギュレータの回路例を示す図であり、図１０は、その再配線パターンの断面を示す図、図１１はその平面図の例である。
【０００７】
この例のボルテージレギュレータは、図９および図１０に示すように、ボルテージレギュレータを含むＩＣチップ５０のボンディングパッド５１と出力負荷５７および容量（コンデンサ）５５を接続する端子（ハンダバンプ）５２とをＣＳＰの再配線層（配線抵抗５４）を介して接続し、この再配線層の抵抗値を所望の値に設定するようにしたものである。すなわち、ボンディングバッドおよびパッシベーション膜および保護膜とその上部に形成されるバリアメタル層とそのバリアメタル層の上部に銅再配線を形成し、ボンディングバッドと銅ポストおよびハンダボールを銅再配線で接続している。
【０００８】
再配線層の抵抗値Ｒｏｕｔは、ウェハーレベルＣＳＰの製造工程において配線長，配線の幅，再配置層の材質のいずれか１つまたは複数を変えることにより使用するコンデンサに対して最適な値のＥＳＲを付加した状態にすることができる。
【０００９】
【発明が解決しようとする課題】
アナログ回路を含む半導体装置において、抵抗素子はアナログ特性を決定する上で重要な素子である。この抵抗素子はチップ内に作りこむか、あるいはＩＣ実装後外付け部品として別に部品を必要とした。チップ内に作りこむ場合、抵抗素材として拡散抵抗および配線抵抗が考えれるが、チップに内蔵する場合、接合容量や配線容量によるアナログ特性の劣化や長期バイアス印加による抵抗値の経年変化、パターン面積の制約による抵抗値の制約等があった。またユーザーの要求に応じたアナログ特性の調整を抵抗値で行う場合、抵抗がチップ内に有る場合、チップ内パターンの変更やトリミング工程の追加等が必要であった。
【００１０】
そこで、本発明は、実装後外付け部品として別に抵抗部品を必要とせず、また、抵抗をチップに内蔵しても、接合容量や配線容量によるアナログ特性の劣化や長期バイアス印加による抵抗値の経年変化、パターン面積の制約による抵抗値の制約等がすくなく、小型化が可能で、所望の抵抗値を形成できる技術を提供するものである。
【００１１】
次に請求項ごとの目的を述べる。
請求項１記載の発明の目的は、従来の外付け抵抗素子をウエハーレベルＣＳＰ内に取り込むことである。
【００１２】
請求項２記載の発明の目的は、従来の外付け抵抗素子をウエハーレベルＣＳＰ内に取り込み、コストを低減でき、実装面積も小さくでき携帯機器等の小型化を可能にすることである。
【００１３】
請求項３記載の発明の目的は、バリアメタル抵抗素子を内蔵するＩＣチップとは別の回路で、抵抗素子が必要な場合にウエハーレベルＣＳＰに内蔵した抵抗素子を使ってコストを低減し、実装面積を小さくし、携帯機器等の小型化を可能にすることである。
【００１４】
請求項４に記載の発明の目的は、新たなコストを必要とせずに１Ω〜１０ｋΩの抵抗を作ることができ、電流の制限や等価抵抗による位相補償用の抵抗として用いることを可能にすることである。
【００１５】
請求項５に記載の発明の目的は、新たなコストを必要とせずに各種アナログ回路のコスト低減や小型化を可能にすることである。
また、請求項６に記載の発明の目的は、従来の外付けの電流モニタ用抵抗素子をウエハーレベルＣＳＰ内に取り込むことである。
【００１６】
【課題を解決するための手段】
本発明は、上記課題を解決するために、ウエハレベルＣＳＰを製造する工程で、バリアメタルを用いて抵抗素子を作りこむようにしたものである。また、バリアメタルの素材を選択することにより、また前記バリアメタル層の材質，幅，長さ，あるいは厚さ少なくとも一つを変えることによって所望の値（例えば１Ωから１０ｋΩ）の抵抗素子を作りこむことができる。
【００１７】
さらに詳細に述べると、
請求項１記載の発明は、半導体チップのパッシベーション膜，その上部に形成された保護膜，その上部の抵抗経路となる部分に形成されたバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を設け、該再配線層が欠落した部分のバリアメタル層を抵抗部とした抵抗素子である。
【００１８】
また、請求項２記載の発明は、半導体チップのボンディングパッド，パッシベーション膜，保護膜，その上部の抵抗経路となる部分にバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、バリアメタル層を抵抗素子として機能させるようにした半導体装置である。
【００１９】
また、請求項３記載の発明は、半導体チップのパッシベーション膜，保護膜，その上部の抵抗経路となる部分にバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、バリアメタル層を抵抗素子として機能させるようにした半導体装置である。
【００２０】
また、請求項４記載の発明は、請求項２または３記載の半導体装置において、抵抗素子の抵抗値を、バリアメタル層の材質，幅，長さ，あるいは厚さ少なくとも一つを変えることによって所望の値にするようにしたものである。
【００２１】
さらに、請求項５記載の発明は、請求項２から４のいずれか１項に記載の半導体装置において、半導体チップを、ボルテージレギュレータ，Ｌｉ二次電池保護用ＩＣ，充電制御ＩＣ，電源ＩＣのいずれかにした半導体装置である。
また、請求項６記載の発明は、半導体チップ上に再配線層が形成されたＣＳＰにおける電流モニタ用抵抗素子であって、半導体チップの少なくとも２つボンディングパッド，パッシベーション膜，その上部に形成された保護膜，その上部に前記２つのボンディングパッド間の抵抗経路になる部分に形成されたバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、該再配線層が欠落した部分の前記バリアメタル層を抵抗部とし、前記２つのボンディングパッドの電圧をセンスすることにより前記抵抗部の電流をモニタ可能としたことを特徴とする電流モニタ用抵抗素子である。
【００２２】
本構成のようにバリアメタルで抵抗を構成した場合、ＩＣの基板バイアスからアイソレーションされており、接合容量が無くなる。また、配線容量はＩＣチップとバリアメタルとの間に厚い膜が形成されているため大きく軽減される。バリアメタルは拡散抵抗に比べ、バイアス印加による経年変化を受けにくいという特徴がある。
【００２３】
【発明の実施の形態】
＜請求項１、請求項２＞
（実施例１）
図１は、本発明の実施例１を説明するための半導体装置の断面図である。また図２はその平面図である。
【００２４】
本実施例１は、従来技術の銅再配線の一部を取り除き、バリアメタル層のみの配線抵抗を抵抗素子とするものである。本実施例１ではバリアメタル層のみを抵抗素子として抵抗を構成することで、後述する図７に示す素材に応じた抵抗値を持つ抵抗素子をウエハレベルＣＳＰの再配線層に作りこむことができる。
【００２５】
例えば、図１のようにＩＣチップ１０上のボンディングバッド１１から、ＩＣ以外の回路に接続されるハンダボール１７の間に１Ω〜１０ｋΩの抵抗を挿入したことになり、電流の制限や等価抵抗による位相補償用の抵抗として用いることができる。図１〜２において、１２は保護膜、１３はスルーホール、１４は銅再配線、１５はバリアメタル（バリアメタル層）、１６は銅ポスト、１８はパッシベーション、１９は封止樹脂、Ｒ１はバリアメタル抵抗部である。
【００２６】
＜請求項６＞
（実施例２）
図３は、本発明の実施例２を説明するための半導体装置の断面図である。また図４はその平面図である。
【００２７】
本実施例２は、図３のようにＩＣチップ２０上のボンディングパッド１（２１Ａ）とボンディングバッド２（２１Ｂ）との間にバリアメタル２５からなる抵抗部Ｒ２を作り、片側のボンディングバッド（２１Ｂ）の近傍に銅ポスト２６およびハンダボール２７を作る。ボンディングパッド１（２１Ａ）からボンディングパッド２（２１Ｂ）に流れる電流、あるいはその逆に流れる電流がバリアメタル２５の抵抗に流れることによりバリアメタル抵抗部Ｒ２の両端に電圧が発生し、その電圧を２つのボンディングパッドでセンスすることにより電流モニタ用抵抗として利用することができる。
【００２８】
また、ハンダボール２７を電源ラインあるいはグランドラインあるいは一定電圧ラインに接続することで、プルアップ抵抗あるいはプルダウン抵抗あるいはレベルシフト回路として作用させることができる。図３〜４において、２２は保護膜、２３はスルーホール、２４は銅再配線、２５はバリアメタル（バリアメタル層）、２８はパッシベーション、２９は封止樹脂、Ｒ２はバリアメタル抵抗部である。
【００２９】
＜請求項６＞
（実施例３）
図５は、本発明の実施例３を説明するための半導体装置の断面図である。
本実施例３は、図５のようにＩＣチップ３０上のボンディングパッド１（３１Ａ）とボンディングバッド２（３１Ｂ）との間にバリアメタル（バリアメタル層）３５からなるバリアメタル抵抗部Ｒ３を作り、両側のボンディングバッド近傍に銅ポスト３６およびハンダボール３７を作る。
【００３０】
ボンディングパッド１（３１Ａ）からボンディングパッド２（３１Ｂ）に流れる電流、あるいはその逆に流れる電流がバリアメタル３５の抵抗に流れることによりバリアメタル抵抗部Ｒ３の両端に電圧が発生し、その電圧を２つのボンディングパッドでセンスすることにより電流モニタ用抵抗として利用することができる。両側のボンディングバッド近傍に銅ポスト３６およびハンダボール３７を設けることで、ＩＣの外側の回路でも電圧をモニタすることが可能になる。
【００３１】
また、片方のボンディングパッドがＩＣ内部で発生した電圧の出力端子でそれに接続されるハンダボールによりＩＣの外側の回路に電圧を供給する場合、そのボンディングパッドともう一方のボンディングバッドの間にバリアメタル抵抗を挿入することでレベルシフト回路として作用させることができる。図５において、３２は保護膜、３３はスルーホール、３４は銅再配線、３８はパッシベーション、３９は封止樹脂である。
【００３２】
＜請求項３、請求項１＞
（実施例４）
図６は、実施例４を説明するための断面図である。
本実施例４では、ウエハーレベルＣＳＰ内にＩＣチップとは独立してバリアメタル４２による抵抗素子（バリアメタル抵抗部）Ｒ４を形成する。このような素子をハンダボール４５を置くことができる制約内であらかじめウエハーレベルＣＳＰ内にいくつか形成しておき、ＩＣ実装時に選択的に接続することで、外付け抵抗素子を必要とせずアナログ特性を調整することが可能となる。
【００３３】
また、実装面積としても、ＩＣ以外に素子を必要としないため、最小面積でコストも安価に最適なアナログ特性を作りこむことが可能となる。アナログ回路以外にもプルアップ抵抗、プルダウン抵抗、分圧抵抗等、従来外付け素子が必要だった部品をウエハーレベルＣＳＰ内に取り込むことができ最小面積でコストも安価に最適なシステムを実現することが可能となる。図６において、４１は保護膜、４３は銅再配線、４４は銅ポスト、４６は封止樹脂、４７はパッシベーションである。
【００３４】
＜請求項４＞
（実施例５）
図７は、バリアメタルに使用される抵抗の一覧を示す図である。これらの抵抗の長さ、幅、厚さの実施例を示す。これらの材質のサイズ、すなわち長さ、幅、厚さを調整することにより１Ω〜１０ｋΩの抵抗をウエハーレベルＣＳＰ内に作りこむことが可能となる。
【００３５】
＜請求項５＞
（実施例６）
上記各実施例における半導体チップとして、各種アナログ回路、例えばボルテージレギュレータの位相補償回路やＣＳＰに実装されたＬｉ二次電池保護用ＩＣ、充電制御ＩＣ、電源ＩＣを用い、従来の外付け抵抗素子をウエハーレベルＣＳＰ内に取り込み、最適な抵抗値を有する抵抗素子を形成することが可能となる。
【００３６】
【発明の効果】
以下、各請求項ごとの効果を説明する。
請求項１記載の発明は、ウエハーレベルＣＳＰの再配線層におけるバリアメタルを抵抗素子としたものであり、従来の外付け抵抗素子をウエハーレベルＣＳＰ内に取り込むことが可能となる。
【００３７】
請求項２記載の発明は、ウエハーレベルＣＳＰの再配線層におけるバリアメタルを抵抗素子としてアナログ回路の特性調整やデジタル回路のプルアップ抵抗等に用いることで、従来の外付け抵抗素子をウエハーレベルＣＳＰ内に取り込むことが可能となり、コストを低減でき、実装面積も小さくでき携帯機器等の小型化にも貢献できる。
【００３８】
請求項３記載の発明によれば、バリアメタル抵抗素子を内蔵するＩＣチップとは別の回路で、抵抗素子が必要な場合に今回の技術によるウエハーレベルＣＳＰに内蔵した抵抗素子を使うことでコストを低減でき、実装面積も小さくでき携帯機器等の小型化にも貢献できる。
【００３９】
請求項４に記載の発明によれば、バリアメタルの材質を選択することにより、また長さ、幅、厚さをウエハーレベルＣＳＰの工程で作りこむことができ、新たなコストを必要とせずに１Ω〜１０ｋΩの抵抗を作ることができ、電流の制限や等価抵抗による位相補償用の抵抗として用いることが可能となる。
【００４０】
請求項５に記載の発明によれば、半導体チップとして、ボルテージレギュレータの位相補償回路やＣＳＰに実装されたＬｉ二次電池保護用ＩＣ、充電制御ＩＣ、あるいは電源ＩＣを用いることにより、従来の外付け抵抗素子をウエハーレベルＣＳＰ内に取り込むことが可能となり、コストを低減でき、実装面積も小さくでき、これらの各種アナログ回路のコスト低減や小型化が可能になる。
また、請求項６記載の発明によれば、ウエハーレベルＣＳＰの再配線層におけるバリアメタルを抵抗部とし、該抵抗部の両端のボンディングパッドの電圧をセンスすることにより該抵抗部の電流をモニタすることにより、従来の外付けの電流モニタ用抵抗をウエハーレベルＣＳＰ内に取り込むことが可能となる。
【図面の簡単な説明】
【図１】本発明の実施例１を説明するための半導体装置の断面図である。
【図２】本発明の実施例１に係る半導体装置の平面図である。
【図３】本発明の実施例２を説明するための半導体装置の断面図である。
【図４】本発明の実施例２に係る半導体装置の平面図である。
【図５】本発明の実施例３を説明するための半導体装置の断面図である。
【図６】本発明の実施例４を説明するための半導体装置の断面図である。
【図７】バリアメタルに使用される抵抗の一覧を示す図である。
【図８】従来の各種ＣＳＰの製造工程を示す図である。
【図９】先に提案したボルテージレギュレータの回路例を示す図である。
【図１０】先に提案したボルテージレギュレータの再配線パターンの断面の例を示す図である。
【図１１】先に提案したボルテージレギュレータの再配線パターンの平面図である。
【符号の説明】
１０：ＩＣチップ、
１１：ボンディングバッド、
１２：保護膜、
１３：スルーホール、
１４：再配線（銅再配線）、
１５：バリアメタル（バリアメタル層）、
１６：銅ポスト、
１７：ハンダボール、
１８：パッシベーション、
１９：封止樹脂、
Ｒ１：バリアメタル抵抗部、
２０：ＩＣチップ、
２１Ａ：ボンディングパッド１、
２１Ｂ：ボンディングバッド２、
２２：保護膜、
２３：スルーホール、
２４：銅再配線、
２５：バリアメタル（バリアメタル層）、
２６：銅ポスト、
２７：ハンダボール、
２８：パッシベーション、
２９：封止樹脂、
Ｒ２：バリアメタル抵抗部、
３０：ＩＣチップ、
３１Ａ：ボンディングパッド１、
３１Ｂ：ボンディングバッド２、
３２：保護膜、
３３：スルーホール、
３４：銅再配線、
３５：バリアメタル（バリアメタル層）、
３６：銅ポスト、
３７：ハンダボール、
３８：パッシベーション、
３９：封止樹脂、
Ｒ３：バリアメタル抵抗部、
４１：保護膜、
４２：バリアメタル、
４３：銅再配線、
４４：銅ポスト、
４５：ハンダボール、
４６：封止樹脂、
４７：パッシベーション、
Ｒ４：抵抗素子（バリアメタル抵抗部）、
５０：ＩＣチップ、
５１：ボンディングパッド、
５２：端子（ハンダバンプ）、
５４：再配線層（配線抵抗）、
５５：容量（コンデンサ）、
５６：抵抗、
５７：出力負荷。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a resistance element and a CSP in a chip size package (CSP), and more particularly, a semiconductor capable of increasing the flexibility of circuit design by utilizing rewiring in the CSP. Relates to the device. The present invention is particularly applicable to a phase compensation circuit for a voltage regulator mounted on a CSP, a Li secondary battery protection IC mounted on a CSP, a charge control IC, a power supply IC, and other various analog circuits.
[0002]
[Prior art]
Many types of LSI chip packages are known, but in recent years, in order to further reduce the size of the package, a package of almost the same size as the chip, that is, a chip size package (CSP) is known. Has been developed.
[0003]
FIGS. 8A and 8B are diagrams showing manufacturing processes of various conventional CSPs. FIG. 8A shows a manufacturing process of a lead frame package, FIG. 8B shows a manufacturing process of an FBGA (Fine-pitch Ball Grid Array), and FIG. FIG. 3C shows a manufacturing process of the wafer level CSP.
[0004]
The lead frame package of FIG. 8 (a) and the FBGA of FIG. 8 (b) are basically the same processes as in the prior art (cutting chip A1, die bonding A2, wire bonding A3, sealing A4, lead formation A5 / lead surface). Process solidification A6 or electronic process solidification A7), that is, individual chips are cut out by dicing from a pre-processed wafer and assembled into a package. The wafer level CSP according to the present invention is As shown in FIG. 8C, package processing (Pi film formation A11, rewiring process A12, post formation A13, sealing A14, and grinding terminal process A15) is directly performed on the pre-processed wafer, and thereafter (Dicing A16).
[0005]
In the conventional wafer level CSP, it is assumed that the IC pad and the aluminum electrode provided on the IC pad and the copper post and the solder bump are connected in a one-to-one relationship by rewiring with as little resistance as possible. .
[0006]
The present applicant has previously proposed a semiconductor device in which a rewiring has a desired resistance value (Japanese Patent Application Nos. 2001-272089 and 2001-272091). 9 is a diagram showing a circuit example of a voltage regulator according to the above Japanese Patent Application No. 2001-272089, FIG. 10 is a diagram showing a cross section of the rewiring pattern, and FIG. 11 is an example of a plan view thereof.
[0007]
As shown in FIGS. 9 and 10, the voltage regulator of this example includes a bonding pad 51 of an IC chip 50 including the voltage regulator and a terminal (solder bump) 52 for connecting an output load 57 and a capacitor (capacitor) 55. They are connected via a rewiring layer (wiring resistor 54), and the resistance value of this rewiring layer is set to a desired value. That is, the bonding pad, passivation film, protective film, barrier metal layer formed on the upper part, and copper rewiring are formed on the upper part of the barrier metal layer, and the bonding pad, copper post, and solder ball are connected by copper rewiring. ing.
[0008]
The resistance value Rout of the redistribution layer is an ESR having an optimum value for the capacitor to be used by changing one or more of the wiring length, the wiring width, and the material of the relocation layer in the manufacturing process of the wafer level CSP. Can be added.
[0009]
[Problems to be solved by the invention]
In a semiconductor device including an analog circuit, a resistance element is an important element for determining analog characteristics. This resistance element was built in the chip, or another component was required as an external component after IC mounting. When built in the chip, diffused resistance and wiring resistance can be considered as the resistance material, but when built in the chip, deterioration of analog characteristics due to junction capacitance and wiring capacitance, aging of resistance value due to long-term bias application, pattern area There were restrictions on the resistance value due to restrictions. In addition, when the analog characteristic is adjusted by the resistance value according to the user's request, if the resistor is in the chip, it is necessary to change the pattern in the chip or add a trimming process.
[0010]
Therefore, the present invention does not require a separate resistance component as an external component after mounting, and even if the resistor is built in the chip, the deterioration of the analog characteristics due to the junction capacitance and wiring capacitance and the aging of the resistance value due to long-term bias application. It is an object of the present invention to provide a technique capable of forming a desired resistance value, which can be reduced in size without being restricted by a resistance value due to a change or a pattern area restriction.
[0011]
Next, the purpose of each claim will be described.
An object of the present invention is to incorporate a conventional external resistance element into a wafer level CSP.
[0012]
An object of the invention described in claim 2 is to incorporate a conventional external resistance element into a wafer level CSP, to reduce the cost, to reduce the mounting area, and to reduce the size of a portable device or the like.
[0013]
The object of the invention of claim 3 is a circuit different from an IC chip having a built-in barrier metal resistance element. When a resistance element is required, the resistance element built in the wafer level CSP is used to reduce the cost and to implement it. It is to reduce the area and enable downsizing of portable devices and the like.
[0014]
The object of the present invention is to make it possible to make a resistance of 1Ω to 10 kΩ without requiring a new cost, and to use it as a resistance for phase compensation by limiting current or equivalent resistance. It is.
[0015]
An object of the invention described in claim 5 is to enable cost reduction and miniaturization of various analog circuits without requiring new costs.
Further, an object of the present invention is to incorporate a conventional external current monitoring resistance element into the wafer level CSP.
[0016]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention is to create a resistance element using a barrier metal in a process of manufacturing a wafer level CSP. Further, by selecting the material of the barrier metal and changing the material, width, length, or thickness of the barrier metal layer, a resistance element having a desired value (for example, 1Ω to 10 kΩ) is formed. be able to.
[0017]
In more detail,
The invention according to claim 1 is a semiconductor chip passivation film, a protective film formed on the passivation film, a barrier metal layer formed on a portion serving as a resistance path above the semiconductor chip, and at least a part of the barrier metal layer on the barrier metal layer. This is a resistance element in which a missing rewiring layer is provided, and a portion of the barrier metal layer where the rewiring layer is missing is a resistance portion.
[0018]
According to a second aspect of the present invention, there is provided a rewiring in which a bonding metal, a passivation film, a protective film of a semiconductor chip, a barrier metal layer in a portion serving as a resistance path above the semiconductor chip, and at least a part of the barrier metal layer are missing. This is a semiconductor device having a layer and functioning a barrier metal layer as a resistance element.
[0019]
According to a third aspect of the present invention, the semiconductor chip has a passivation film, a protective film, a barrier metal layer in a portion serving as a resistance path above the semiconductor chip, and a rewiring layer at least partially missing on the barrier metal layer. In this semiconductor device, the barrier metal layer functions as a resistance element.
[0020]
According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, the resistance value of the resistive element is desired by changing at least one of the material, width, length, or thickness of the barrier metal layer. It is made to the value of.
[0021]
Further, the invention according to claim 5 is the semiconductor device according to any one of claims 2 to 4, wherein the semiconductor chip is any one of a voltage regulator, a Li secondary battery protection IC, a charge control IC, and a power supply IC. This is a crushed semiconductor device.
The invention according to claim 6 is a resistance element for current monitoring in a CSP in which a redistribution layer is formed on a semiconductor chip, and is formed on at least two bonding pads, a passivation film, and an upper part of the semiconductor chip. A protective film, a barrier metal layer formed in a portion serving as a resistance path between the two bonding pads on the protective film, and a rewiring layer at least partially missing on the barrier metal layer, the rewiring layer The resistance element for current monitoring is characterized in that the portion of the barrier metal layer where the gap is missing is used as a resistance section, and the current of the resistance section can be monitored by sensing the voltage of the two bonding pads.
[0022]
When the resistor is configured with a barrier metal as in this configuration, it is isolated from the substrate bias of the IC, and the junction capacitance is eliminated. Also, the wiring capacitance is greatly reduced because a thick film is formed between the IC chip and the barrier metal. A barrier metal is characterized by being less susceptible to aging due to bias application than a diffusion resistor.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
<Claim 1, Claim 2>
Example 1
FIG. 1 is a cross-sectional view of a semiconductor device for explaining a first embodiment of the present invention. FIG. 2 is a plan view thereof.
[0024]
In the first embodiment, a part of the conventional copper rewiring is removed, and the wiring resistance of only the barrier metal layer is used as a resistance element. In the first embodiment, by configuring the resistance using only the barrier metal layer as a resistance element, a resistance element having a resistance value corresponding to the material shown in FIG. 7 to be described later can be formed in the rewiring layer of the wafer level CSP. .
[0025]
For example, a resistor of 1Ω to 10 kΩ is inserted between a bonding pad 11 on the IC chip 10 and a solder ball 17 connected to a circuit other than the IC as shown in FIG. It can be used as a resistance for phase compensation. 1-2, 12 is a protective film, 13 is a through hole, 14 is a copper rewiring, 15 is a barrier metal (barrier metal layer), 16 is a copper post, 18 is passivation, 19 is a sealing resin, and R1 is a barrier. It is a metal resistor.
[0026]
<Claim 6>
(Example 2)
FIG. 3 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention. FIG. 4 is a plan view thereof.
[0027]
In the second embodiment, as shown in FIG. 3, a resistor R2 made of a barrier metal 25 is formed between the bonding pad 1 (21A) and the bonding pad 2 (21B) on the IC chip 20, and the bonding pad (21B) on one side is formed. The copper post 26 and the solder ball 27 are made in the vicinity of When a current flowing from the bonding pad 1 (21A) to the bonding pad 2 (21B) or vice versa flows through the resistance of the barrier metal 25, a voltage is generated at both ends of the barrier metal resistor R2, and the voltage is reduced to 2 By sensing with one bonding pad, it can be used as a resistance for current monitoring.
[0028]
Further, by connecting the solder ball 27 to a power supply line, a ground line, or a constant voltage line, it is possible to act as a pull-up resistor, a pull-down resistor, or a level shift circuit. 3 to 4, 22 is a protective film, 23 is a through hole, 24 is a copper rewiring, 25 is a barrier metal (barrier metal layer), 28 is passivation, 29 is a sealing resin, and R2 is a barrier metal resistor. .
[0029]
<Claim 6>
Example 3
FIG. 5 is a cross-sectional view of a semiconductor device for explaining a third embodiment of the present invention.
In the third embodiment, as shown in FIG. 5, a barrier metal resistor R3 made of a barrier metal (barrier metal layer) 35 is formed between the bonding pad 1 (31A) and the bonding pad 2 (31B) on the IC chip 30. The copper posts 36 and the solder balls 37 are formed in the vicinity of the bonding pads on both sides.
[0030]
A current that flows from the bonding pad 1 (31A) to the bonding pad 2 (31B) or vice versa flows through the resistance of the barrier metal 35, thereby generating a voltage at both ends of the barrier metal resistor R3. By sensing with one bonding pad, it can be used as a resistance for current monitoring. By providing the copper post 36 and the solder ball 37 in the vicinity of the bonding pads on both sides, the voltage can be monitored even in a circuit outside the IC.
[0031]
In addition, when one bonding pad is an output terminal of a voltage generated inside the IC and a voltage is supplied to a circuit outside the IC by a solder ball connected thereto, a barrier metal is provided between the bonding pad and the other bonding pad. Inserting a resistor can act as a level shift circuit. In FIG. 5, 32 is a protective film, 33 is a through hole, 34 is a copper rewiring, 38 is a passivation, and 39 is a sealing resin.
[0032]
<Claim 3 and Claim 1>
Example 4
FIG. 6 is a cross-sectional view for explaining the fourth embodiment.
In the fourth embodiment, a resistance element (barrier metal resistance portion) R4 made of a barrier metal 42 is formed in the wafer level CSP independently of the IC chip. Some of these elements are formed in the wafer level CSP in advance within the constraints that the solder balls 45 can be placed, and are selectively connected at the time of IC mounting, so that no external resistance element is required and analog characteristics are obtained. Can be adjusted.
[0033]
In addition, since an element other than an IC is not required for the mounting area, it is possible to create optimum analog characteristics with a minimum area and a low cost. In addition to analog circuits, pull-up resistors, pull-down resistors, voltage dividing resistors, and other components that previously required external elements can be incorporated into the wafer level CSP, and an optimum system can be realized with a minimum area and low cost. Is possible. In FIG. 6, 41 is a protective film, 43 is a copper rewiring, 44 is a copper post, 46 is a sealing resin, and 47 is a passivation.
[0034]
<Claim 4>
(Example 5)
FIG. 7 is a diagram showing a list of resistors used for the barrier metal. Examples of the length, width, and thickness of these resistors are shown. By adjusting the size of these materials, that is, the length, width, and thickness, a resistance of 1Ω to 10 kΩ can be formed in the wafer level CSP.
[0035]
<Claim 5>
(Example 6)
As the semiconductor chip in each of the above embodiments, various external circuits such as a phase compensation circuit of a voltage regulator, a Li secondary battery protection IC mounted on a CSP, a charge control IC, and a power supply IC are used. It is possible to form a resistance element having an optimum resistance value taken into the wafer level CSP.
[0036]
【The invention's effect】
Hereinafter, the effect of each claim will be described.
According to the first aspect of the present invention, the barrier metal in the rewiring layer of the wafer level CSP is used as a resistance element, and a conventional external resistance element can be taken into the wafer level CSP.
[0037]
The invention according to claim 2 uses the barrier metal in the redistribution layer of the wafer level CSP as a resistance element for the characteristic adjustment of the analog circuit, the pull-up resistance of the digital circuit, etc., so that the conventional external resistance element is used as the wafer level CSP. It is possible to reduce the cost, reduce the mounting area, and contribute to downsizing of portable devices.
[0038]
According to the third aspect of the present invention, when a resistance element is required in a circuit different from an IC chip having a built-in barrier metal resistance element, the use of the resistance element built into the wafer level CSP according to the present technology reduces the cost. Can be reduced, and the mounting area can be reduced, which contributes to miniaturization of portable devices and the like.
[0039]
According to the invention described in claim 4, by selecting the material of the barrier metal, the length, width, and thickness can be created in the process of the wafer level CSP without requiring a new cost. A resistance of 1Ω to 10 kΩ can be made, and can be used as a resistance for phase compensation by limiting current or equivalent resistance.
[0040]
According to the invention described in claim 5, by using a phase compensation circuit of a voltage regulator or a Li secondary battery protection IC, a charge control IC, or a power supply IC mounted on a CSP as a semiconductor chip, The attached resistance element can be taken into the wafer level CSP, the cost can be reduced, the mounting area can be reduced, and the cost and size of these various analog circuits can be reduced.
According to the sixth aspect of the present invention, the barrier metal in the rewiring layer of the wafer level CSP is used as the resistance portion, and the current of the resistance portion is monitored by sensing the voltage of the bonding pads at both ends of the resistance portion. This makes it possible to incorporate a conventional external current monitoring resistor into the wafer level CSP.
[Brief description of the drawings]
1 is a cross-sectional view of a semiconductor device for explaining a first embodiment of the present invention;
FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention;
FIG. 4 is a plan view of a semiconductor device according to Embodiment 2 of the present invention.
FIG. 5 is a cross-sectional view of a semiconductor device for explaining Example 3 of the invention.
FIG. 6 is a cross-sectional view of a semiconductor device for explaining a fourth embodiment of the present invention.
FIG. 7 is a diagram showing a list of resistors used for barrier metal.
FIG. 8 is a diagram showing manufacturing steps of various conventional CSPs.
FIG. 9 is a diagram showing a circuit example of the previously proposed voltage regulator.
FIG. 10 is a diagram showing an example of a cross section of a rewiring pattern of the previously proposed voltage regulator.
FIG. 11 is a plan view of a rewiring pattern of the previously proposed voltage regulator.
[Explanation of symbols]
10: IC chip,
11: Bonding pad
12: protective film,
13: Through hole,
14: Rewiring (copper rewiring),
15: Barrier metal (barrier metal layer),
16: Copper post
17: Solder ball,
18: Passivation,
19: sealing resin,
R1: Barrier metal resistor,
20: IC chip,
21A: Bonding pad 1,
21B: Bonding pad 2
22: Protective film,
23: Through hole,
24: Copper rewiring,
25: Barrier metal (barrier metal layer),
26: Copper post,
27: Solder ball,
28: Passivation,
29: sealing resin,
R2: Barrier metal resistor,
30: IC chip,
31A: Bonding pad 1
31B: Bonding pad 2,
32: protective film,
33: Through hole,
34: Copper rewiring
35: Barrier metal (barrier metal layer),
36: Copper post,
37: Solder ball,
38: Passivation,
39: sealing resin,
R3: Barrier metal resistor,
41: protective film,
42: Barrier metal,
43: Copper rewiring
44: Copper post,
45: Solder ball,
46: sealing resin,
47: Passivation,
R4: resistance element (barrier metal resistor),
50: IC chip,
51: Bonding pad,
52: Terminal (solder bump),
54: Rewiring layer (wiring resistance),
55: Capacity (capacitor),
56: resistance,
57: Output load.

Claims (6)

半導体チップ上に再配線層が形成されたＣＳＰにおける抵抗素子であって、
前記半導体チップのパッシベーション膜，その上部に形成された保護膜，その上部の抵抗経路になる部分に形成されたバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、該再配線層が欠落した部分の前記バリアメタル層を抵抗部としたことを特徴とする抵抗素子。A resistance element in a CSP in which a redistribution layer is formed on a semiconductor chip,
The semiconductor chip has a passivation film, a protective film formed on the passivation film, a barrier metal layer formed on a portion serving as a resistance path above the semiconductor chip, and a rewiring layer at least partially missing on the barrier metal layer. A resistance element, wherein the barrier metal layer in a portion where the rewiring layer is missing is used as a resistance portion. 半導体チップ上に再配線層が形成されたＣＳＰを備えた半導体装置であって、
前記半導体チップのボンディングパッド，パッシベーション膜，保護膜，その上部の抵抗経路になる部分に形成されたバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、前記バリアメタル層を抵抗素子として機能させることを特徴とする半導体装置。A semiconductor device including a CSP in which a redistribution layer is formed on a semiconductor chip,
A bonding pad of the semiconductor chip, a passivation film, a protective film, a barrier metal layer formed in a portion serving as a resistance path above the semiconductor chip, and a rewiring layer at least partially missing on the barrier metal layer, A semiconductor device, wherein a barrier metal layer functions as a resistance element. 半導体チップ上に再配線層が形成されたＣＳＰを備えた半導体装置であって、
前記半導体チップのパッシベーション膜，保護膜，その上部の抵抗経路になる部分に形成されたバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、前記バリアメタル層を抵抗素子として機能させることを特徴とする半導体装置。A semiconductor device including a CSP in which a redistribution layer is formed on a semiconductor chip,
A barrier metal layer formed on a passivation film and a protective film of the semiconductor chip ; a barrier metal layer formed on a portion serving as a resistance path above the semiconductor chip; and a rewiring layer at least partially missing on the barrier metal layer; Function as a resistance element. 請求項２または３記載の半導体装置において、前記抵抗素子の抵抗値は、前記バリアメタル層の材質，幅，長さ，あるいは厚さ少なくとも一つを変えることによって所望の値にすることを特徴とする半導体装置。  4. The semiconductor device according to claim 2, wherein the resistance value of the resistance element is set to a desired value by changing at least one of the material, width, length, or thickness of the barrier metal layer. Semiconductor device. 請求項２から４のいずれか１項に記載の半導体装置において、
前記半導体チップは、ボルテージレギュレータ，Ｌｉ二次電池保護用ＩＣ，充電制御ＩＣ，電源ＩＣのいずれかであることを特徴とする半導体装置。The semiconductor device according to any one of claims 2 to 4,
The semiconductor device is any one of a voltage regulator, a Li secondary battery protection IC, a charge control IC, and a power supply IC. 半導体チップ上に再配線層が形成されたＣＳＰにおける電流モニタ用抵抗素子であって、
前記半導体チップの少なくとも２つボンディングパッド，パッシベーション膜，その上部に形成された保護膜，その上部に前記２つのボンディングパッド間の抵抗経路になる部分に形成されたバリアメタル層，該バリアメタル層の上部に少なくとも一部が欠落した再配線層を有し、該再配線層が欠落した部分の前記バリアメタル層を抵抗部とし、前記２つのボンディングパッドの電圧をセンスすることにより前記抵抗部に流れる電流をモニタ可能としたことを特徴とする電流モニタ用抵抗素子。A resistance element for current monitoring in a CSP in which a redistribution layer is formed on a semiconductor chip,
At least two bonding pads of the semiconductor chip, a passivation film, a protective film formed thereon, a barrier metal layer formed in a portion serving as a resistance path between the two bonding pads, and a barrier metal layer It has a rewiring layer that is at least partially missing on the upper part, the barrier metal layer where the rewiring layer is missing is used as a resistance part, and flows to the resistance part by sensing the voltage of the two bonding pads A resistance element for current monitoring, characterized in that current can be monitored.
JP2002084243A 2002-03-25 2002-03-25 Resistance element in CSP and semiconductor device having CSP Expired - Fee Related JP3856304B2 (en)

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