? 419765 五、發明說明（1) 本發明是有關於一種積體電路晶片（integratecl circui ts ; I Cs)的封裝（package )技術，特別是有關於一 種用於覆晶（flip-chip)之晶片焊接凸塊（s〇ider bumps) 的製造方法。 所谓覆晶封裝是將裸晶（bare die)以表面朝下的方式 與基板（substrate)進行接合的技術。以下利用第ία圖〜第 1 B圖所示的製造流程剖面圖當作例子，來說明覆晶技術。 首先’請參照第1A圖’上半部所示的符號丨〇為積體電 路晶片’符號1 2為金屬導線，符號1 4為保護層，1 6為凸塊 底部金屬層（under bump metal ;UBM)，符號20則是銲接 凸塊，其係由錫-鉛或是錫—金等合金構成。下半部所示的 符號30為基板，符號32為導體層，而符號34表示銲接層 (solder layer)，可以採用與銲接凸塊相同的材料。 然後’請參照第1 B圖，利用熱處理將第丨A圖所示的銲 接凸塊20與銲接層34進行接合’以構成接合部b。如上所 述將晶片的表面朝下與基板進行接合的技術亦即所謂的覆 晶。以下利用第2圖，以說明傳統的積體電路晶片之銲接 凸塊。 第2圊所示的符號50表示晶片，而符號52為金屬導 線，54為絕緣保護層，5 6為例如由鈦/氮化鈦/銅或金等構 成的凸塊底部金屬層，而符號60表示由錫或錫合金構成的 銲接凸塊。傳統形成銲接凸塊6〇的方法包括：（丨）利用光 阻圖案覆蓋欲形成銲接凸塊6〇以外的區域再以物理氣相 沈積法形成錫或錫合金構成的銲接凸塊，然後，剝除上述419765 V. Description of the invention (1) The present invention relates to a package technology of integrated circuit chips (integratecl circui ts; I Cs), and particularly to a chip for flip-chip Manufacturing method of solder bumps. The flip-chip package is a technology in which a bare die is bonded to a substrate with its surface facing downward. The following describes the flip-chip technology by using the cross-sectional views of the manufacturing process shown in FIG. 1 to FIG. 1B as examples. Firstly, please refer to the symbol shown in the upper part of 'Please refer to FIG. 1A'. It is an integrated circuit chip. Symbol 12 is a metal wire, symbol 14 is a protective layer, and 16 is an under bump metal layer (under bump metal; UBM), symbol 20 is a solder bump, which is made of tin-lead or tin-gold alloy. The symbol 30 shown in the lower part is a substrate, the symbol 32 is a conductor layer, and the symbol 34 is a solder layer. The same material as the solder bump can be used. Then, referring to FIG. 1B, heat-welding the solder bump 20 shown in FIG. 丨 A with the solder layer 34 to form a joint portion b. As described above, the technique of bonding the surface of the wafer to the substrate is called a flip chip. In the following, FIG. 2 is used to explain the solder bumps of the conventional integrated circuit wafer. The symbol 50 shown in the second figure represents the wafer, the symbol 52 is a metal wire, 54 is an insulating protective layer, 56 is a metal layer at the bottom of the bump composed of titanium / titanium nitride / copper or gold, and the symbol 60 Represents solder bumps made of tin or tin alloy. The traditional method of forming the solder bump 60 includes: (丨) covering a region other than the solder bump 60 with a photoresist pattern, and then forming a solder bump composed of tin or a tin alloy by a physical vapor deposition method, and then peeling Except for the above
第4頁 41 9765 五、發明說明（2) ~ 以光阻圖案配 光陴圖案。（2)全面性形成錫或錫合金層’ 合蝕刻步驟以定義出銲接凸塊。 需要形成密度Page 4 41 9765 V. Description of the invention (2) ~ Photoresist pattern with photoresist pattern. (2) Comprehensive formation of a tin or tin alloy layer 'and an etching step to define solder bumps. Need to form density
然而，隨著積體電路之積集度的増加 極高的光阻圖案，此在實務上具有困難Q 有鑑於此，本發明的目的在於提供一種用於覆晶 (flip-chip)之晶片焊接凸塊（bumps)的製造方法藉由使 用電化學沈積法以選擇性地形成銅或金材料構成的焊接凸 塊。由於不需形成密度極高的光阻圖案，能夠避免傳統 術所衍生的問題。並且可提昇產品之性能與產能。 根據上述目的，本發明提供一種用於覆晶 (f 1 ip~chip)之晶片焊接凸塊（bumps)的製造方法，適用於 形成有金屬導線之積體電路晶片，上述方法包括下列步、 驟·（ a)在上述晶片表面形成一絕緣保護層，其具有一露 出上述金屬導線之開口部；（b)在上述絕緣保護層表面依 序形成一凸塊底部金屬層、以及一種晶層；（幻去除上述 開口部以外的種晶層，直到露出上述凸塊底部金屬層表面 為止，而在上述開口部留下一種晶墊；（d)利用電化學沈 積法（E CD )以沿著上述種晶墊成長一焊接凸塊；以及（e )去 除路出的凸塊底部金屬層。 上述晶片焊接凸塊的製造方法’其中上述金屬導線係 由銘銅合金或銅金屬構成。上述絕緣層保護層係氧化層。 而上述凸塊底部金屬層係利用化學氣相沈積法形成的氮化 欽或氮化钽層。上述種晶層係銅（Cu)或金（Au)種晶層，此 時上述焊接凸塊係分別由銅金屬或金構成However, as the integration degree of integrated circuits increases with extremely high photoresist patterns, this is difficult in practice. In view of this, the object of the present invention is to provide a wafer bonding for flip-chip Bumps are manufactured by using an electrochemical deposition method to selectively form solder bumps made of copper or gold materials. Since it is not necessary to form a photoresist pattern with extremely high density, the problems caused by the conventional technique can be avoided. And can improve product performance and productivity. According to the above object, the present invention provides a method for manufacturing wafer solder bumps for flip-chip (f 1 ip ~ chip), which is suitable for forming integrated circuit wafers with metal wires. The above method includes the following steps, steps (A) forming an insulating protective layer on the surface of the wafer, which has an opening exposing the metal wire; (b) sequentially forming a metal layer at the bottom of the bump and a crystal layer on the surface of the insulating protective layer; The seed layer other than the opening is removed until the surface of the metal layer at the bottom of the bump is exposed, and a crystal pad is left in the opening; (d) Electrochemical deposition (E CD) is used to follow the seed. The crystal pad grows a solder bump; and (e) removes the metal layer at the bottom of the bump. The manufacturing method of the wafer solder bump described above, wherein the metal wire is made of copper alloy or copper metal. The insulating layer protective layer It is an oxide layer. The metal layer at the bottom of the bump is a cyanide or tantalum nitride layer formed by chemical vapor deposition. The seed layer is a copper (Cu) or gold (Au) seed layer. Solder bumps are respectively formed of gold or copper metal
第5頁 五 '發明說明（3) 用化^ Ϊ艸上述晶片焊接凸塊的製造方法之步驟（C)係利 (e)係干利用V研磨法去除上述開口部以外的種晶I。而步驟 金屬居廿刻法或㈣刻法去除上述露出之凸塊底部 熱流處理的步驟 4纟包括—進行焊接凸塊再 懂，發明之上述目的、特徵、和優點能更明顯易 明如；文特舉一較佳實施例’並配合所附圖式，作詳細說 圖式之簡單說明： 第1 Α〜第1 Β圖為覆晶技術之剖面示意圖。 第2圖為傳統之晶片焊接凸塊的剖面示意圖。 第3 A〜3 D圖為择據本發明較佳實施例曰 的製程剖面示意圖。 日日 焊接凸塊 符號之說明 100〜積體電路晶片。 102~金屬導線。 104〜絕緣保護層。 1 0 5〜開口部。 106、106a〜凸塊底部金屬層。 I 0 8 ~種晶層。 108a〜種晶墊。 II 0 ~焊接凸塊。 實施例 以下利用第3A~第3D圖所示之製程剖面示意圖，、 以說(5) Description of the invention (3) The method (C) of the manufacturing method of the wafer solder bump manufacturing method described above (e) The seed crystals other than the openings are removed by a V polishing method. The step 4 of the method of metal engraving or engraving to remove the heat flow treatment of the exposed bottom of the bumps includes-performing soldering bumps to understand, the above-mentioned objects, features, and advantages of the invention can be more clearly understood. A preferred embodiment is given in conjunction with the accompanying drawings to briefly explain the drawings in detail: Figures 1A to 1B are schematic cross-sectional views of flip-chip technology. Figure 2 is a schematic cross-sectional view of a conventional wafer bonding bump. Figures 3A to 3D are schematic cross-sectional views of the process according to the preferred embodiment of the present invention. Every day Solder bump description of symbols 100 ~ Integrated circuit chip. 102 ~ Metal wire. 104 ~ Insulation protective layer. 1 0 5 to opening. 106, 106a ~ metal layer at the bottom of the bump. I 0 8 ~ seed layer. 108a ~ seed pad. II 0 ~ solder bump. Example The following is a schematic cross-sectional view of the process shown in Figs. 3A to 3D.
第6頁 五、發明說明（4) 明本發明晶片焊接凸塊之製造技術。 首先’請參照第3 Α圖，該圖顯示形成有例如銅或是鋁 銅合金構成之金屬導線102的積體電路晶片1〇〇，符號1〇4 表示氧化層等構成的絕緣保護層（passivation layer)， 符號105表示露出金屬導線i〇2的開口部。符號表示厚 度介於500〜2 0 0 0 A的凸塊底部金屬層（UBM)，其例如為利用 化學氣相沈積法（chemical vapor deposition ; CVD)形成 的氮化鈇層或氮化钽層。符號108表示厚度約為2〇〇〇A的種 晶層（seed layer)，其例如為利用物理氣相沈積法（pvd) 賤鍍而成的銅（Cu)或金（Au)種晶層π 接著，請參照第3Β圖，利用例如化學機械研磨法 (chemical mechanical polishing ;CMP)，並且配合適當 的研漿與研磨速度、時間等條件，以去除上述開口部丨〇 5 以外的種晶層1 0 8，直到露出上述凸塊底部金屬層丨0 6的表 面為止，而在上述開口部105留下一種晶墊i〇8a，其用途 在於建立後續電化學電鍍沈積時的金屬基本結構。 然後，請參照第3C圖，利用電化學沈積法 (electro-chemical deposition ;ECD)以沿著上述種晶墊 108a成長一焊接凸塊11〇 ’當種晶層1〇8採用銅時將形成銅 材料凸塊，而當種晶層108採用金時則將形成金材料凸 塊。此時’由於電化學沈積法具有選擇性成長的特性，因 此，僅在種晶墊l〇8a的區域沈積金屬。 其次’請參照第2 D圖，利用乾餘刻（d r y e t c h i n g)或 溼蝕刻法（wet etching)以去除露出的凸塊底部金屬層Page 6 V. Description of the invention (4) Describe the manufacturing technology of the wafer solder bump of the present invention. First, please refer to FIG. 3A, which shows an integrated circuit wafer 100 formed with a metal wire 102 made of, for example, copper or an aluminum-copper alloy, and a reference numeral 104 indicates an insulation protection layer composed of an oxide layer or the like. layer), and the reference numeral 105 denotes an opening where the metal wire i02 is exposed. The symbol indicates a bump bottom metal layer (UBM) having a thickness between 500 and 2000 A, which is, for example, a hafnium nitride layer or a tantalum nitride layer formed by a chemical vapor deposition (CVD) method. Reference numeral 108 denotes a seed layer having a thickness of about 2000 A, which is, for example, a copper (Cu) or gold (Au) seed layer π that is plated by physical vapor deposition (PVD). Next, referring to FIG. 3B, using a chemical mechanical polishing (CMP) method, and appropriate conditions such as slurry and polishing speed, time, etc., to remove the seed layer 1 other than the above openings 0, until the surface of the metal layer at the bottom of the bump is exposed, and a crystal pad i08a is left in the opening 105, and its purpose is to establish the basic metal structure during subsequent electrochemical plating. Then, referring to FIG. 3C, an electro-chemical deposition (ECD) method is used to grow a solder bump 110 along the seed pad 108a. When the seed layer 108 uses copper, copper will be formed. Material bumps, and gold seed bumps are formed when the seed layer 108 is gold. At this time ', since the electrochemical deposition method has a characteristic of selective growth, the metal is deposited only in the region of the seed pad 108a. Secondly, please refer to FIG. 2D, and use the dry etching (d r y e t c h i n g) or wet etching to remove the exposed metal layer at the bottom of the bump.
第7頁Page 7
五、發明說明¢5) (UBM)106 。 之後’可視需要施以再熱流（re-flow)處理，使得焊 接凸塊11 0的外形與結構更符合需求。 發明特徵與效果 本發明利用電化學沈積法以選擇性地形成銅或金材料 構成的焊接凸塊，其能夠取代傳統的錫或錫合金材料構成 的焊接凸塊。藉此可解決習知光阻圖案不易形成的問題， 並且幵產品之性能與產能。 雖然本發明已以較佳實施例揭露如上，然立並葬用以 限定J發明何熟習此項技藝者，“脫離：精 神和,，當：作更動與满飾， 當視後附之申請專利範圍所界定者為準。3 73之保邊犯5. Description of the invention ¢ 5) (UBM) 106. After that, a re-flow treatment may be applied as needed, so that the shape and structure of the solder bump 110 are more in accordance with requirements. Features and Effects of the Invention The present invention uses an electrochemical deposition method to selectively form solder bumps made of copper or gold materials, which can replace conventional solder bumps made of tin or tin alloy materials. This can solve the problem that the conventional photoresist pattern is not easy to form, and the performance and productivity of the product. Although the present invention has been disclosed as above in a preferred embodiment, it is set up and buried to limit J's invention. Those who are familiar with this art, "Divergence: Spiritual harmony, When: Make changes and full decoration, When you see the attached patent The scope of the definition shall prevail.