CN106252318B - Plant ball process and structure - Google Patents
Plant ball process and structure Download PDFInfo
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- CN106252318B CN106252318B CN201610866729.6A CN201610866729A CN106252318B CN 106252318 B CN106252318 B CN 106252318B CN 201610866729 A CN201610866729 A CN 201610866729A CN 106252318 B CN106252318 B CN 106252318B
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- wafer
- insulating layer
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- salient point
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a plant ball process and structures, it is characterized in that: including upper wafer and lower wafer, the lower surface of upper wafer deposits upper wafer insulating layer, lower wafer upper surface depositing insulating layer, upper wafer lower surface is equipped with salient point, lower wafer upper surface has the embedded soldered ball for being embedded in lower wafer upper surface, and the salient point of upper wafer lower surface is embedded in the embedded soldered ball of lower wafer, and the insulating layer of upper wafer insulating layer and lower wafer upper surface realizes bonding.The embedded soldered ball is set in the embedment hole of lower wafer upper surface, and the inner wall in embedment hole sets gradually insulating layer, seed layer and pad layer, and soldered ball is arranged on the pad layer in embedment hole.Shape, the size in the embedment hole are consistent with the shape of salient point, size.The present invention can guarantee the effective interconnection and the reliability of two panels wafer bonding of wafer convex point.
Description
Technical field
The present invention relates to a plant ball process and structures, belong to technical field of semiconductors.
Background technique
With the development of semiconductor technology, the characteristic size of integrated circuit constantly reduces, and device interconnection density is continuously improved.
Then, wafer-level packaging (Wafer Level Package, WLP), which gradually replaces wire bond package, becomes a kind of more common
Packaging method.Wafer-level packaging (Wafer Level Packaging, WLP) technology is to be packaged test to full wafer wafer
It cuts to obtain the technology of single finished product chip again afterwards, the chip size after encapsulation is completely the same with bare die, has complied with market to micro-
Electronic product is increasingly light, small, short, thinning and low priceization requirement.
Wafer-level packaging either MEMS or CIS BSI technique will use bonding, and bonding technology is generally divided into anode
The techniques such as bonding, metal melting bonding, oxidation Si direct bonding.Wafer is carried out after bonding thinned, then carries out conventional half
Semiconductor process, including photoetching, etching, film deposition etc..
But in bonding technology, if crystal column surface has salient point, with metal bonding technique will result in two wafers it
Between there are gaps；And if salient point using subsequent annealing because will complete to weld using silica bonding technology, then such as
Fruit technology controlling and process is inaccurate, and the salient point that will lead to partial region cannot effectively complete conducting.
Summary of the invention
The purpose of this section is to summarize some aspects of the embodiment of the present invention and briefly introduce some preferable implementations
Example.It may do a little simplified or be omitted to avoid our department is made in this section and the description of the application and the title of the invention
Point, the purpose of abstract of description and denomination of invention it is fuzzy, and this simplification or omit and cannot be used for limiting the scope of the invention.
In view of there are gap and wafers between wafer present in above-mentioned and/or existing semiconductor packages bonding technology
The problem of surface salient point cannot be connected, proposes the present invention.
The purpose of the present invention is overcoming the deficiencies in the prior art, a plant ball process and structure, Neng Goubao are provided
Demonstrate,prove the effective interconnection and the reliability of two panels wafer bonding of wafer convex point.
According to technical solution provided by the invention, ball placement structure, it is characterized in that: include upper wafer and lower wafer, on
The lower surface of wafer deposits upper wafer insulating layer, and lower wafer upper surface depositing insulating layer, upper wafer lower surface is equipped with salient point, lower crystalline substance
Circle upper surface has the embedded soldered ball for being embedded in lower wafer upper surface, and the salient point of upper wafer lower surface is embedded in the embedded of lower wafer
In soldered ball, the insulating layer of upper wafer insulating layer and lower wafer upper surface realizes bonding.
Further, the embedded soldered ball is set in the embedment hole of lower wafer upper surface, embedment hole inner wall according to
Soldered ball is arranged on the pad layer in embedment hole in secondary setting insulating layer, seed layer and pad layer.
Further, shape, the size in the embedment hole are consistent with the shape of salient point, size.
Ball placement technique, characterized in that the following steps are included:
(1) upper wafer insulating layer is deposited in the lower surface of upper wafer, makes salient point in upper wafer surface of insulating layer；
(2) position production shape, size and the consistent embedment hole of salient point in the upper surface of lower wafer relative to salient point；
(3) in the inner wall depositing insulating layer of the upper surface of lower wafer and embedment hole；
(4) in the surface deposited seed layer of insulating layer, in the electroplating surface pad layer of seed layer；
(5) the pad layer surface in embedment hole sprays scaling powder, is implanted into soldered ball being embedded in hole using ball technique is planted；Or
It is being embedded to direct applying solder paste in hole；
(6) wafer crosses Reflow Soldering under, makes soldered ball or solder(ing) paste in conjunction with the pad layer being embedded in hole, then cleaning removal
Film of flux residue；
(7) seed layer and pad layer for removing lower wafer upper surface, only retain insulating layer；
(8) wafer and lower wafer bonding are made using bonding technology, is heated to 100~300 degree, makes wafer lower surface
Salient point is immersed in the embedment hole of lower wafer upper surface；Behind the lower surface of upper wafer and the contact of the upper surface of lower wafer, it is warming up to
300~500 degree, wafer and lower wafer is made to realize Direct Bonding；After cooling, i.e., the bonding of upper wafer and lower wafer is realized simultaneously
And intermetallic bonding.
Further, the diameter of the salient point be 1 μm ~ 1000 μm, be highly 1 μm ~ 700 μm, material be copper, titanium, nickel,
The one or several kinds of gold, silver, tungsten, aluminium, tin.
Further, the diameter in the embedment hole is 1 μm~1000 μm, and depth is 1 μm~700 μm.
Further, the material of the insulating layer and upper wafer insulating layer is silica, silicon nitride, aluminium oxide or carbonization
Silicon.
Further, the material of the seed layer is the one or several kinds of copper, titanium, nickel, gold, silver, tungsten, aluminium, tin, seed
Layer with a thickness of 10nm~100 μm.
Further, the material of the pad layer is the one or several kinds of copper, titanium, nickel, gold, silver, tungsten, aluminium, tin, pad
Layer with a thickness of 100 nm~200 μm.
Further, the diameter of the soldered ball it is 10 μm smaller than the diameter for being embedded to hole~100 μm, the material of soldered ball be tin ball or
Person's tin ping-pong ball.
Present invention has the advantage that
(1) lower surface of wafer is made into salient point on, and the upper surface of lower wafer is made into embedded soldered ball, convex in welding
Point is inserted into soldered ball, realizes interconnection；
(2) after embedded soldered ball and salient point combine, metal is not present between two wafers, crystalline substance may be implemented after annealing in this way
The bonding of silica and silicon oxide interface between circle, ensure that the reliability of two panels wafer bonding.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.Wherein:
Fig. 1 a-1 is the schematic diagram of upper wafer of the present invention.
Fig. 1 a-2 is the schematic diagram of lower wafer of the present invention.
Fig. 1 b is the schematic diagram in lower wafer upper surface depositing insulating layer.
Fig. 1 c is to make the schematic diagram of seed layer and pad layer in surface of insulating layer.
Fig. 1 d is the schematic diagram that soldered ball is implanted into embedment hole.
Fig. 1 e is the schematic diagram of the applying solder paste in embedment hole.
Fig. 1 f is the schematic diagram that lower wafer crosses Reflow Soldering.
Fig. 1 g is the schematic diagram for removing lower wafer upper surface seed layer and pad layer.
Fig. 1 h is the schematic diagram that upper wafer lower surface salient point immerses that lower wafer upper surface is embedded to hole.
Fig. 1 i is the schematic diagram for realizing wafer bonding and metal bonding.
Serial number in figure: lower wafer 101, embedment hole 102, insulating layer 103, seed layer 104, pad layer 105, soldered ball 106, weldering
Tin cream 107, upper wafer 200, upper wafer insulating layer 201, salient point 202.
Specific embodiment
In order to keep the above objects, features and advantages of the present invention more obvious and easy to understand, below with reference to specific attached drawing pair
A specific embodiment of the invention is further described.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Using other than the one described here other way come embodiment, those skilled in the art can be without prejudice to intension of the present invention
In the case where do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in implementing production.
Plant ball technique of the present invention, comprising the following steps:
(1) as shown in Fig. 1 a-1, the above is upper wafer 200, deposits upper wafer insulating layer in the lower surface of upper wafer 200
201, salient point 202 is made on upper 201 surface of wafer insulating layer, salient point 202 is made of electroplating technology, and diameter is 1 μm ~ 1000 μ
M is highly 1 μm ~ 700 μm, and material is the one or several kinds of copper, titanium, nickel, gold, silver, tungsten, aluminium, tin etc.；
(2) as shown in Fig. 1 a-2, here is lower wafer 101, in position of the upper surface of lower wafer 101 relative to salient point 202
Set production embedment hole 102；The technique in production embedment hole 102 are as follows: first lithographic definition goes out to be embedded to the position in hole 102, then by dry
Method etches embedment hole 102；The diameter in the embedment hole 102 is 1 μm~1000 μm, and depth is 1 μm~700 μm；
(3) as shown in Figure 1 b, in the inner wall depositing insulating layer 103 of the upper surface of lower wafer 101 and embedment hole 102, this is absolutely
The material of edge layer 103 is silica, silicon nitride, aluminium oxide, silicon carbide；
(4) as illustrated in figure 1 c, in the surface deposited seed layer 104 of insulating layer 103, the material of seed layer 104 be copper, titanium,
The one or several kinds of nickel, gold, silver, tungsten, aluminium, tin etc., seed layer 104 with a thickness of 10nm~100 μm；In seed layer 104
Electroplating surface pad layer 105, the material of pad layer 105 are the one or several kinds of copper, titanium, nickel, gold, silver, tungsten, aluminium, tin etc., weldering
Disc layer 105 with a thickness of 100 nm~200 μm；
(5) as shown in Figure 1 d, scaling powder is sprayed on 105 surface of pad layer in embedment hole 102, is being embedded to using ball technique is planted
The inner implantation soldered ball 106 in hole 102, the diameter of soldered ball 106 are 50 μm~500 μm, 10 μm smaller than the diameter in embedment hole 102~100 μm,
The material of soldered ball 106 is tin ball or tin ping-pong ball；
It may be otherwise as shown in fig. le, be embedded in hole 102 direct applying solder paste 107；
(6) as shown in Figure 1 f, lower wafer 101 crosses Reflow Soldering, makes in soldered ball 106 or solder(ing) paste 107 and embedment hole 102
Pad layer 105 combines, then cleaning removal film of flux residue；
(7) as shown in Figure 1 g, the seed layer of lower 101 upper surface of wafer is removed using wet-etching technology or CMP process
104 and pad layer 105, only retain insulating layer 103, which can realize with upper wafer insulating layer 201 and be bonded；
(8) as shown in figure 1h, it is bonded upper wafer 200 and lower wafer 101 using bonding technology, is heated to 230 degree, makes
The salient point 202 of 200 lower surface of wafer is immersed in the embedment hole 102 of lower 101 upper surface of wafer；The lower surface of upper wafer 200 and
After the upper surface contact of lower wafer 101,400 degree are warming up to, wafer 200 and lower wafer 101 is made to realize Direct Bonding；It is cooling
Afterwards, while the bonding and intermetallic bonding for going up wafer 200 and lower wafer 101 being realized, as shown in figure 1i.
It should be noted that the above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although referring to preferable
Embodiment describes the invention in detail, those skilled in the art should understand that, it can be to technology of the invention
Scheme is modified or replaced equivalently, and without departing from the spirit and scope of the technical solution of the present invention, should all be covered in this hair
In bright scope of the claims.
Claims (7)
1. a plant ball technique, characterized in that the following steps are included:
(1) upper wafer insulating layer (201) are deposited in the lower surface of upper wafer (200), is made on upper wafer insulating layer (201) surface
Salient point (202)；
(2) consistent relative to the position production shape, size and salient point (202) of salient point (202) in the upper surface of lower wafer (101)
Embedment hole (102)；
(3) in the inner wall depositing insulating layer (103) of the upper surface of lower wafer (101) and embedment hole (102)；
(4) in the surface deposited seed layer (104) of insulating layer (103), in the electroplating surface pad layer (105) of seed layer (104)；
(5) scaling powder is sprayed on pad layer (105) surface of embedment hole (102), hole (102) are inner plants in embedment using ball technique is planted
Enter soldered ball (106)；Or in the inner directly applying solder paste (107) of embedment hole (102)；
(6) wafer (101) crosses Reflow Soldering under, makes soldered ball (106) or solder(ing) paste (107) and is embedded to hole (102) inner pad layer
(105) it combines, then cleaning removal film of flux residue；
(7) seed layer (104) and pad layer (105) for removing lower wafer (101) upper surface, only retain insulating layer (103)；
(8) it is bonded wafer (200) and lower wafer (101) using bonding technology, is heated to 100~300 degree, makes wafer
(200) salient point (202) of lower surface be immersed in lower wafer (101) upper surface embedment hole (102) it is inner；Under upper wafer (200)
Behind surface and the contact of the upper surface of lower wafer (101), 300~500 degree are warming up to, keeps wafer (200) and lower wafer (101) real
Existing Direct Bonding；After cooling, i.e., the bonding and intermetallic bonding of upper wafer (200) and lower wafer (101) are realized simultaneously.
2. ball technique is planted as described in claim 1, it is characterized in that: the diameter of the salient point (202) is 1 μm ~ 1000 μm, height
It is 1 μm ~ 700 μm, material is the one or several kinds of copper, titanium, nickel, gold, silver, tungsten, aluminium, tin.
3. ball technique is planted as described in claim 1, it is characterized in that: the diameter of embedment hole (102) is 1 μm~1000 μm,
Depth is 1 μm~700 μm.
4. ball technique is planted as described in claim 1, it is characterized in that: the insulating layer (103) and upper wafer insulating layer (201)
Material is silica, silicon nitride, aluminium oxide or silicon carbide.
5. as described in claim 1 plant ball technique, it is characterized in that: the material of the seed layer (104) be copper, titanium, nickel, gold,
The one or several kinds of silver, tungsten, aluminium, tin, seed layer (104) with a thickness of 10nm~100 μm.
6. as described in claim 1 plant ball technique, it is characterized in that: the material of the pad layer (105) be copper, titanium, nickel, gold,
The one or several kinds of silver, tungsten, aluminium, tin, pad layer (105) with a thickness of 100 nm~200 μm.
7. ball technique is planted as described in claim 1, it is characterized in that: the diameter of the soldered ball (106) is more straight than embedment hole (102)
Diameter is 10 μm small~and 100 μm, the material of soldered ball (106) is tin ball or tin ping-pong ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610866729.6A CN106252318B (en) | 2016-09-29 | 2016-09-29 | Plant ball process and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610866729.6A CN106252318B (en) | 2016-09-29 | 2016-09-29 | Plant ball process and structure |
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| Publication Number | Publication Date |
|---|---|
| CN106252318A CN106252318A (en) | 2016-12-21 |
| CN106252318B true CN106252318B (en) | 2019-01-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610866729.6A Active CN106252318B (en) | 2016-09-29 | 2016-09-29 | Plant ball process and structure |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299601A (en) * | 2021-05-21 | 2021-08-24 | 浙江集迈科微电子有限公司 | Wafer-level welding process for multilayer adapter plate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050194695A1 (en) * | 2001-03-05 | 2005-09-08 | Shih-Hsiung Lin | Method of assembling chips |
| CN101796636A (en) * | 2005-06-14 | 2010-08-04 | 丘费尔资产股份有限公司 | Chip connection method |
| CN101844740A (en) * | 2010-06-01 | 2010-09-29 | 中国科学院上海微系统与信息技术研究所 | Low-temperature bonding method based on gold silicon eutectic |
| CN103258791A (en) * | 2013-05-16 | 2013-08-21 | 华进半导体封装先导技术研发中心有限公司 | Method and relevant device for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces |
-
2016
- 2016-09-29 CN CN201610866729.6A patent/CN106252318B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050194695A1 (en) * | 2001-03-05 | 2005-09-08 | Shih-Hsiung Lin | Method of assembling chips |
| CN101796636A (en) * | 2005-06-14 | 2010-08-04 | 丘费尔资产股份有限公司 | Chip connection method |
| CN101844740A (en) * | 2010-06-01 | 2010-09-29 | 中国科学院上海微系统与信息技术研究所 | Low-temperature bonding method based on gold silicon eutectic |
| CN103258791A (en) * | 2013-05-16 | 2013-08-21 | 华进半导体封装先导技术研发中心有限公司 | Method and relevant device for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces |
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| CN106252318A (en) | 2016-12-21 |
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