TW483078B - Manufacturing method of stitch bond circuit - Google Patents

Manufacturing method of stitch bond circuit Download PDF

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Publication number
TW483078B
TW483078B TW090112002A TW90112002A TW483078B TW 483078 B TW483078 B TW 483078B TW 090112002 A TW090112002 A TW 090112002A TW 90112002 A TW90112002 A TW 90112002A TW 483078 B TW483078 B TW 483078B
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Taiwan
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bump
patent application
scope
metal
item
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TW090112002A
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Chinese (zh)
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Jr-Chiang Chen
Pei-Hua Tsau
Jung-Yu Wang
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

The present invention discloses a manufacturing method of stitch bond circuit, which proposes a globally-formed metal bump on the bonding pad. The surface of the metal bump is flat to increase the bonding area. The present method is different from the traditional stitch bonding method in which ball bump needs to be formed individually for each bonding pad. The present invention utilizes the electroplating way or non-electroplating way to grow the metal bump globally, which greatly reduces the processing time. Afterwards, a ball bump is formed by using the solder pin comprising soldering material on the lead frame, and a conductive wire is formed on top of the ball bump. Finally, a conductive wire is formed on the metal bump to bond with the metal bump, so as to complete the manufacturing method of connecting circuit by stitch bonding.

Description

483078483078

五、發明說明（i) 發明領域： 本發明係關於一種打線（w i r e b ο n d i n g )的製程，特別 是關於在半導體晶片和構裝基板間的縫合線路（s t i t e h bond)製程。 發明背景： 在IC晶片製作完後’續建立i c晶片與構裝基板上之導 線架（1 e a d f r a m e )連線，如此，才能藉由外在電路控制I c 晶片之動作。因此，在製作完IC晶片之多層金屬内連線 後’给進行打線的製f王’早期之打線方式係利用一焊針先 形成球狀凸塊（b a 1 1 b ο n d )於I C晶片之銲墊上，而後再形 成另一球狀凸塊於導線架上，並利用毛係管於構裝基板上 之球狀凸塊上延伸出導線連接至銲墊上之球狀凸塊，完成 stitch bond製程。但由於在stitch bond製程中使用焊針 產生導線連接至銲墊上之球狀凸塊時，其焊針係提供一外 力使導線連接至球狀凸塊上，此一外力會使底下之銲墊產 生裂痕。因此’製程上提出反向打線方式（reverse wire bond)以解決所述問題，係先形成球狀凸塊於導線架上， 而後形成球狀凸塊和導線於銲墊上，最後，才使導線與位 於導線架上之球狀凸塊焊接。其詳細製成程序如下所述： 首先，如圖一 A所示，提供一基板10和一導線架30，其基 板10最表面均形成一護層（Passivation 1巧6〇為保&其 下之金屬層暴露於大氣中而產生腐蝕之情形，而在護層中 會裸露出與外界連線之銲墊2〇，使用一焊針4〇内含欲形成V. Description of the invention (i) Field of the invention: The present invention relates to a process of wire bonding, in particular to the process of stitching (s t i t e h bond) between a semiconductor wafer and a mounting substrate. Background of the Invention: After the IC chip is manufactured, the connection between the IC chip and the lead frame (1 e a d f r a m e) on the mounting substrate is continued, so that the operation of the IC chip can be controlled by external circuits. Therefore, after the multilayer metal interconnects of the IC chip are made, the early wire bonding method of “to the f-king system” is to use a solder pin to form a spherical bump (ba 1 1 b ο nd) on the IC chip. On the solder pad, and then form another spherical bump on the lead frame, and use a hair tube to extend the wire to the spherical bump on the solder pad to complete the stitch bond process . However, in the stitch bond process, when a welding pin is used to generate a wire to connect to a spherical bump on a pad, the welding pin provides an external force to connect the wire to the spherical bump. This external force will cause the underlying pad to generate crack. Therefore, a reverse wire bond is proposed in the process to solve the problem. First, a spherical bump is formed on the lead frame, and then a spherical bump and a lead are formed on the bonding pad. Finally, the lead and the Solder the ball bumps on the lead frame. The detailed manufacturing process is as follows: First, as shown in FIG. 1A, a substrate 10 and a lead frame 30 are provided, and a protective layer is formed on the outermost surface of the substrate 10 (Passivation 1 The metal layer is exposed to the atmosphere to cause corrosion, and the bonding pad 20 connected to the outside is exposed in the protective layer. A solder pin 40 is used to contain the desired formation.

五、發明說明（2) 球狀凸塊之焊接材質33,如金之材質，經 供導焊接材質33於導線架3〇上。 屏口提 焊”垂直括離，其焊接材質33::物；：二’將V. Description of the invention (2) The welding material 33 of the spherical bumps, such as the material of gold, is provided on the lead frame 30 by the guide welding material 33. "Ping mouth lifting welding" vertical bracket, the welding material 33 :: 物;: 二 ’

ί 上。再來，請參考圖-L ::供焊接材質33並將焊針4〇移開導線 狀凸塊35之製作。續請參考圖_ 、 0疋成球 接材質33，如傲- 所 將卜針40内之焊 彤忐找你几 材質，經由焊針4 0開口提供焊接材質以 形成球狀凸塊！ 5焊接於Ic晶片之 鋒！I材貝 離球狀凸塊15但仍於焊針辦 接2焊針鄕 塊15上方形成導線17，同時移二質使球狀凸 口 ί =狀凸塊35上方，*圖- E所示。使導 、貝0月多考圖一 F所示，焊斜4恤 球狀凸塊35接合，並產生超九供-外力將導線17與 音波能量焊接導線17和球狀里，::便能利用此超 球狀凸塊35,完成打線動作。▲ 5,而後才將焊針40抬離 此_ stitch bond方式 f： 士丨 m 次僅能製作出單個球狀凸塊，而用:針製作球狀凸塊且- 積密度增加時，其元件與外界的ί = ，ΐ元件的ί on. Again, please refer to Figure -L :: for welding material 33 and remove the solder pin 40 from the wire-shaped bump 35. Continue to refer to the picture _, 0 疋 into the ball to connect the material 33, such as Ao-so the welding in the pin 40 to find you a few materials, through the welding pin 40 opening to provide the welding material to form a spherical bump! 5 Solder to the front of IC chip! I material is separated from the spherical bump 15 but still forms a wire 17 above the solder pin connection 2 and the welding pin block 15 while moving the second mass to make the spherical bump = = the convex bump 35, as shown in Figure E. . As shown in Figure 1F, the guide and the shell will be welded with the oblique 4-shirt ball-shaped bumps 35 to produce a super-nine supply-external force. With this hyperspherical bump 35, the threading action is completed. ▲ 5, and then lift the welding pin 40 away from this _ stitch bond method f: 丨 丨 m times can only make a single spherical bump, and using: needle to make a spherical bump and-when the bulk density increases, its component Ί = to the outside

Stitch bQnd方式製作其^\路“增加’右以 凸塊3 5和導線i 7之接和時幵有限。且在進行球狀 打線之準確ί ::坦亦會降低打線效率和 法，係增加打線製程之效率，一線路縫合的製造方 解決上述所造成之問題。 483078 483078Stitch bQnd method to make it ^ \ the way "increasing" the connection between the right side of the bump 3 5 and the wire i 7 is limited. And the accuracy of the ball-shaped wire ί: Tan will also reduce the efficiency and method of wire tying, increasing For the efficiency of the threading process, the manufacturer of a line stitching solves the problems caused above.

圖號說明： 1 5 -球形凸塊 2 0-銲墊 3〇 -導線架 3 5 -球形凸塊 1 〇 〇 -金屬凸塊 1 〇 -基板 17-導線 2 5 -護層 3 3 -阻障層 4 0 -焊針 11 〇 -金屬凸塊 Θ 發明詳細說明： 本發明可應用在以縫合方式連接線路的製程 在銲墊上全面性沈積一層符合銲墊接觸窗大小之金^由 塊’增加線路縫合之打線效率和打線之準確性。以 — 施例將利用已完成超大型積體電路之主要元件及多芦I 連線製作後，接續，欲形成線路縫合的製程，來& 明之技術手段。 &Description of drawing number: 1 5-spherical bump 2 0-pad 3〇-lead frame 3 5-spherical bump 1 〇〇-metal bump 1 〇-substrate 17-wire 2 5-sheath 3 3-barrier Layer 4 0-solder pin 11 〇-metal bump Θ Detailed description of the invention: The present invention can be applied to the process of connecting lines by stitching. A layer of gold is deposited on the pad in accordance with the size of the contact window of the pad. The efficiency and accuracy of stitching. Taking this example as an example, we will use the main components of the ultra-large integrated circuit and the Dolu I connection after fabrication, and then continue the process of forming the line stitching to the technical means of the Ming. &

首先，提供一半導體矽基板1〇,其上述之半導體碎基 板1 0已完成主要電性元件、内連線結構製作（圖中未示）: 於圖二A之不意圖中僅表現出最上層銲墊接觸窗中之銲墊 2 0用來與導線架相通，及最上層之護層25用以防止最上層 之金屬連線接觸到空氣中的水氣及酸氣而產生腐餘現象， 其上述之護層15係使用氮化矽（Si 3N4)作為保護層材料， 多採取電漿增強化學氣相沉積法（p 1 a s m a E n h a n c e dFirst, a semiconductor silicon substrate 10 is provided. The above-mentioned semiconductor chip substrate 10 has completed the production of main electrical components and interconnect structures (not shown in the figure): it only shows the uppermost layer in the intention of FIG. 2A The pad 20 in the pad contact window is used to communicate with the lead frame, and the uppermost protective layer 25 is used to prevent the uppermost metal connection from coming into contact with water vapor and acid gas in the air to cause corrosion. The protective layer 15 mentioned above uses silicon nitride (Si 3N4) as the protective layer material, and more often adopts plasma enhanced chemical vapor deposition (p 1 asma E nhanced

第7頁 483078 五、發明說明（5)Page 7 483078 V. Description of the invention (5)

Chemical Vapor Deposition; PECVD)的方式沈積。而其 銲墊2 0係使用濺鍍方式（sputter)沈積鋁合金（A1 alloy) 或銅合金（Cu alloy)。 接續，進入本發明之重點，本發明實施例係在銲墊2 0 上全面性沈積一層符合銲墊接觸窗大小之金屬凸塊，其全 面性沈積係可使用如圖二B所示之電鍍方式（p 1 a t i ng process)或如圖二c所示之無電極電鍍方式（electroless process)製作而成。Chemical Vapor Deposition; PECVD). The pad 20 is sputter-deposited with an aluminum alloy (A1 alloy) or a copper alloy (Cu alloy). Continuing, and entering the focus of the present invention, the embodiment of the present invention is to deposit a layer of metal bumps on the pad 20 in accordance with the size of the contact window of the pad. The comprehensive deposition can use the plating method shown in Figure 2B (P 1 ati ng process) or the electrodeless plating method shown in FIG. 2c.

若採用電艘方式，係將基板置於含金之電鍵液中進行 電鍍。如圖二B所示，在電鍍過程中，由於基板的最表面 僅有銲墊2 0上為金屬材質，其餘為介電層材質之護層25， 因此，僅有銲墊2 0上方會有金屬材質之金屬凸塊1〇〇生 成，不需使用任何微影製程定義出金屬凸塊位置。其所形 成之金屬凸塊1〇〇厚度與習知技術中形成之球狀凸塊高度 相同，其其所形成之金屬凸塊1 〇 0寬度和銲墊接觸窗相 同。不同點在於所形成之塊狀凸塊由於表面平坦，因此， 可進行焊接範圍增大，如此更易於進行後續之導線焊接之 步驟。 另’由於本發明實施例中係一次成長所有之金屬凸塊If the electric boat method is adopted, the substrate is plated in a gold-containing key solution. As shown in FIG. 2B, during the electroplating process, since only the pad 20 is made of metal on the outermost surface of the substrate, and the rest is a protective layer 25 made of a dielectric layer, only the pad 20 has Metal bumps of metal material are generated at 100, without using any lithography process to define the position of the metal bumps. The thickness of the metal bump 100 formed is the same as the height of the spherical bump formed in the conventional technology, and the width of the metal bump 100 formed is the same as that of the pad contact window. The difference lies in that the formed bumps have a flat surface, so that the range of soldering can be increased, which makes it easier to perform subsequent wire bonding steps. In addition, because all the metal bumps are grown at one time in the embodiment of the present invention

1 0 0，因此，可省下製程上個別形成凸塊之時間，大大提 高產能。且所形成之金屬凸塊厚度可隨順製程需要而調 變’不再戈限於焊針之半徑大小和焊接材質本身之凝聚 力。 其使用無電鍍方式，如圖二c所示，係將基板置於含1 0 0, therefore, it can save the time of individual bump formation in the process and greatly increase the production capacity. And the thickness of the formed metal bump can be adjusted according to the needs of the process. It is no longer limited to the radius of the welding pin and the cohesion of the welding material itself. It uses an electroless plating method, as shown in Figure 2c.

第8頁 483078Page 8 483078

t之無電鍍液中進行無電鍍步驟，由於基板的最表面僅有 銲墊20上為金屬材質，因此，無電鍍液僅會在銲墊20上沈 積金屬之金屬凸塊i 10，其係先沈積金屬鎳（Ni)增加金和 銲墊2 0間之附著力，再續沈積金於其上。 在製作完金屬凸塊1〇〇/11〇後，便可進行如習知技術 中圖一 D至圖一 F類似的打線縫合技術。The electroless plating step is performed in the electroless plating solution of t, because only the pad 20 is made of metal on the outermost surface of the substrate. Therefore, the electroless plating solution only deposits metal bumps i 10 on the pad 20, which is the first Depositing metal nickel (Ni) increases the adhesion between the gold and the pad 20, and then deposits gold on it. After the metal bumps 100/110 have been fabricated, the thread-stitching technique similar to that in Figs. 1D to 1F of the conventional technique can be performed.

$圖一 D所不，使用焊針40，其内含焊接材質3 3如金 f t質’經由焊針40提供焊接材質和能量以形成球狀凸塊 /焊接於導線架3 〇上，續將焊針4 〇抬離球狀凸塊3 5但仍於 悍針4 0中持續提供焊接材質使球狀凸塊3 5上方形成導線 17同時移動焊針4 0使導線形成至金屬凸塊1 0 0 / 1 1 0上 方新如圖一 E所示’在移動焊針4 0之同時以不斷提供焊接 材質方式不致使導線i 7在焊針4 〇移動時而斷掉。 續請參考圖二F所示，藉由焊針40將導線丨7牽引至金 1凸塊1 0 〇 / 1 1 〇上方後，使導線1 7與金屬凸塊1 〇 〇 /丨丨〇接 合/係使用超音波能量焊接導線1 7和金屬凸塊1 〇 〇 /丨丨〇， 而後才將焊針40抬離金屬凸塊100/110，完成打線動作。$ 图 一 D, using a welding pin 40, which contains a welding material 3 3 such as gold ft quality 'provides the welding material and energy via the welding pin 40 to form a spherical bump / welding on the lead frame 3 〇, continued The welding pin 4 is lifted away from the spherical bump 3 5 but the welding material is still provided in the hard pin 40 to form a wire 17 above the spherical bump 3 5 while moving the welding pin 4 0 to form the wire to the metal bump 1 0 The top of 0/1 1 0 is new as shown in Fig. 1E 'while moving the welding pin 40 while continuously providing the welding material, the wire i 7 will not be broken when the welding pin 4 〇 moves. Continuing, please refer to FIG. 2F. After the lead 丨 7 is pulled to the top of the gold 1 bump 1 0 〇 / 1 1 〇 by the solder pin 40, the lead 17 is bonded to the metal bump 1 〇〇 / 丨 丨/ The system uses ultrasonic energy to weld the wire 17 and the metal bump 100, and then the solder pin 40 is lifted away from the metal bump 100/110 to complete the wire bonding action.

以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明的範圍，因此熟知此技藝的人士應能明瞭，適當 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不^離本發明之精神和範圍，故都應視為本發明的進一步 實施狀况。謹請貴審查委員明鑑，並祈惠准，是所至 禱。The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation status of the present invention. I would like to ask your reviewing committee to make a clear reference and pray for your sincere prayer.

第9頁 483078 圖式簡單說明 圖式簡要說明： 圖一 A為習知技術中提供焊接材料於導線架上形成球 狀凸塊之製程剖面示意圖。 圖一 B為習知技術中形成導線架上之球狀凸塊之製程 剖面示意圖。 圖一 C為習知技術中形成導線架上之球狀凸塊之製程 剖面示意圖。 圖一 D為習知技術中形成銲墊上之球狀凸塊之製程剖 面示意圖。Page 9 483078 Brief description of the drawings Brief description of the drawings: Figure 1A is a schematic cross-sectional view of a conventional process for providing soldering materials on a lead frame to form spherical bumps in the conventional technology. FIG. 1B is a schematic cross-sectional view of a manufacturing process for forming a spherical bump on a lead frame in the conventional technology. FIG. 1C is a schematic cross-sectional view of a manufacturing process for forming a spherical bump on a lead frame in the conventional technology. FIG. 1D is a schematic cross-sectional view of a manufacturing process for forming a spherical bump on a solder pad in the conventional technology.

圖一 E為習知技術中於銲墊上之球狀凸塊形成導線之 製程剖面示意圖。 圖一 F為習知技術中導線焊接至導線架上之球狀凸塊 之製程剖面示意圖。 圖二A為本發明實施例中晶片最上層之製程剖面示意 圖。 圖二B為本發明實施例中使用電鍍方式於銲墊上成長 金屬凸塊之製程剖面示意圖。 圖二C為本發明實施例中使用無電鍍方式於銲墊上成 長金屬凸塊之製程剖面示意圖。FIG. 1E is a schematic cross-sectional view of a process for forming a conductive line with a spherical bump on a solder pad in the conventional technology. FIG. 1F is a schematic cross-sectional view of a conventional process for soldering a wire to a ball bump on a lead frame. FIG. 2A is a schematic cross-sectional view of the manufacturing process of the uppermost layer of the wafer in the embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of a process for growing metal bumps on a pad by using an electroplating method in an embodiment of the present invention. FIG. 2C is a schematic cross-sectional view of a process for forming metal bumps on a pad by using an electroless plating method in an embodiment of the present invention.

圖二D為本發明實施例中於導線架上形成球狀凸塊之 製程剖面示意圖。 圖二E為本發明實施例中於導線架上之球狀凸塊形成 導線之製程剖面示意圖。 圖二F為本發明實施例中導線焊接至銲墊上之金屬凸FIG. 2D is a schematic cross-sectional view of a process for forming a spherical bump on a lead frame according to an embodiment of the present invention. FIG. 2E is a schematic cross-sectional view of a process for forming a wire by a spherical bump on a lead frame according to an embodiment of the present invention. FIG. 2F is a metal projection of a wire soldered to a pad in an embodiment of the present invention

第10頁 483078 圖式簡單說明 塊之製程剖面示意圖。 Η·ΙPage 10 483078 Schematic illustration of the process cross-section of the block. Η · Ι

Claims (1)

483078 秦483078 Qin 六、申請專利範圍 申請專利範圍： 1. 一種以缝合方式連接線路（stitch bond)的製造方法， 係包括： (a )沈積一金屬凸塊於一銲塾（b ο n d p a d )結構上，其所 述銲墊結構係位於已製作完成元件基板之最上層； (b) 使用内含焊接物質之焊針形成一球形凸塊於構裝基 板之導線架（lead frame)上； (c) 使用内含焊接物質之焊針於所述之球形凸塊上端形 成導線； (d )移動所述焊針使所述導線和所述金屬凸塊焊接。 2. 如申請專利範圍第1項所述以缝合方式連接線路的製造 方法，其中所述之金屬凸塊係使用電鍍（plating)方式 形成。 3. 如申請專利範圍第2項所述以缝合方式連接線路的製造 方法，其中所述之金屬凸塊係為金之材質。 4. 如申請專利範圍第1項所述以縫合方式連接線路的製造 方法，其中所述之金屬凸塊係使用無電鍍 (electroless)方式形成。 5. 如申請專利範圍第4項所述以縫合方式連接線路的製造 方法，其中所述之金屬凸塊係為錄和金之雙層結構。VI. Scope of patent application Scope of patent application: 1. A method for manufacturing stitch bonds by stitching, comprising: (a) depositing a metal bump on a solder pad (b ο ndpad) structure; The pad structure is located on the uppermost layer of the completed component substrate; (b) a solder bump containing a soldering substance is used to form a spherical bump on the lead frame constituting the substrate; (c) using the included A welding pin of a welding substance forms a wire at the upper end of the spherical bump; (d) moving the welding pin to weld the wire and the metal bump. 2. The manufacturing method of connecting lines by stitching as described in item 1 of the scope of patent application, wherein the metal bumps are formed using plating. 3. The manufacturing method of connecting lines by stitching as described in item 2 of the scope of patent application, wherein the metal bumps are made of gold. 4. The manufacturing method of connecting lines by stitching as described in item 1 of the scope of the patent application, wherein the metal bumps are formed using an electroless method. 5. The manufacturing method of connecting lines by stitching as described in item 4 of the scope of the patent application, wherein the metal bumps are a double-layered structure made of metal and gold. 第12頁 483078 毳 六、申請專利範圍 6 .如申請專利範圍第1項所述以缝合方式連接線路的製造 方法，其中所述之銲接物質係為金。 7 ·如申請專利範圍第1項所述以縫合方式連接線路的製造 方法，其中所述之步驟（d )係使用超音波能量用以焊 接。 8 · —種連接線路裝置，用以導通銲塾（b ο n d p a d )和導線架 (lead frame)，其係包括有： 一金屬凸塊，係位於晶片之銲墊結構上方，其所述金屬 凸塊的寬度和所述銲墊之接觸窗寬度相同； 一球形凸塊，係位於導線架上方； 一導線，係連接所述金屬凸塊和所述球形凸塊； 其特徵在於： 所述金屬凸塊係使用沈積方式一次成長所述晶片上所有 之金屬凸塊。 9 .如申請專利範圍第8項所述連接線路裝置，其中所述之 沈積方式係使用電鍍（p 1 a t i n g )方式形成金屬凸塊。 1 〇 .如申請專利範圍第9項所述連接線路裝置，其中所述之 金屬凸塊係為金（A u )之材質。Page 12 483078 六 6. Scope of patent application 6. The manufacturing method of connecting lines by stitching as described in item 1 of the scope of patent application, wherein the welding substance is gold. 7 · The manufacturing method of connecting lines by stitching as described in item 1 of the scope of patent application, wherein said step (d) uses ultrasonic energy for welding. 8 · A connection line device for conducting a solder pad (b ο ndpad) and a lead frame, comprising: a metal bump, which is located above a pad structure of a wafer, and the metal bump The width of the block is the same as the width of the contact window of the pad; a spherical bump is located above the lead frame; a wire is connected between the metal bump and the spherical bump; characterized in that: the metal bump Bumps use deposition to grow all metal bumps on the wafer at one time. 9. The connection line device according to item 8 of the scope of the patent application, wherein the deposition method is to form a metal bump using a plating method (p 1 a t i n g). 10. The connection circuit device according to item 9 of the scope of the patent application, wherein the metal bumps are made of gold (Au). 第13頁 483078 六、申請專利範圍 1 1 ·如申請專利範圍第8項所述連接線路裝置，其中所述之 沈積方式係使用無電鍍（electroless)方式形成金屬凸 塊。 1 2 .如申請專利範圍第8項所述連接線路裝置，其中所述 之金屬凸塊係為録（N i )和金之雙層結構。 1 3 .如申請專利範圍第8項所述連接線路裝置，其中所述之 球形凸塊和所述導線係使用内含焊接物質之焊針形成。 1 4 .如申請專利範圍第8項所述連接線路裝置，其中所述之 球形凸塊的材質係為金。Page 13 483078 6. Scope of patent application 1 1 · The connection line device as described in item 8 of the scope of patent application, wherein the deposition method is to form a metal bump using an electroless method. 12. The connection circuit device according to item 8 of the scope of the patent application, wherein the metal bumps are a double-layer structure of Ni (Ni) and gold. 1 3. The connection line device according to item 8 of the scope of the patent application, wherein the spherical bumps and the wires are formed using a solder pin containing a soldering substance. 14. The connection circuit device according to item 8 of the scope of the patent application, wherein the material of the spherical bump is gold. 第14頁 iP. 14 i
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103533B (en) * 2013-04-03 2017-06-23 矽品精密工业股份有限公司 Welding method of welding wire

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103533B (en) * 2013-04-03 2017-06-23 矽品精密工业股份有限公司 Welding method of welding wire

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