JP2005303176A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve connection reliability at the time of flip chip connection. <P>SOLUTION: In a semiconductor device, a part of the wiring pattern 6 of a carrier board 8 and the surface of a semiconductor chip 1 are flip-chip-connected. In the bump size of a bump formed on an electrode pad of an area at the time of flip chip connection, a peripheral edge area is larger than a center area in a plane of the semiconductor chip 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to the arrangement and size of electrode pads and bumps on the electrode pads in a semiconductor chip constituting a semiconductor device by flip chip connection, and a plurality of electrode pads of the semiconductor chip are arranged in a frame shape, The present invention relates to a semiconductor device having a structure that ensures flip-chip connection reliability.

  FIG. 8 is a configuration diagram of a conventional semiconductor device, here, a flip chip mounting type semiconductor device called a CSP (Chip Size Package). 8A is a plan view of a semiconductor chip mounted on the semiconductor device and an enlarged view of the periphery of the pad, FIG. 8B is a cross-sectional view of a flip-chip mounting type semiconductor device, and FIG. The perspective view is shown.

  As shown in FIG. 8A, in the semiconductor chip 1, electrode pads for connection to the outside of the semiconductor chip 1 are formed, and gold bumps are formed on the electrode pads. The electrode pad includes an outermost peripheral electrode pad 2 arranged as a peripheral at the outermost peripheral part and a central region area electrode pad 3 arranged as an area at the center of the chip. Central area area bumps 5 are formed. The enlarged view shows the outermost peripheral electrode pad 2 portion in the plan view B position.

  As shown in FIG. 8B, in the semiconductor device, the outermost peripheral edge bump 4 and the central area area bump 5 of the semiconductor chip 1 are a single-layer or multi-layer substrate in which a wiring pattern 6 is formed in each layer. It is connected to the wiring pattern 6 on the front surface of the substrate 8, and is further connected to an external terminal 9 that leads out of the semiconductor device on the back surface of the carrier substrate 8 through the wiring pattern 6 in the carrier substrate 8. A gap between the carrier substrate 8 and the semiconductor chip 1 is sealed with a sealing resin 7.

Conventionally, the outermost peripheral electrode pad 2 and the central region area electrode pad 3 have the same size in the chip. Further, the outermost peripheral edge bump 4 and the central area area bump 5 on the outermost peripheral electrode pad 2 and the central area electrode pad 3 have the same size (for example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 01-238148

  However, in the configuration of the conventional semiconductor device, the flip-chip connected semiconductor chip 1 has a strain stress due to thermal expansion / contraction applied to the outermost peripheral bump 4 formed on the outermost peripheral edge of the semiconductor chip 1. Since it is larger than the stress applied to the central region area bump 5 formed in the central region, the connection reliability at the outermost peripheral portion is inferior to the connection reliability of the central region.

  In general, the strain stress due to thermal expansion and contraction correlates with the temperature difference applied to the bump and the distance from the central point of the semiconductor chip. When the temperature difference is uniform, the stress applied to the bump formed at a position where the distance from the central point of the semiconductor chip is large is greater than the stress applied to the bump formed near the center of the semiconductor chip. As a result, when the bump size is the same in the semiconductor chip, the connection reliability of the bump formed on the outermost peripheral edge of the semiconductor chip, which is located at a large distance from the central reference point of the semiconductor chip, is the bump formed near the central area. It is inferior to connection reliability, and the reliability as a semiconductor device is not ensured.

  In order to solve this problem, a semiconductor device of the present invention includes a carrier substrate having a wiring pattern on the front surface and an external terminal connected to the wiring pattern on the back surface, and an integrated circuit element and a plurality of frames on the front surface. A semiconductor chip formed with a plurality of arranged electrode pads, and a part of the wiring pattern of the carrier substrate and a bump formed on the electrode pad on the surface of the semiconductor chip are flip-chip connected The bump formed on the electrode pad at the time of flip chip connection has a structure in which the bump size is larger in the peripheral region than in the central region in the plane of the semiconductor chip. Yes. In addition, bumps formed on a plurality of electrode pads arranged in a plurality of frames in a semiconductor chip plane are different in bump diameter from the center of the semiconductor chip by 1.1 times / mm or more in the outer peripheral direction. It is a semiconductor device having.

  As described above, the present invention has a structure in which the bump forming size on the semiconductor chip constituting the semiconductor device is larger in the peripheral portion in the plane of the semiconductor chip than in the central region, and an electrode capable of realizing it. By configuring the pad opening size, connection reliability at the time of flip-chip connection can be improved.

  Hereinafter, an embodiment of a semiconductor device of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of a semiconductor device according to the first embodiment of the present invention, here, a flip-chip mounting type semiconductor device. 1A is a plan view of a semiconductor chip mounted on a semiconductor device, FIG. 1B is a plan view when bumps are formed on electrode pads of the semiconductor chip, and an enlarged view around the pad, FIG. ) Shows a cross-sectional view taken along the line AA ′ of FIG. 1B in a flip-chip mounting type semiconductor device.

  As shown in FIG. 1A, the semiconductor chip 1 is formed with electrode pads for electrical connection to the outside of the semiconductor chip 1, and an outermost peripheral electrode pad 12 peripherally arranged on the outermost peripheral edge. First, second, and third central region area electrode pads 13, 14, and 15 are sequentially formed in a rectangular frame shape from the outermost peripheral edge toward the center of the chip.

  As shown in FIG. 1B, on the outermost peripheral electrode pad 12 and the first, second and third central region area electrode pads 13, 14, 15 respectively, the outermost peripheral bump 16 and the first Second and third central area bumps 17, 18, and 19 are formed.

  As shown in FIG. 1C, the semiconductor device includes the outermost peripheral bump 16, the first, second, and third central area bumps 17, 18, and 19 of the semiconductor chip 1, and the wiring pattern 6 in each layer. It is flip-chip connected to the wiring pattern 6 on the surface of the carrier substrate 8 which is the formed single-layer or multiple-layer substrate, and is further drawn out to the outside of the semiconductor device on the back surface of the carrier substrate 8 via the wiring pattern 6 in the carrier substrate 8. It is connected to the external terminal 9. A gap between the carrier substrate 8 and the semiconductor chip 1 is sealed with a sealing resin 7.

  In the semiconductor device of the present invention, the first, second and third central region area bumps 17, 18 and 19 are configured to be smaller than the outermost peripheral bump 16. Furthermore, the size of the first, second, and third central region area bumps 17, 18, and 19 is configured so as to decrease from the outermost peripheral edge toward the center. That is, the size of the bumps decreases in the order of the first central region area bump 17, the second central region area bump 18, and the third central region area bump 19.

  Here, the correlation between the diameter of the outermost peripheral bump 16 of the semiconductor chip 1 and the bump diameter of the first, second, and third central region area bumps 17, 18, 19 is expressed by the following equations (1), (2), It is represented by (3).

(Diameter of third central region area bump 19) × 1.1 × (pitch distance between bumps) ≦ (diameter of second central region area bump 18) (1)
(Diameter of second central region area bump 18) × 1.1 × (pitch distance between bumps) ≦ (diameter of first central region area bump 17) (2)
(Diameter of first central region area bump 17) × 1.1 × (pitch distance between bumps) ≦ (diameter of outermost peripheral bump 16) (3)
The sizes of the outermost peripheral electrode pad 12 and the first, second, and third central region area electrode pads 13, 14, and 15 are configured to change according to the size of the bump formed thereon. , Same.

  As described above, by sequentially reducing the size of the bump and the electrode pad from the outermost peripheral portion, the difference in stress applied to each bump is reduced, which is effective for a semiconductor chip having a large number of electrode pads. Connection reliability is improved, and reliability as a semiconductor device is ensured.

  FIG. 2 is a configuration diagram of a semiconductor device according to the second embodiment of the present invention, here, a flip-chip mounting type semiconductor device. 2A is a plan view of a semiconductor chip mounted on a semiconductor device, FIG. 2B is a plan view when bumps are formed on electrode pads of the semiconductor chip, and FIG. 2C is flip-chip mounting. 1 shows a cross-sectional view of a type semiconductor device.

  The difference from the semiconductor device in the first embodiment shown in FIG. 1 is that the size of the first, second, and third central region area bumps 17, 18, 19 is smaller than the outermost peripheral bump 16. However, the first, second, and third central region area bumps 17, 18, and 19 have the same size. Similarly, the first, second, and third central region area electrode pads 13, 14, and 15 have the same size and a smaller configuration than the outermost peripheral electrode pad 12.

Here, the correlation between the diameter of the outermost peripheral bump 16 of the semiconductor chip 1 and the bump diameter of the first, second, and third central region area bumps 17, 18, 19 is expressed by the following formula (4).
(Diameter of first central area area bump 17) = (diameter of second central area area bump 18) = (diameter of third central area area bump 19) ≦ (diameter of outermost peripheral edge bump 16) / ( 1.1 x pitch distance between bumps) (4)
As described above, by reducing the size of the bump and the electrode pad in the central region from the outermost peripheral edge, the difference in stress applied to each bump is reduced, which is effective for a semiconductor chip having a small number of electrode pads. As a result, the bump connection reliability is improved and the reliability of the semiconductor device is ensured. Further, by limiting to the size of the two types of electrode pads and bumps in the central region and the outermost peripheral edge, the manufacturing process and quality control can be simplified as compared with the first embodiment.

  Although not shown here, the arrangement of the electrode pads and bumps formed in the central region of the semiconductor chip may be an area (lattice) arrangement or a honeycomb (honeycomb) arrangement.

  FIG. 3 is a cross-sectional view showing connection bumps of a semiconductor device according to an embodiment of the present invention. 3A is a cross-sectional view of a flip-chip mounting type semiconductor device (sealing resin is not shown), and FIGS. 3B, 3C, and 3D are the same as FIG. FIG. 4 is an enlarged view of the outermost peripheral bump 16 portion shown in the figure, and shows three patterns depending on the connection bump method.

  In the connection bump method shown in FIG. 3B, a gold stud bump 21 is formed on the electrode pad 12 in the semiconductor chip 1, and the connection resin 22 is placed on the gold stud bump 21 by a transfer method. This is a method of bonding to the wiring pattern 6. This connection method is called an SBB (stud bump bonding) method. The connection resin 22 includes, for example, an adhesive made of epoxy resin as a binder and Ag—Pd coprecipitate as a conductor filler.

  The connection bump method of FIG. 3C is a method of forming a gold plating bump 24 on the electrode pad 12 in the semiconductor chip 1. In general, the gold plating bumps 24 are collectively formed on the electrode pads 12 of each semiconductor chip 1 in a semiconductor wafer state. As a manufacturing method, in order to form gold plating bumps 24 on the electrode pads 12 of each semiconductor chip 1 in a semiconductor wafer state, TiN and Au are vapor-deposited on the electrode pads 12 of the semiconductor wafer by sputtering, and AL-TiN. -A layer of Au is formed. Thereafter, a mask opened only on the electrode pad 12 is covered, and gold plating is performed on the electrode pad 12 by an electrolytic plating method. Then, the resist is removed, and a gold plating bump 24 is formed.

  The connection bump method of FIG. 3D is a method of forming solder plating bumps 25 on the electrode pads 12 in the semiconductor chip 1. In general, solder plating bumps 25 are collectively formed on the electrode pads 12 of each semiconductor chip 1 in a semiconductor wafer state. As a manufacturing method, solder plating bumps 25 are collectively formed on the electrode pads 12 of each semiconductor chip 1 in a semiconductor wafer state, TiN and N are vapor-deposited on the electrode pads 12 of the semiconductor wafer, and AL-TiN- N layers are formed. Thereafter, a mask opened only on the electrode pad 12 is covered, and Sn—Ag solder plating is performed on the electrode pad 12 by an electrolytic plating method. Then, the resist is removed, and a solder plating bump 25 is formed.

  Here, although the outermost peripheral bump 16 has been described as an example, the same applies to the first, second, and third central region area bumps 17, 18, and 19.

  FIG. 4 is a diagram showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and shows a method for manufacturing a bump.

  FIG. 4A shows a process in which a plurality of electrode pads arranged in a plurality of frame shapes in the plane of the semiconductor chip 1 form a peripheral region larger than the central region. Here, the case where it arranges in three frame shape is shown.

  Outermost peripheral edge bump 16 formed on outermost peripheral electrode pad 12 and first and second central area electrode pads 13 and 14 on the surface of semiconductor chip 1, first and second central area area bump 17, respectively. The size of 18 is about φ 0.03 to 0.1 mm, and the height is about 0.01 to 0.05 mm. The size of the outermost peripheral electrode pad 12 and the first and second central region area electrode pads 13 and 14 is several tens of the size of the outermost peripheral bump 16 and the first and second central region area bumps 17 and 18. Form larger than μm. The semiconductor chip 1 is formed by forming an integrated circuit (transistor or the like) on the surface layer of the single crystal silicon base material, and then electrically connecting with a plurality of layers (3 to 4 layers) that are conducted with W, Ti, TiN, etc. Further, they are electrically connected by Cu wiring patterning with a thickness of 30 nm to 1000 nm on the surface layer, and connected to arbitrary outermost peripheral electrode pads 12 and first and second central region area electrode pads 13 and 14. The outermost peripheral electrode pad 12 and the first and second central region area electrode pads 13 and 14 are provided with AL and Cu layers, and AL, Pd, Au, or the like is formed on the outermost surface by CVD or the like. This is to maintain the reliability of bonding after assembly, such as the impact of ultrasonic waves, load, heat, etc. during bonding when forming the outermost peripheral bump 16, the first and second central area bumps 17, 18. .

  FIG. 4B shows a process of forming bumps on the electrode pads so that the peripheral area is larger than the central area.

  Bump outermost peripheral bump 16, which is a gold stud, and first and second central region area bumps 17 and 18 are formed by using a gold wire 31 of φ18 μm to φ30 μm by a wire bonder equipment of a thermocompression bonding / ultrasonic method, A ball formed at the tip of the gold wire 31 is brought into thermal contact with the electrode pad to form a lower step portion of the two-step protrusion of the gold stud bump, and further, the capillary 30 is moved to provide a loop of the formed gold wire 31. The upper step portion of the two-step protrusion is formed.

  At this time, the outermost peripheral bump 16 is formed on the outermost peripheral electrode pad 12 and the first and second central area electrode pads 13 and 14 in the plane of the semiconductor chip 1 by using the same gold wire diameter 32. The gold derived from the capillary 30 so that the sizes of the first central area area bump 17 and the second central area area bump 18 become smaller in order, that is, smaller toward the central area than the peripheral area. Different gold balls are generated by adjusting the current value condition and discharge time at the tip of the wire 31 to form gold stud bumps of different sizes. When described as gold stud bumps, the bump outermost peripheral bump 16 and the first and second central region area bumps 17 and 18 are collectively referred to. The bumps may be other than gold or stud bumps.

  FIG. 4C shows a step of leveling (flattening) the top of the gold stud bump. Immediately after the step of FIG. 4B, even if the gold stud bumps of the same size are used, the height of the bumps is not uniform, and the flatness of the top of the head is lacking. Is pressed with a leveling tool 33 to make the height uniform and level the top of the head. Here, the outermost peripheral bump 16 on the outermost peripheral electrode pad 12 in the peripheral region in the plane of the semiconductor chip 1 and the first and second central region area bumps 17 and 18 in the central region are different from each other. By leveling at 35, 36, and 37, the top of each gold stud bump can be optimally flattened.

  4D and 4E show a plan view in which gold stud bumps of different sizes are formed in the semiconductor chip 1 and a cross-sectional view of the gold stud bump 38 after leveling the top.

  FIG. 5 is a process showing a part of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

  5A and 5B show a state in which the outermost peripheral edge bump 16 and the first and second central region area bumps 17 and 18 having different sizes are formed in the semiconductor chip 1. A part is shown, and a state in which the outermost peripheral bump 16 and the first and second central region area bumps 17 and 18 are covered with the connection resin 40 by a transfer method is shown.

  As shown in FIG. 5B, the connecting resin 40 is prepared with a uniform thickness on a table such as a petri dish, and the connecting resin 40 is placed on the gold stud bump by a transfer method. At this time, the semiconductor chip 1 and the carrier substrate 8 can be satisfactorily connected by adjusting and covering the connecting resin 40 on the outermost peripheral edge bump 16 and the first and second central area area bumps 17 and 18 of different sizes.

  FIG. 5C shows the position of the semiconductor chip 1 with the connection resin 40 covered with gold stud bumps on the wiring pattern 6 on the surface of the individual carrier substrate 8 of the sheet substrate 41 (a collection of a plurality of carrier substrates 8). In addition, the state of flip chip connection is shown. The carrier substrate 8 is made of ceramic in which wiring layers are laminated in a plurality of layers, and a wiring pattern 6 of a tungsten layer is embedded between each layer. Vias connecting portions (electrically connected portions) are electrically connected with molybdenum material. The portion to be connected to the outermost peripheral electrode pad 12 and the first and second central region area electrode pads 13 and 14 of the semiconductor chip 1 and the portion to be the external terminal 9 is made of tungsten having a thickness of 10 to 30 μm. An electroless plating is applied to the wiring to form a Ni layer having a thickness of several μm and an Au layer having a thickness of about 0.1 μm to 0.8 μm.

  FIG. 5D shows a step of filling the sealing resin 7 with the sealing resin nozzle 43 so as to cover the gold stud bump in the gap between the surface of the carrier substrate 8 flip-chip connected and the surface of the semiconductor chip 1. ing.

  FIG. 5E shows a state of the process of separating the sheet substrate 41 into individual carrier substrates 8 by the cutting saw 45. In order to separate the individual carrier substrates 8 with the cutting saw 45, the sheet substrate 41 is fixed with a jig, and the cutting saw 45 rotated at 20000 rpm to 50000 rpm while spraying cutting water is 10 mm / s to 100 mm / s. Cutting and separating. The material structure of the cutting saw 45 is composed of abrasive grains corresponding to a grindstone and a bond material for bonding them. Generally, the abrasive grains are made of diamond, cubic boron nitride, GC, A, WA or the like, and the bond material is plated with a metal such as nickel such as electrodeposition or electroforming, frit, ceramic, etc. It is made of a material such as a sintered resin such as sintered vitrifide or phenol resin, or a metal sintered using various metals such as copper or tin.

  FIG. 6 is a process cross-sectional view showing a part of a method for manufacturing a semiconductor device in another embodiment of the present invention.

  4 is different from the embodiment shown in FIG. 4 in that a gold wire 50 having gold wire diameters 47, 48, and 49 different from φ18 μm to φ30 μm, respectively, is applied to different sizes of gold stud bumps by wire bonding equipment using a thermocompression bonding and ultrasonic method. Then, by using the capillaries 51, 52, 53 for that purpose, gold balls 55, 56, 57 of different sizes are generated at the tips of the gold wires, and gold stud bumps of different sizes are formed by heat-contacting the electrode pads. The following is equivalent to FIG.

  FIG. 7 is a plan view of the semiconductor chip 1 shown in FIG. 7A in the semiconductor chip of the semiconductor device according to the embodiment of the present invention, and is a graph showing the expansion due to the thermal expansion of the bump with respect to the distance D from the center of the semiconductor chip. Yes (FIG. 7B).

  First, second, and third central region area bumps 17 and 18 are formed in the region of the outermost peripheral edge bump 16 formed in the outermost peripheral region of the semiconductor device in the region closer to the center of the chip than the outermost peripheral region. , 19 or more than 1.1 / mm times the size of the 19 shows the grounds for greatly improving the connection reliability.

  The connection resistance value between the bump and the carrier substrate that determines the bump connection reliability is proportional to the distance D from the central portion of the semiconductor chip. For example, considering a ceramic carrier substrate and bump connection, the thermal expansion coefficient of the ceramic carrier substrate is 15 ppm / ° C., and since there is a temperature difference of 280 to 320 ° C. in production, the amount of elongation due to thermal expansion applied to the bump is 15 ppm. / ° C. × (distance D from the center of the semiconductor chip) × 280 to 320 ° C.

  FIG. 7A shows a simplified correlation graph between the size of the semiconductor chip 1 and the expansion rate (elongation amount due to expansion). In FIG. 7A, the size of the semiconductor chip 1 is the final form of the semiconductor chip 1 of most system LSIs because of the demand for miniaturization of the size of the semiconductor device due to the fine process, reliability, and production efficiency. The size ranges from 5 mm × 5 mm to 10 mm × 10 mm and the thickness ranges from 0.1 mm to 0.4 mm. Therefore, the distance D from the center of the semiconductor chip is shown up to 5 mm. In addition, since the electrode pad row interval for forming the electrode pad is practically 1 mm in consideration of the electrode pad size and the like, the horizontal axis is indicated by 1 mm. The largest difference in elongation between the rows where the electrode pads are adjacent is when the distance D from the center of the semiconductor chip 1 is 4 mm and 5 mm, and the maximum value is 19.2 um when the distance from the center of the semiconductor chip 1 is 4 mm. The ratio of the minimum value 21.0 um when the distance from the center of the semiconductor chip 1 is 5 mm is 1.1 times. Accordingly, the bump size was set to 1.1 times / mm in order to realize a bump size that makes the bump connection resistance of the semiconductor chip 1 uniform.

  As described above, the semiconductor device according to the present invention relates to the arrangement and size of the electrode pads and bumps in the semiconductor chip in which the semiconductor device is configured by flip chip connection, and sufficient flip chip connection reliability of the semiconductor device. The present invention relates to a semiconductor device having a structure for ensuring the performance.

  INDUSTRIAL APPLICABILITY The present invention is effective not only for a single semiconductor device but also for stacking semiconductor devices, and can be used for all semiconductor devices in which electrode pads are formed in a plurality of frames and bumps are formed there. It is.

1 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention. The block diagram of the semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the connection bump of the semiconductor device in one Embodiment of this invention The figure which shows the manufacturing method of the semiconductor device in one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device in one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device in one Embodiment of this invention. The characteristic view which shows the thermal expansion of the bump of the semiconductor device in one Embodiment of this invention Configuration diagram of a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 6 Wiring pattern 7 Sealing resin 8 Carrier substrate 9 External terminal 12 Outermost peripheral electrode pad 13 1st center area area electrode pad 14 2nd center area area electrode pad 15 3rd center area area electrode pad 16 Outermost peripheral bump 17 First central area area bump 18 Second central area area bump 19 Third central area area bump 30 Capillary 31 Gold wire

Claims (11)

In the semiconductor device in which electrode pads for connecting to the outside are arranged in a plurality of rows on the surface of the semiconductor chip, and bumps are formed on the electrode pads, the first is arranged in a frame in the peripheral region. A semiconductor device, wherein the size of the first bump on the electrode pad is larger than the size of the second bump on the second electrode pad arranged in the central region. The second electrode pads arranged in the central region are arranged in a grid or a plurality of rows of frames, and the sizes of the second bumps formed on the second electrode pads are all the same. The semiconductor device according to claim 1. The second electrode pads arranged in the central region are arranged in a plurality of rows of frames, and the size of the second bump formed on the second electrode pad is determined from the center of the semiconductor chip to the peripheral portion. 2. The semiconductor device according to claim 1, wherein the semiconductor device is increased in a region direction. 2. The semiconductor device according to claim 1, wherein a diameter of the first bump is 1.1 times / mm or more different from a diameter of the second bump. 4. The semiconductor device according to claim 3, wherein the size of the second bump is increased by 1.1 times / mm or more from the center of the semiconductor chip toward the peripheral region. 6. The semiconductor device according to claim 1, wherein the first electrode pad and the second electrode pad are changed in association with the size of the first bump and the size of the second bump. . The carrier substrate on which the semiconductor chip is mounted has a wiring pattern on the front surface and an external terminal electrically connected to the wiring pattern on the back surface, and the first bump and the second bump formed on the semiconductor chip are The sealing resin is filled so as to cover the bumps in the gap between the surface of the carrier substrate and the surface of the semiconductor chip, which is connected to the wiring pattern. The semiconductor device described. In the semiconductor device manufacturing method in which electrode pads for connecting to the outside on the surface of the semiconductor chip are arranged in a plurality of frames and bumps are formed on the electrode pads, the pads are arranged in a frame in the peripheral region. And a step of forming the size of the first bump on the first electrode pad larger than the size of the second bump on the second electrode pad arranged in the central region. Manufacturing method. The step of forming the size of the first bump larger than the size of the second bump uses the same gold wire diameter and discharges the gold wire from the capillary to the tip of the gold wire and discharges the current value condition. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the time is adjusted to generate gold balls of different sizes. In the step of forming the size of the first bump larger than the size of the second bump, the first gold wire is derived from the first capillary to generate the first bump, and the second capillary is used to generate the second bump. 9. The semiconductor according to claim 8, wherein the second gold bump is generated by deriving the first gold wire, and the diameter of the first gold wire is made larger than the diameter of the second gold wire. Device manufacturing method. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the first bump and the second bump are formed and then leveled at different heights.

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