US20090067248A1 - Program method of flash memory device - Google Patents

Program method of flash memory device Download PDF

Info

Publication number
US20090067248A1
US20090067248A1 US11/965,345 US96534507A US2009067248A1 US 20090067248 A1 US20090067248 A1 US 20090067248A1 US 96534507 A US96534507 A US 96534507A US 2009067248 A1 US2009067248 A1 US 2009067248A1
Authority
US
United States
Prior art keywords
voltage
program
channel regions
line
string
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/965,345
Other languages
English (en)
Inventor
Hee Youl Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, HEE YOUL
Publication of US20090067248A1 publication Critical patent/US20090067248A1/en
Priority to US12/903,968 priority Critical patent/US8238153B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Definitions

  • the present invention relates to a program method of a flash memory device and, more particularly, to a program method of a flash memory device, which minimizes program disturbance during a program operation.
  • a flash memory device is a type of non-volatile memory device in which stored data is not erased when a power supply is removed.
  • Data can be stored in or deleted from a flash memory device through a program operation or an erase operation.
  • the flash memory device can be classified as a NOR type or a NAND type depending on the shape of a memory cell array.
  • the NAND flash memory device is advantageous in that it can have a high level of integration compared with the NOR flash memory device.
  • a memory cell array of the NAND flash memory device and a program operation method are described below.
  • FIG. 1 is a circuit diagram illustrating a cell array of a conventional NAND flash memory device and a program operation method thereof.
  • the cell array of the NAND flash memory device includes a plurality of memory cell blocks.
  • Each cell block includes a plurality of cell strings (only two cell strings ST 1 and ST 2 are illustrated for convenience).
  • the cell strings are respectively connected to bit lines BL 1 and BL 2 .
  • the cell string ST 1 has a structure in which a drain select transistor DST, a plurality of memory cells CA 0 to CAn, and a source select transistor SST are connected in series.
  • the drain select transistor DST, included in each cell string has a drain connected to a corresponding bit line BL 1
  • the source select transistor SST included in each cell string, has a source connected to a common source line CSL.
  • the drain select transistors DST, included in the respective cell strings ST 1 and ST 2 have gates connected to each other, thereby forming a drain select line DSL.
  • the source select transistors SST, included in the respective cell strings ST 1 and ST 2 have gates connected to each other, thereby forming a source select line SSL.
  • the memory cells CA 0 to CAn and CB 0 to CBn have gates connected to each other, thereby forming word lines WL 0 to WLn.
  • the memory cells CAk and CBk, which share a word line (for example, WLk), are classified on a per page (PG) basis.
  • a program operation of the NAND flash memory device is executed on a per page basis.
  • the drain select line DSL is supplied with a drain select voltage, for example a power supply voltage Vcc
  • the source select line SSL is supplied with a ground voltage.
  • a program voltage is applied to a selected word line (for example WLk), and a pass voltage is applied to the remaining word lines. Under the above conditions, the program operation of memory cells sharing the selected word line WLk is executed.
  • the threshold voltage of a memory cell is raised by the program operation, and a logical value of stored data is classified according to the changed threshold voltage of the memory cell.
  • both the memory cells CAk and CBk sharing the selected word line WLk can be programmed, under certain circumstances both the memory cells CAk and CBk sharing the selected word line WLk may not be programmed according to stored data.
  • Different voltages are applied to bit lines connected to a corresponding string depending on which one of a to-be-programmed cell and a not-to-be-programmed cell is included in the string (a cell in which an erase state or a previous state is to be maintained).
  • a cell that should not be programmed is hereinafter referred to as a “program-inhibited cell.”
  • a ground voltage is applied to a bit line BL 1 connected to the string ST 1 , including a to-be-programmed cell (for example, CAk).
  • the ground voltage causes the voltage level of a channel region within the string ST 1 to drop to the level of the ground voltage. Consequently, a high potential is maintained between the word line WLk and the channel region, and electrons are injected from the channel region to a floating gate of the memory cell CAk by F-N tunneling, so that the threshold voltage of the memory cell is raised. Accordingly, the program operation is executed.
  • a program-inhibited voltage for example, a power supply voltage Vcc
  • Vcc a power supply voltage
  • the power supply voltage causes the channel region within the string ST 2 to be precharged to a level higher than OV (Vcc-Vth, where V is the threshold voltage of the drain select transistor). If the channel region is precharged, the drain select transistor DST is turned off and the channel region of the string ST 2 , including the program-inhibited cell CBk, is floated in a precharged state because Vgs (the potential between the gate and the source) of the drain select transistor DST is not greater than the threshold voltage.
  • a program method of storing 2-bit data or more in one memory cell has recently been developed.
  • threshold voltage distributions of the memory cell must be classified into four types and at least two program operations must be executed on one memory cell.
  • a first program operation for changing a lower bit to ‘0’ and a second program operation for changing an upper bit to ‘0’ must be executed.
  • the first and second program operations are generally performed sequentially from the first word line WL 0 to the last word line WLn.
  • the memory cells CB 0 to CBk ⁇ 1 disposed on the source select transistor (SST) side have already experienced the program operation.
  • the cells are classified into a program state or an erase state according to stored data.
  • a memory cell CBk+1 disposed on the drain select transistor (DST) side has not experienced the program operation, and is therefore maintained at an erase state. If a larger number of programmed cells exist on the source select transistor (SST) side, the potential between the word line and the channel region decreases due to electrons injected into the floating gate, so that a weak channel boosting phenomenon may occur.
  • channel boosting occurs with different intensities, which may result in a changed program characteristic. This phenomenon may happen not only in the program operation for storing 2-bit data, but also in a program method of storing 1-bit data.
  • the program operation can be performed by using an erase area self-boosting (EASB) method of generating channel boosting only in a channel region of memory cells, which are maintained at an erase state while being placed on the drain select transistor (DST) side in the selected word line WLk.
  • EASB erase area self-boosting
  • DST drain select transistor
  • the program operation can be performed by using a local self-boosting (LSB) method of generating channel boosting only in a channel region of memory cells, which share the selected word line WLk by turning off the memory cells WLk ⁇ 1 and WLk+1 adjacent to the selected word line WLk.
  • LSB local self-boosting
  • the program operation of the EASB method or the LSB method can have a good effect when memory cells disposed between the selected word line WLk and the drain select line DSL are in an erase state.
  • the sequence of the first and second program operations or the sequence of word lines is changed.
  • programmed cells may exist between the selected word line WLk and the drain select line DSL, it is difficult to obtain good program characteristics even with the program operation of the EASB method or the LSB method.
  • all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon in which the threshold voltage of program-inhibited cells is changed can be prevented.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having a string connected between a bit line and a common source line; applying a program-inhibited voltage in a state where channel regions within the string are not electrically connected to the bit line; applying a pass voltage to the word lines; applying a drain select voltage to the drain select line; and executing a program operation by applying a program voltage higher than the pass voltage to a selected one of the word lines.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having strings respectively connected between bit lines and a common source line; in a state where channel regions within the string are not electrically connected to the bit lines, applying a ground voltage to a first bit line connected to a first string including a to-be programmed memory cell and applying a program-inhibited voltage to a second bit line connected to a second string including a program-inhibited cell; applying a pass voltage to the word lines; applying a drain select voltage to the drain select line; and executing a program operation by applying a program voltage higher than the pass voltage to a selected one of the word lines.
  • Memory cells that share the word lines may be all turned on according to the pass voltage irrespective of a program state.
  • a level of the pass voltage applied to the selected word line may rise to a level of the program voltage.
  • a drain select transistor included in the first string may be turned on according to the drain select voltage, so that channel regions within the first string may be electrically connected to the first bit line.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having a string connected between a bit line and a common source line; applying a program-inhibited voltage to the bit line in a floating state where channel regions within the string are not electrically connected to the bit line; electrically connecting the channel regions in a state where the channel regions are not electrically connected to the bit line; applying a drain select voltage to the drain select line; and executing a program operation by applying a program voltage higher than a pass voltage to a selected one of the word lines.
  • the channel regions may be connected according to the pass voltage applied to each of the word lines.
  • a channel boosting phenomenon may be generated and a voltage of the channel regions may rise.
  • the program-inhibited voltage may be applied earlier than the pass voltage, the pass voltage may be applied earlier than the program-inhibited voltage, or the pass voltage and the program-inhibited voltage may be applied at the same time.
  • the drain select voltage may be applied after the program-inhibited voltage and the pass voltage are applied.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having strings respectively connected between bit lines and a common source line; in a floating state where channel regions within the string are not electrically connected to the bit lines, applying a ground voltage to a first bit line connected to a first string including a to-be programmed memory cell and applying a program-inhibited voltage to a second bit line connected to a second string including a program-inhibited cell; in a state where the channel regions are not connected to the bit lines, electrically connecting first channel regions of memory cells, included in the first string, and second channel regions of memory cells, included in the second string, respectively; in a state where the first and second channel regions are connected to each other, electrically connecting the first channel regions to the first bit line; and executing a program operation so that a threshold voltage of the to-be programmed memory cell rises.
  • the first channel regions may be connected to each other according to a pass voltage applied to each of the word lines, and the second channel regions may be connected to each other according to the pass voltage applied to each of the word lines. Since a channel boosting phenomenon is generated in each of the first and second channel regions by the pass voltage, a voltage of the first and second channel regions may rise.
  • the first channel regions may be connected to the first bit line as a drain select transistor of the first string is turned on according to a drain select voltage applied to the drain select line.
  • the drain select voltage may have the same level as that of the program-inhibited voltage.
  • the program-inhibited voltage may be applied before the first and second channel regions are connected to each other, the program-inhibited voltage may be applied after the first and second channel regions are connected to each other, or the first and second channel regions may be connected to each other at the same time when the program-inhibited voltage is applied. After the first and second channel regions are connected to each other and the program-inhibited voltage is applied, the first channel regions may be electrically connected to the first bit line.
  • a source select voltage for turning off a source select transistor may be applied to the source select line, and a positive voltage may be applied to a common source line.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having a string connected between a bit line and a common source line; applying a ground voltage to the bit line and a first voltage to the drain select line; applying a second voltage to the word lines so that memory cells are turned on; applying a pass voltage higher than the second voltage to the word lines while applying a program-inhibited voltage to the bit line; and executing a program operation by applying a program voltage higher than the pass voltage to a selected one of the word lines.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having strings respectively connected between bit lines and a common source line; applying a ground voltage to the bit lines and a first voltage to the drain select line; applying a second voltage to the word lines so that memory cells are turned on; applying a pass voltage higher than the second voltage to the word lines, a ground voltage to a first bit line connected to a first string including a to-be programmed memory cell, and a program-inhibited voltage to a second bit line connected to a second string including a program-inhibited cell; and executing a program operation by applying a program voltage higher than the pass voltage to a selected one of the word lines.
  • the memory cells may be all turned on according to the second voltage irrespective of a program state or an erase state. During execution of the program operation, a level of the pass voltage applied to the selected word line may rise to a level of the program voltage.
  • a drain select transistor included in the first string may be turned on according to the first voltage applied to the drain select line, so that channel regions within the first string may be electrically connected to the first bit line. Channel regions within the string may be electrically connected to one another according to the second voltage. The channel regions within the string may be disposed in a semiconductor substrate between the source select line and the drain select line, or in a semiconductor substrate under the word lines.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having a string connected between a bit line and a common source line; applying a ground voltage to the bit line and a first voltage to the drain select line; electrically connecting channel regions within the string; generating a channel boosting phenomenon in the channel regions, thereby raising a potential of the channel regions; and executing a program operation by applying a program voltage to a selected one of the word lines.
  • the channel regions may be connected to one another when memory cells that share the word lines are turned on according to a second voltage applied to the word lines.
  • the potential of the channel regions may rise in proportion to a value in which a voltage applied to the word lines rises as a drain select transistor that shares the drain select line is turned off according to a program-inhibited voltage applied to the bit line and the channel regions enter a floating state.
  • a program method of a flash memory device includes providing a memory device comprising a drain select line, a source select line, and word lines, and having strings connected between bit lines and a common source line; applying a ground voltage to the bit lines and a first voltage to the drain select line; connecting first channel regions of a first string of the strings, which includes a to-be programmed memory cell, and second channel regions of a second string of the strings, which includes a program-inhibited cell; applying a ground voltage to the first channel regions of the first string and generating a channel boosting phenomenon in the second channel regions of the second string, thereby raising a potential of the second channel regions; and executing a program operation by applying a program voltage to a selected one of the word lines.
  • Memory cells that share the word lines may be turned on according to a second voltage applied to the word lines, so that the first channel regions and the second channel regions are connected to each other. While a drain select transistor of the first string that shares the drain select line is turned on, the first channel regions may be electrically connected to the first bit line, so that the ground voltage is applied to the first channel regions. The potential of the channel regions may rise in proportion to a value in which a voltage applied to the word lines rises as a drain select transistor of the second string that shares the drain select line is turned off according to a program-inhibited voltage applied to the second bit line and the channel regions enter a floating state.
  • a source select voltage may be applied to the source select line so that a source select transistor is turned off and a positive voltage is applied to a common source line.
  • the channel regions within the string may be disposed in a semiconductor substrate between the source select line and the drain select line.
  • a program-inhibited voltage is applied to a bit line. Accordingly, all of the channel regions within the string can be precharged uniformly.
  • channel boosting is generated in the state where the channel regions are precharged uniformly. Accordingly, a channel boosting potential can be increased and the occurrence of program disturbance can be minimized.
  • the present invention can also be applied to a case where the sequence of program operations or word lines is changed in order to prevent a variation in the threshold voltage of neighboring cells due to an interference phenomenon during a program operation.
  • the present invention can also be applied to a case where memory cells located between a selected word line and a drain select line have been programmed.
  • channel boosting is generated not only in a channel region within a string, but also in the entire channel region. It is therefore possible to prevent the threshold voltage of program-inhibited cells from being changed due to hot electrons when channel boosting occurs in some regions.
  • FIG. 1 is a circuit diagram illustrating a cell array of a conventional NAND flash memory device and a program operation method thereof;
  • FIG. 2 is a circuit diagram illustrating a program method of a flash memory device according to an embodiment of the present invention
  • FIG. 3 is a waveform illustrating a program method of a flash memory device according to a first embodiment of the present invention
  • FIG. 4 is a cross-sectional view of memory cells CAk, CBk that share a k th word line in the circuit diagram of FIG. 2 ;
  • FIGS. 5A to 5D are cross-sectional views of a string in the circuit diagram of FIG. 2 ;
  • FIG. 6 is a waveform illustrating a program method of a flash memory device according to a second embodiment of the present invention.
  • FIG. 7 is a waveform illustrating a program method of a flash memory device according to a third embodiment of the present invention.
  • FIG. 8 is a waveform illustrating a program method of a flash memory device according to a fourth embodiment of the present invention.
  • FIG. 2 is a circuit diagram illustrating a program method of a flash memory device according to an embodiment of the present invention.
  • FIG. 3 is a waveform illustrating a program method of a flash memory device according to a first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of memory cells CAk, CBk that share a k th word line in the circuit diagram of FIG. 2 .
  • the flash memory device includes a memory cell array 210 , a voltage generator 220 , and page buffers 230 A and 230 B.
  • the memory cell array 210 includes a plurality of blocks, each of which includes a plurality of strings (only two cell strings ST 1 and ST 2 are illustrated for convenience).
  • a word line and a select line include tunnel insulating layers 305 , a floating gate 307 , dielectric layers 309 , and a control gate 311 ; all of which are stacked over a semiconductor substrate 301 .
  • Two select lines SSL and DSL are connected to the floating gate 307 and the control gate 311 since a hole is formed in the dielectric layer 309 .
  • Junction regions 315 J are formed in the semiconductor substrate 301 between the word lines and the select lines.
  • a bit line BL 1 is connected to a source 315 S formed at one side of a common source line CSL.
  • a bit line BL 2 is connected to a drain 315 D of the drain select line DSL.
  • the memory cell array 210 has the same memory cell array structure as that of FIG. 1 , and a description thereof will be omitted for simplicity.
  • the voltage generator 220 supplies operating voltages, necessary for a program operation, to the drain select line DSL, word lines WL 0 to WLn, and the source select line SSL.
  • Page buffers 230 A and 230 B are respectively connected to the drains of drain select transistors DST included in the strings ST 1 and ST 2 through the bit lines BL 1 and BL 2 .
  • the page buffers 230 A and 230 B apply a program-inhibited voltage (for example, a power supply voltage) or a ground voltage to the bit lines according to externally input data.
  • a program-inhibited voltage or a ground voltage is applied to the bit lines BL 1 and BL 2 according to externally input data.
  • the ground voltage is applied to the first bit line BL 1 connected to the first string ST 1 including the first memory cell CAk to be programmed, and a program-inhibited voltage Vpch is applied to the second bit line BL 2 connected to the second string ST 2 including the second memory cell CBk (that is, a program-inhibited cell).
  • a power supply voltage is applied to the common source line CSL and the ground voltage is applied to the source select line SSL.
  • the program-inhibited voltage Vpch is not transferred to a second channel region 313 B within the second string ST 2 . That is, even if the program-inhibited voltage Vpch is applied, the second channel region 313 B of the second string ST 2 is not precharged.
  • a pass voltage Vpass is applied to the word lines WL 0 to WLn so that all of the memory cells CA 0 to CAn and CB 0 to CBn, which are included in a block selected at the time of a program operation, are turned on.
  • the pass voltage Vpass refers to a voltage, which is applied to turn on memory cells connected to an unselected word line during a general program operation.
  • the pass voltage Vpass is applied to the word lines WL 0 to WLn, all of the memory cells CA 0 to CAn and CB 0 to CBn are turned on, and all of the channel regions are electrically connected to the semiconductor substrate 301 between the source select line SSL and the drain select line DSL within each of the strings ST 1 and ST 2 . Since the drain select line DSL and the source select line SSL are supplied with the ground voltage and the drain select transistor DST and the source select transistor SST are in a turn-off state, the first and second channel regions 313 A and 313 B of the strings ST 1 and ST 2 are supplied with the pass voltage Vpass in a floating state. Accordingly, a boosting phenomenon occurs in the strings ST 1 and ST 2 due to a capacitance coupling phenomenon, so that the voltage levels of the first and second channel regions 313 A and 313 B rise.
  • a drain select voltage is applied to the drain select line DSL.
  • the drain select voltage applied to the drain select line DSL may have the same level as that of the program-inhibited voltage applied to the second bit line BL 2 . If the drain select voltage is applied to the drain select line DSL, the drain select transistor DST of the first string ST 1 is turned on and, therefore, the first bit line BL 1 applied to the ground voltage is electrically connected to the first channel region 313 A of the first string ST 1 . Thus, the voltage level of the first channel region 313 A of the first string ST 1 drops to the level of the ground voltage.
  • the drain select transistor DST is not turned on due to a difference between Vgs (the potential between the gate and the source) and Vth (the threshold voltage of the drain select transistor).
  • the second channel region 313 B of the second string ST 2 is kept at a voltage level, which is raised by a boosting phenomenon. If the boosted voltage level of the second channel region 313 B is lower than the program-inhibited voltage, the drain select transistor DST of the second string ST 2 is turned on and the second channel region of the second string ST 2 is precharged to a predetermined level (i.e., the program-inhibited voltage which is the threshold voltage of the drain select transistor). The drain select transistor DST is then turned off.
  • a program operation is performed by applying a program voltage Vpgm to a selected word line WLk.
  • Vpgm program voltage
  • the first string ST 1 electrons are injected from the first channel region 313 A to the floating gate 307 of the memory cell CAk due to the potential between the word line WLk of the memory cell CAk and the first channel region 313 A, so that the threshold voltage rises. Consequently, the memory cell CAk is programmed.
  • the program voltage Vpgm is applied in the state where the drain select transistor DST of the second string ST 2 is turned off and the second channel region 313 B of the second string ST 2 is floated.
  • a boosting phenomenon occurs in the second channel region 313 B of the second string ST 2 due to the program voltage Vpgm, and the voltage of the second channel region 313 B rises additionally.
  • the program-inhibited cell CBk is not programmed and a program disturbance phenomenon is not generated.
  • the supply of the program voltage Vpgm applied for the program operation, the pass voltage Vpass, and the drain select voltage applied to the drain select line DSL is stopped in the remaining periods.
  • the supply of the program voltage Vpgm, the pass voltage Vpass, and the drain select voltage may be stopped sequentially. Though not shown in the drawing, the supply of the program-inhibited voltage Vpch and the voltage of the common source line CSL is also stopped.
  • a program verification operation for verifying whether the threshold voltage of the memory cell CAk has risen to a target voltage is performed. If, as a result of the verification, the threshold voltage of the memory cell CAk has risen to the target voltage, the program operation is finished. However, if, as a result of the verification, the threshold voltage has not risen to the target voltage, the program operation is performed again according to the above method while raising the level of the program voltage Vpgm step-by-step until the threshold voltage becomes the same as or higher than the target voltage.
  • the program-inhibited voltage is applied to the bit line before the pass voltage.
  • the program-inhibited voltage may be applied to the bit line in various ways.
  • FIG. 6 is a waveform illustrating a program method of a flash memory device according to a second embodiment of the present invention.
  • the pass voltage is applied to the word lines WL 0 to WLn before the program-inhibited voltage. Even in this case, a channel boosting phenomenon described with reference to FIG. 3 can be generated uniformly.
  • the program-inhibited voltage is applied before the drain select voltage
  • the program-inhibited voltage and the drain select voltage may be applied at the same time.
  • FIG. 7 is a waveform illustrating a program method of a flash memory device according to a third embodiment of the present invention.
  • the pass voltage and the program-inhibited voltage may be applied to the word lines WL 0 to WLn and the bit line, respectively, at the same time.
  • a channel boosting phenomenon described with reference to FIG. 3 can also be generated uniformly.
  • the pass voltage is applied simultaneously with a positive voltage applied to the common source line CSL.
  • the pass voltage may be applied before the positive voltage of the common source line CSL.
  • FIG. 8 is a waveform illustrating a program method of a flash memory device according to a fourth embodiment of the present invention.
  • a first voltage for turning on the drain select transistor DST is applied to the drain select line DSL, and a ground voltage is applied to the bit lines BL 1 and BL 2 and the word lines WL 0 to WLn. Even though the drain select transistor DST is turned on, the channel regions 313 A and 313 B are not precharged because the ground voltage is applied to the bit lines BL 1 and BL 2 .
  • the source select voltage of, for example, 0 V may be applied to the source select line SSL so that the source select transistor SST is turned off. Further, although the source select transistor SST is turned off, the leakage current to the common source line CSL can be generated. Accordingly, a common source voltage may be applied to the common source line CSL and the power supply voltage Vcc.
  • a second voltage is applied to the word lines WL 0 to WLn so that the memory cells CA 0 to CAn and CB 0 to CBk are turned on irrespective of a program state. If the memory cells CA 0 to CAn and CB 0 to CBk are turned on in the state where the drain select transistor DST is turned on and the ground voltage is applied to the bit lines BL 1 and BL 2 , the ground voltage is applied to the first channel region 313 A of the first string ST 1 and the second channel region 313 B of the second string ST 2 .
  • the program-inhibited voltage Vpch or the ground voltage is applied to the bit lines BL 1 and BL 2 according to externally input data.
  • the ground voltage is applied to the first bit line BL 1 connected to the first string ST 1 including the first memory cell CAk that is to be programmed
  • the program-inhibited voltage Vpch is applied to the second bit line BL 2 connected to the second string ST 2 including the second memory cell CBk (i.e., a program-inhibited cell).
  • the pass voltage Vpass higher than the second voltage is applied to the word lines WL 0 to WLn.
  • the second channel region 313 B is precharged to a level as much as Vpch-Vth (the threshold voltage of the drain select transistor) according to the program-inhibited voltage Vpch applied through the second bit line BL 2 . Since the second channel region 313 B is precharged, the drain select transistor DST is turned off, so that the second channel region 313 B enters a floating state. Further, since a boosting phenomenon is generated in response to the pass voltage Vpass, the voltage of the second channel region 313 B rises.
  • Vpch-Vth the threshold voltage of the drain select transistor
  • the second voltage applied to the word lines WL 0 to WLn in the second period T 2 causes all of the memory cells CB 0 to CBn to turn on, thereby connecting the channel regions 313 B of the memory cells CB 0 to CBn. Accordingly, a boosting phenomenon is generated uniformly in the channel regions 313 B of the memory cells CB 0 to CBn according to the pass voltage Vpass irrespective of a program state.
  • a program operation is performed by applying the program voltage Vpgm to the selected word line WLk.
  • the program voltage Vpgm is applied to the selected word line WLk.
  • the first string ST 1 electrons are injected from the first channel region 313 A to the floating gate 307 of the memory cell CAk due to the potential between the word line WLk of the memory cell CAk and the first channel region 313 A, so that the threshold voltage rises. Consequently, the memory cell CAk is programmed.
  • the program voltage Vpgm is applied in the state where the drain select transistor DST of the second string ST 2 is turned off and the second channel region 313 B of the second string ST 2 is floated.
  • a boosting phenomenon occurs additionally in the second channel region 313 B of the second string ST 2 according to the program voltage Vpgm, so that the voltage of the second channel region 313 B rises incidentally.
  • the potential between the word line WLk of the program-inhibited cell CBk and the second channel region 313 B further decreases. Consequently, the program-inhibited cell CBk is not programmed and a program disturbance phenomenon is not generated.
  • the supply of the program voltage Vpgm for the program operation, the pass voltage Vpass, and the drain select voltage applied for the drain select line DSL is stopped in the remaining periods.
  • the supply of the voltages may be stopped sequentially. Though not shown in the drawing, the supply of the program-inhibited voltage Vpch and the voltage applied to the common source line CSL is also stopped.
  • a program verification operation for verifying whether the threshold voltage of the memory cell CAk has risen to a target voltage is performed. If, as a result of the verification, the threshold voltage of the memory cell CAk has risen to the target voltage, the program operation is finished. However, if, as a result of the verification, the threshold voltage has not risen to the target voltage, the program operation is performed again according to the above method while raising the level of the program voltage Vpgm step-by-step until the threshold voltage becomes the same as or higher than the target voltage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
US11/965,345 2007-09-10 2007-12-27 Program method of flash memory device Abandoned US20090067248A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/903,968 US8238153B2 (en) 2007-09-10 2010-10-13 Program method of flash memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070091529A KR100885785B1 (ko) 2007-09-10 2007-09-10 플래시 메모리 소자의 프로그램 방법
KR2007-91529 2007-09-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/903,968 Division US8238153B2 (en) 2007-09-10 2010-10-13 Program method of flash memory device

Publications (1)

Publication Number Publication Date
US20090067248A1 true US20090067248A1 (en) 2009-03-12

Family

ID=40431664

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/965,345 Abandoned US20090067248A1 (en) 2007-09-10 2007-12-27 Program method of flash memory device
US12/903,968 Active US8238153B2 (en) 2007-09-10 2010-10-13 Program method of flash memory device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/903,968 Active US8238153B2 (en) 2007-09-10 2010-10-13 Program method of flash memory device

Country Status (4)

Country Link
US (2) US20090067248A1 (ja)
JP (1) JP2009070537A (ja)
KR (1) KR100885785B1 (ja)
CN (1) CN101388250B (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090141551A1 (en) * 2007-11-29 2009-06-04 Hynix Semiconductor Inc. Method for performing erasing operation in nonvolatile memory device
US20110110153A1 (en) * 2009-11-11 2011-05-12 Deepanshu Dutta Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
US20120020153A1 (en) * 2010-07-22 2012-01-26 Sang-Hyun Joo Nonvolatile Memory Devices with Highly Reliable Programming Capability and Methods of Operating Same
US8531886B2 (en) 2010-06-10 2013-09-10 Macronix International Co., Ltd. Hot carrier programming in NAND flash
US8842479B2 (en) 2011-10-11 2014-09-23 Macronix International Co., Ltd. Low voltage programming in NAND flash with two stage source side bias
US8947939B2 (en) 2010-09-30 2015-02-03 Macronix International Co., Ltd. Low voltage programming in NAND flash
TWI473098B (zh) * 2010-11-12 2015-02-11 Macronix Int Co Ltd 反及閘快閃記憶體之低電壓程式化
US9899093B2 (en) * 2016-05-17 2018-02-20 SK Hynix Inc. Semiconductor memory device having memory strings coupled to bit lines and operating method thereof
US10283202B1 (en) 2017-11-16 2019-05-07 Sandisk Technologies Llc Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming
CN112820329A (zh) * 2021-01-19 2021-05-18 长江存储科技有限责任公司 存储器的编程操作方法及装置

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101001449B1 (ko) * 2009-04-14 2010-12-14 주식회사 하이닉스반도체 불휘발성 소자의 독출 동작 방법
KR101662821B1 (ko) * 2010-06-16 2016-10-05 삼성전자주식회사 멀티-페이지 프로그램 방법, 그것을 이용한 불 휘발성 메모리 장치, 그리고 그것을 포함한 데이터 저장 시스템
KR20130091909A (ko) * 2012-02-09 2013-08-20 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 프로그램 방법과 이를 이용하는 데이터 처리 시스템
KR101979395B1 (ko) * 2012-05-08 2019-08-28 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR102011466B1 (ko) * 2012-08-29 2019-08-16 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법
KR20150004215A (ko) * 2013-07-02 2015-01-12 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법
KR102179845B1 (ko) 2014-02-03 2020-11-17 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 프로그램 방법
KR102210328B1 (ko) * 2014-02-12 2021-02-01 삼성전자주식회사 불휘발성 메모리 장치, 메모리 시스템 및 불휘발성 메모리 장치의 동작 방법
KR102320861B1 (ko) * 2015-10-06 2021-11-03 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
KR102323612B1 (ko) * 2015-11-23 2021-11-08 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
US9666282B1 (en) * 2016-05-03 2017-05-30 Micron Technology, Inc. Program inhibiting in memory devices
JP2017228325A (ja) * 2016-06-20 2017-12-28 ウィンボンド エレクトロニクス コーポレーション 不揮発性半導体記憶装置
KR102307063B1 (ko) 2017-06-26 2021-10-01 삼성전자주식회사 메모리 장치
US11488659B2 (en) * 2020-05-28 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and write method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570315A (en) * 1993-09-21 1996-10-29 Kabushiki Kaisha Toshiba Multi-state EEPROM having write-verify control circuit
US6614688B2 (en) * 2000-12-28 2003-09-02 Samsung Electronic Co. Ltd. Method of programming non-volatile semiconductor memory device
US6859394B2 (en) * 2001-03-06 2005-02-22 Kabushiki Kaisha Toshiba NAND type non-volatile semiconductor memory device
US7468918B2 (en) * 2006-12-29 2008-12-23 Sandisk Corporation Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323553B1 (ko) * 1997-02-03 2002-03-08 니시무로 타이죠 데이타오기입방지능력이있는비휘발성반도체메모리
JPH10223866A (ja) * 1997-02-03 1998-08-21 Toshiba Corp 半導体記憶装置
KR100562506B1 (ko) * 2003-12-01 2006-03-21 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
KR100645055B1 (ko) * 2004-10-28 2006-11-10 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570315A (en) * 1993-09-21 1996-10-29 Kabushiki Kaisha Toshiba Multi-state EEPROM having write-verify control circuit
US6614688B2 (en) * 2000-12-28 2003-09-02 Samsung Electronic Co. Ltd. Method of programming non-volatile semiconductor memory device
US6859394B2 (en) * 2001-03-06 2005-02-22 Kabushiki Kaisha Toshiba NAND type non-volatile semiconductor memory device
US7468918B2 (en) * 2006-12-29 2008-12-23 Sandisk Corporation Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7830717B2 (en) * 2007-11-29 2010-11-09 Hynix Semiconductor Inc. Method for performing erasing operation in nonvolatile memory device
US20090141551A1 (en) * 2007-11-29 2009-06-04 Hynix Semiconductor Inc. Method for performing erasing operation in nonvolatile memory device
USRE45520E1 (en) 2009-11-11 2015-05-19 Sandisk Technologies Inc. Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
US20110110153A1 (en) * 2009-11-11 2011-05-12 Deepanshu Dutta Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
US8169822B2 (en) 2009-11-11 2012-05-01 Sandisk Technologies Inc. Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
US8611148B2 (en) 2009-11-11 2013-12-17 Sandisk Technologies Inc. Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
US8531886B2 (en) 2010-06-10 2013-09-10 Macronix International Co., Ltd. Hot carrier programming in NAND flash
US8755232B2 (en) 2010-06-10 2014-06-17 Macronix International Co., Ltd. Hot carrier programming in NAND flash
US20120020153A1 (en) * 2010-07-22 2012-01-26 Sang-Hyun Joo Nonvolatile Memory Devices with Highly Reliable Programming Capability and Methods of Operating Same
US8947939B2 (en) 2010-09-30 2015-02-03 Macronix International Co., Ltd. Low voltage programming in NAND flash
TWI473098B (zh) * 2010-11-12 2015-02-11 Macronix Int Co Ltd 反及閘快閃記憶體之低電壓程式化
US8842479B2 (en) 2011-10-11 2014-09-23 Macronix International Co., Ltd. Low voltage programming in NAND flash with two stage source side bias
US9899093B2 (en) * 2016-05-17 2018-02-20 SK Hynix Inc. Semiconductor memory device having memory strings coupled to bit lines and operating method thereof
US10283202B1 (en) 2017-11-16 2019-05-07 Sandisk Technologies Llc Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming
CN112820329A (zh) * 2021-01-19 2021-05-18 长江存储科技有限责任公司 存储器的编程操作方法及装置

Also Published As

Publication number Publication date
US8238153B2 (en) 2012-08-07
US20110026330A1 (en) 2011-02-03
CN101388250A (zh) 2009-03-18
JP2009070537A (ja) 2009-04-02
KR100885785B1 (ko) 2009-02-26
CN101388250B (zh) 2012-02-08

Similar Documents

Publication Publication Date Title
US8238153B2 (en) Program method of flash memory device
US7733702B2 (en) Semiconductor memory device and method of erasing data therein
US7672166B2 (en) Method of programming in a non-volatile memory device and non-volatile memory device for performing the same
US7773429B2 (en) Non-volatile memory device and driving method thereof
US20050254309A1 (en) Program method of non-volatile memory device
US7751243B2 (en) Semiconductor memory device provided with MOS transistor having charge accumulation layer and control gate and data write method of NAND flash memory
US8917555B2 (en) Semiconductor device and operating method thereof
US8891314B2 (en) Semiconductor memory device and operating method thereof
US8625359B2 (en) Programming method of flash memory device
KR101264019B1 (ko) 반도체 장치의 동작 방법
US7672169B2 (en) Nonvolatile semiconductor memory and driving method thereof
US20130163345A1 (en) Semiconductor memory device and method of operating the same
US8050088B2 (en) Programming method of non-volatile memory device
US20120170376A1 (en) Semiconductor memory device and operating method thereof
JP2009205728A (ja) Ｎａｎｄ型不揮発性半導体メモリ
US7768833B2 (en) Method of programming non-volatile memory device
KR100525910B1 (ko) 플래시 메모리 셀의 프로그램 방법 및 이를 이용한 낸드플래시 메모리의 프로그램 방법
US8804426B2 (en) Methods of operating semiconductor device
US7990770B2 (en) Method of programming nonvolatile memory device
KR20090019718A (ko) Ｎａｎｄ형 불휘발성 반도체 메모리
KR20090052507A (ko) 플래시 메모리 소자의 동작 방법
KR20100013956A (ko) 플래시 메모리 소자 및 이의 프로그램 방법
KR20100016758A (ko) 플래시 메모리 장치의 프로그램 방법
KR20060070724A (ko) 플래쉬 메모리 소자의 프로그램 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, HEE YOUL;REEL/FRAME:020470/0545

Effective date: 20071220

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION