US20070032073A1 - Method of substrate processing and apparatus for substrate processing - Google Patents

Method of substrate processing and apparatus for substrate processing Download PDF

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Publication number
US20070032073A1
US20070032073A1 US10/571,256 US57125606A US2007032073A1 US 20070032073 A1 US20070032073 A1 US 20070032073A1 US 57125606 A US57125606 A US 57125606A US 2007032073 A1 US2007032073 A1 US 2007032073A1
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film
substrate processing
silicon compound
forming
chamber
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US10/571,256
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English (en)
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Yasuo Kobayashi
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Tokyo Electron Ltd
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Individual
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Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HASHIMOTO, YSUYOSHI, KOBAYASHI, YASUO
Publication of US20070032073A1 publication Critical patent/US20070032073A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

Definitions

  • This invention relates to a substrate processing method and a substrate processing apparatus for forming a metal silicide layer on a surface layer of a silicon material layer.
  • a silicidation method As a method for the reduction of resistance of the impurity diffusion layers, a silicidation method has been developed, wherein a metal silicide layer whose electric resistance is low is formed on surfaces of the impurity diffusion layers.
  • a silicidation method a thin metal film that can be silicided is deposited on the whole surface of a silicon material layer, and a thermal process (an annealing process for silicidation) is conducted so that a silicidation reaction is caused at a contact portion of the thin metal film and the silicon material layer in order to form a metal silicide.
  • a natural oxide film that has been formed on the surface of the silicon material layer has to be removed before the silicidation process.
  • a wet cleaning process using DHF(HF/H 2 O) or the like is adopted as a method of removing the natural oxide film.
  • the annealing process in order to sufficiently reduce the resistance of the metal silicide layer, the annealing process has to be conducted at 550° C. or higher.
  • a graph of FIG. 6 reveals the fact. From the graph, when a DHF cleaning process is adopted, it is found that the temperature has to be at 550° C. or higher in order to control the resistance of a cobalt silicide to about 60 ohm/sq. The reason is that a small amount of oxide film remains on the silicon material layer even after the DHF cleaning process and hence the silicidization needs more energy.
  • the object of this invention is to provide a substrate processing method and a substrate processing apparatus that need no high-temperature process for forming a metal silicide.
  • an invention according to claim 1 is a substrate processing method comprising the steps of: removing an oxide film, which has been formed on a surface layer of a silicon compound, by means of a reaction gas that has been activated; forming a metal film on the surface layer of the silicon compound after the oxide film has been removed; and forming a metal silicide on the surface layer of the silicon compound by means of a reaction of the metal film that has been formed thereon and the silicon compound.
  • An invention according to claim 2 has a feature that the step of forming a metal film on the surface layer of the silicon compound and the step of forming a metal silicide are conducted at the same time.
  • An invention according to claim 3 has a feature that the reaction of the metal film that has been formed and the silicon compound is conducted by an annealing process, and a feature that the reaction of the metal film that has been formed and the silicon compound is conducted after the step of forming a metal film on the surface layer of the silicon compound.
  • An invention according to claim 4 has a feature that the reaction gas is NF 3 .
  • An invention according to claim 5 has a feature that the step of activating the reaction gas is conducted by adding the reaction gas to an activating gas that has been activated by plasma.
  • An invention according to claim 6 has a feature that the activating gas is a mixed gas of N 2 and H 2
  • An invention according to claim 7 has a feature that the metal film is a Co film.
  • An invention according to claim 8 has a feature that the metal film is a Ni film.
  • An invention according to claim 9 has a feature that a step of forming an antioxidant film on the metal film that has been formed is further provided between the step of forming a metal film on the surface layer of the silicon compound and the step of forming a metal silicide.
  • An invention according to claim 10 has a feature that the antioxidant film is a TiN film.
  • An invention according to claim 11 is a substrate processing method for a MOS transistor having side walls between a gate region and a source region or a drain region, the method comprising the steps of: removing an oxide film, which has been formed on a surface layer of the gate region, the source region and the drain region, by means of a reaction gas that has been activated; forming a metal film on the surface layer of the gate region, the source region and the drain region after the oxide film has been removed; and forming a metal silidde on the surface layer of the gate region, the source region and the drain region, by annealing the gate region, the source region and the drain region on which the metal film has been formed.
  • An invention according to claim 12 is a substrate processing apparatus comprising: an oxide-film removing chamber for removing an oxide film, which has been formed on a surface layer of a silicon compound, by means of a reaction gas that has been activated; a metal-film forming chamber for forming a metal film on the surface layer of the silicon compound after the oxide film has been removed; and a conveyance chamber connected to the oxide-film removing chamber and the metal-film forming chamber, having a conveying apparatus that conveys an object to be processed between the oxide-film removing chamber and the metal-film forming chamber.
  • An invention according to claim 13 is a substrate processing apparatus comprising: a modified film forming chamber for forming a modified film by causing an oxide film, which has been formed on a surface layer of a silicon compound, to react with a reaction gas that has been activated; a modified film removing chamber for heating the silicon compound, on which the modified film has been formed, in order to evaporate the modified film and remove the same; a metal-film forming chamber for forming a metal film on the surface layer of the silicon compound after the modified film has been removed; and a conveyance chamber connected to the modified film forming chamber and the modified film removing chamber and the metal-film forming chamber, filled with a unreactive gas, having a conveying apparatus that conveys an object to be processed between the modified film forming chamber and the modified film removing chamber and the metal-film forming chamber.
  • FIG. 1 is a schematic sectional view showing a first step for conducting a process to a MOSFER by a substrate processing method according to an embodiment of the present invention
  • FIG. 2 is a schematic sectional view showing a second step for conducting the process to the MOSFET by the substrate processing method according to the embodiment of the present invention
  • FIG. 3 is a schematic sectional view showing a third step for conducting the process to the MOSFET by the substrate processing method according to the embodiment of the present invention
  • FIG. 4 is a schematic plan view showing a substrate processing apparatus according to an embodiment of the present invention.
  • FIG. 5 is a schematic sectional view showing a low-temperature processing chamber that conducts a low-temperature process in the embodiment of the present invention.
  • FIG. 6 is a graph showing a relationship between annealing temperature and resistance of cobalt silicide, in a case wherein a DHF cleaning process has been conducted and in a case wherein an NOR cleaning process has been conducted.
  • FIG. 1 is a schematic sectional view showing a MOSFET 11 to which a processing method of the present invention is applied.
  • the numeral sign 13 shows a silicon substrate.
  • a source 15 and a drain 17 which are impurities diffusion layers, are respectively provided on both lateral sides of the silicon substrate 13 .
  • a gate 21 consisting of a polycrystalline silicon is provided at an exposed portion of the silicon substrate between the source 15 and the drain 17 , via a gate oxide film 19 .
  • side walls 23 are provided at both lateral sides of the gate 21 .
  • the MOSFET 11 is processed by a substrate processing apparatus 41 as shown in FIG. 4 .
  • the substrate processing apparatus 41 has a conveyance chamber 43 at a central portion thereof.
  • a conveying apparatus for conveying a wafer is provided in the conveyance chamber 43 .
  • the inside of the conveying chamber 43 is filled with a unreactive atmosphere, for example a vacuum.
  • a unreactive atmosphere for example a vacuum.
  • a low-temperature processing chamber 47 is connected to the conveying chamber 43 , on the opposite side of the load-lock chamber 45 .
  • the low-temperature processing chamber 47 has a processing container 49 in which a vacuum can be created.
  • a stage 51 for placing the wafer W to be processed thereon is provided in the processing container 49 .
  • a plasma forming pipe 53 is provided at a ceiling wall of the processing container 49 . Through the plasma forming pipe 53 , an N 2 gas and an H 2 gas that have been activated by plasma are supplied into the processing container 49 .
  • a cover member 55 having a shape of an umbrella expanding downwardly is connected to a lower end of the plasma forming pipe 53 , so that the gases can flow efficiently toward the wafer W on the stage 51 .
  • a circular showerhead 59 having a large number of gas holes 57 is arranged on the inner side of the cover member 55 .
  • a communication pipe 61 is connected to the showerhead 59 .
  • An NF 3 gas is supplied to the showerhead 59 via the communication pipe 61 , and supplied into the cover member 55 through the large number of gas holes 57 .
  • the NF 3 gas collides with the active species of the N 2 gas and the H 2 gas in the cover member 55 , so that the NF 3 gas is also activated.
  • the activated NF 3 gas reacts with a natural oxide film that has been formed on the surface of the MOSFET on the wafer W, in order to form a modified film.
  • a heating chamber 71 is connected to the conveyance chamber 43 , adjacent to the low-temperature processing chamber 47 .
  • the wafer W is conveyed into the heating chamber 71 from the low-temperature processing chamber 47 via the conveyance chamber 43 .
  • the modified film which has been formed on the surface of the MOSFET on the wafer W in the low-temperature processing chamber 47 , is heated and evaporated, so that the wafer surface is cleaned.
  • a Co-sputtering chamber 81 is connected to the conveyance chamber 43 , on the opposite side of the heating chamber 71 with respect to the low-temperature processing chamber 47 .
  • a TiN-sputtering chamber 83 is also connected to the conveyance chamber 43 , adjacent to the Co-sputtering chamber 81 .
  • a Co film is formed on the cleaned surface of the MOSFET by means of sputtering.
  • a TiN film is formed on the Co film by means of sputtering.
  • An annealing chamber 85 is connected to the conveyance chamber 43 , adjacent to the TiN-sputtering chamber 83 . In the annealing chamber 85 , an annealing process is conducted to the wafer W on which the Co film has been formed.
  • a cooling chamber 87 is connected to the conveyance chamber 43 , adjacent to the heating chamber 71 .
  • the processed and heated wafer W is cooled.
  • the wafer doesn't react with a reactive atmosphere even when the wafer is conveyed into the reactive atmosphere.
  • a MOSFET as shown in FIG. 1 is conveyed into the low-temperature processing chamber 47 as shown in FIG. 4 . Then, in the low-temperature processing chamber 47 , the activated NF 3 gas and the natural oxide film are caused to react with each other, in order to form a modified film.
  • the cleaning method is referred to as NOR cleaning.
  • the MOSFET whose surface has been cleaned as described above is conveyed into the Co-sputtering chamber 81 .
  • the MOSFET whose surface has been cleaned is conveyed into the Co-sputtering chamber 81 . Then, as shown in FIG. 2 , a Co film 91 is formed on the surface. After that, the MOSFET is conveyed into the TiN-sputtering chamber 83 . Then, a TiN film 93 is formed on the surface. The TiN film 93 functions to prevent the Co film 91 from being oxidized.
  • the MOSFET is conveyed into the annealing chamber 85 .
  • the MOSFET is subjected to an annealing process at a low temperature (450 to 550° C.), so that a CoSi layer 95 is formed on each surface of the source 15 , the drain 17 and the gate 21 .
  • the Co—Si layer 95 functions as a mask at a cleaning process that is conducted thereafter, differently from a CoSi 2 layer described below.
  • the reason why the annealing process can be conducted at a low-temperature is as follows.
  • the resistance of the Cobalt silicide (Co—Si) can be reduced to 60 ohm/sq at an annealing temperature of 450 to 550° C.
  • an annealing process can be conducted at a much lower temperature than when a DHF cleaning is adopted.
  • thermal history of a high-temperature annealing process may have an adverse effect on distribution of impurities in the substrate.
  • the MOSFET is conveyed out through the conveyance chamber 43 and the load-lock chamber 45 , and conveyed into a metal cleaning chamber (not shown). Then, in the metal cleaning chamber, an SPM cleaning process is conducted, so that the remaining Co film and the remaining TiN film are removed.
  • the CoSi layer 95 that has been formed before cannot be dissolved by the SPM cleaning process.
  • the CoSi layer 95 is exposed on each surface of the gate 21 , the source 15 and the drain 17 .
  • the MOSFET is conveyed from the metal cleaning chamber into the second annealing chamber (not shown), and subjected to another annealing process at 650° C. or higher.
  • the CoSi layer 95 that has been formed on the surfaces of the source 15 , the drain 17 and the gate 21 is changed into a CoSi 2 layer 97 , which is a cobalt silicide layer achieving a lower resistance.
  • the natural oxide film formed on the surface layers of the gate 21 , the source 15 and the drain 17 of the MOSFET 11 is removed by the activated NF 3 gas, the Co film 91 is formed on the surfaces of the gate 21 , the source 15 and the drain 17 from which the natural oxide film has been removed, and the MOSFET is subjected to the low-temperature annealing process (450 to 550° C.), so that the Co film 91 and the silicon compound of the gate 21 , the source 15 and the drain 17 are caused to react with each other in order to form the metal silicide layer on the surface layer of the silicon compound.
  • the low-temperature annealing process 450 to 550° C.
  • the annealing process can be conducted at the lower temperature, and hence it can be prevented that thermal history of a high-temperature annealing process may have an adverse effect on distribution of impurities in the substrate.
  • the TiN film 93 is formed on the surface of the Co film 91 , it can be prevented that the Co film is oxidized after the Co film has been formed.
  • the above substrate processing apparatus 41 comprises: the low-temperature processing chamber 47 for causing the activated reaction gas to react with the oxide film formed on the surface layer of the silicon compound in order to form the modified film; the heating chamber 71 for heating the silicon compound on which the modified film has been formed and hence evaporating the modified film in order to remove the same; the Co-sputtering chamber 81 for forming the metal film on the surface of the silicon compound from which the modified film has been removed; and the conveyance chamber 43 connected to the low-temperature processing chamber 47 , the heating chamber 71 and the Co sputtering chamber 81 , having the conveying apparatus that conveys the wafer in the unreactive atmosphere between the low-temperature processing chamber 47 , the heating chamber 71 and the Co sputtering chamber 81 .
  • the removal of the oxide film, the forming of the Co film, and the forming of the Co silicide layer can be conducted efficiently. In addition, it can be prevented that undesired oxidization is caused during the above processes.
  • the step of forming the cobalt silicide is conducted.
  • the invention is not limited thereto.
  • the step of forming the Co film on the surfaces of the gate, the source and the drain and the step of forming the cobalt silicide may be conducted at the same time. In this case, the processes (steps) can be shortened, and hence the throughput can be improved.
  • the Co film is formed on the surfaces of the gate, the source and the drain of the MOSFET.
  • the invention is not limited thereto.
  • a Ni film may be formed thereon.
  • the Cobalt silidde is formed on the surfaces of the gate, the source and the drain of the MOSFET.
  • the invention is not limited thereto. This invention can be applied to any case wherein a metal silicide is formed on a surface layer of a silicon compound from which an oxide film has been removed.
  • the invention can be applied to an elevated source and/or an elevated drain.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US10/571,256 2003-09-19 2004-09-01 Method of substrate processing and apparatus for substrate processing Abandoned US20070032073A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003328226A JP2005093909A (ja) 2003-09-19 2003-09-19 基板処理方法及び基板処理装置
JP2003-328226 2003-09-19
PCT/JP2004/012647 WO2005029562A1 (ja) 2003-09-19 2004-09-01 基板処理方法及び基板処理装置

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US20070032073A1 true US20070032073A1 (en) 2007-02-08

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US (1) US20070032073A1 (enrdf_load_stackoverflow)
JP (1) JP2005093909A (enrdf_load_stackoverflow)
KR (1) KR100855767B1 (enrdf_load_stackoverflow)
CN (1) CN1853259A (enrdf_load_stackoverflow)
WO (1) WO2005029562A1 (enrdf_load_stackoverflow)

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Publication number Priority date Publication date Assignee Title
US20090209096A1 (en) * 2008-02-14 2009-08-20 Nam Yeal Lee Method for manufacturing semiconductor device having decreased contact resistance

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US7550381B2 (en) 2005-07-18 2009-06-23 Applied Materials, Inc. Contact clean by remote plasma and repair of silicide surface
JP2007214538A (ja) * 2006-01-11 2007-08-23 Renesas Technology Corp 半導体装置およびその製造方法

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US6114216A (en) * 1996-11-13 2000-09-05 Applied Materials, Inc. Methods for shallow trench isolation
US20010015261A1 (en) * 1997-06-04 2001-08-23 Tokyo Electro Limited Processing method and apparatus for removing oxide film
US20020137295A1 (en) * 2000-02-07 2002-09-26 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
US20020166256A1 (en) * 2000-01-28 2002-11-14 Samoilov Arkadii V. Process and apparatus for cleaning a silicon surface
US20030224617A1 (en) * 2002-06-04 2003-12-04 Eun-Kyung Baek Method of manufacturing a semiconductor device
US20040005408A1 (en) * 2000-03-30 2004-01-08 Hideki Kiryu Method of forming a dielectric film
US20040074515A1 (en) * 2002-10-22 2004-04-22 Jung-Wook Kim Method for cleaning a processing chamber and method for manufacturing a semiconductor device
US20050023640A1 (en) * 2003-06-17 2005-02-03 Jae-Hyoung Choi Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs and methods of forming the same

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TW209308B (en) * 1992-03-02 1993-07-11 Digital Equipment Corp Self-aligned cobalt silicide on MOS integrated circuits
JPH0738104A (ja) * 1993-07-22 1995-02-07 Toshiba Corp 半導体装置の製造方法
JPH0950973A (ja) * 1995-08-10 1997-02-18 Sony Corp シリサイド層の形成方法
JP4057198B2 (ja) * 1999-08-13 2008-03-05 東京エレクトロン株式会社 処理装置及び処理方法
EP1099776A1 (en) * 1999-11-09 2001-05-16 Applied Materials, Inc. Plasma cleaning step in a salicide process
KR100316721B1 (ko) * 2000-01-29 2001-12-12 윤종용 실리사이드막을 구비한 반도체소자의 제조방법

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US6114216A (en) * 1996-11-13 2000-09-05 Applied Materials, Inc. Methods for shallow trench isolation
US20010015261A1 (en) * 1997-06-04 2001-08-23 Tokyo Electro Limited Processing method and apparatus for removing oxide film
US20020166256A1 (en) * 2000-01-28 2002-11-14 Samoilov Arkadii V. Process and apparatus for cleaning a silicon surface
US20020137295A1 (en) * 2000-02-07 2002-09-26 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
US20040005408A1 (en) * 2000-03-30 2004-01-08 Hideki Kiryu Method of forming a dielectric film
US20030224617A1 (en) * 2002-06-04 2003-12-04 Eun-Kyung Baek Method of manufacturing a semiconductor device
US20040074515A1 (en) * 2002-10-22 2004-04-22 Jung-Wook Kim Method for cleaning a processing chamber and method for manufacturing a semiconductor device
US20050023640A1 (en) * 2003-06-17 2005-02-03 Jae-Hyoung Choi Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs and methods of forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090209096A1 (en) * 2008-02-14 2009-08-20 Nam Yeal Lee Method for manufacturing semiconductor device having decreased contact resistance
KR100920054B1 (ko) * 2008-02-14 2009-10-07 주식회사 하이닉스반도체 반도체 소자의 제조방법

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JP2005093909A (ja) 2005-04-07
CN1853259A (zh) 2006-10-25
KR20060090224A (ko) 2006-08-10
KR100855767B1 (ko) 2008-09-01

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