US20060226014A1 - Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing - Google Patents

Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing Download PDF

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Publication number
US20060226014A1
US20060226014A1 US11/103,917 US10391705A US2006226014A1 US 20060226014 A1 US20060226014 A1 US 20060226014A1 US 10391705 A US10391705 A US 10391705A US 2006226014 A1 US2006226014 A1 US 2006226014A1
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Prior art keywords
copper
ecp
deplating
openings
depositing
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Abandoned
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US11/103,917
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English (en)
Inventor
Yen Chuang
Huang-Yi Huang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US11/103,917 priority Critical patent/US20060226014A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUANG, YEN, HUANG, HUANG-YI
Priority to TW094137450A priority patent/TWI304225B/zh
Priority to CN200510126140A priority patent/CN100577890C/zh
Publication of US20060226014A1 publication Critical patent/US20060226014A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals

Definitions

  • the present invention relates generally to the electrochemical plating of film and more particularly to the electrochemical plating of copper-based metal layers during the fabrication of semiconductor devices.
  • ICs In the fabrication of integrated circuit (IC) semiconductor devices, substrate surface planarity is of critical importance. This is especially so as the scale of integration increases and the device features are reduced in size (e.g., sub-micron sized geometries).
  • ICs typically include metal layers that are used to interconnect individual device features thereof. Individual metal layers are typically isolated from each other by one or more insulating, dielectric material layers. Conductive interconnection features (e.g., trenches, vias, contacts, etc.) may be formed through the dielectric layers to provide the electrical access between successive conductive metal layers.
  • Copper and copper alloys are becoming a metal of choice in ICs as the metal layers and the interconnection structures that provide the electrical access between successive metal layers. Copper metal is used because its material properties feature lower resistance and improved electromigration performance compared to traditional metal materials such as aluminum and aluminum alloys. Copper and copper alloy layers (films) may be deposited by various methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD) and electrochemical plating (ECP). ECP for copper is preferred as a low cost and effective deposition method.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ECP electrochemical plating
  • a typical ECP process for copper involves the deposition of the metal conductive layer on the semiconductor substrate surface by contacting the wafer with an electrolyte solution and applying an electrochemical potential between electrodes of opposing polarities. During this process, copper ions plate out of the electrolyte solution and deposit onto the semiconductor substrate surface.
  • Copper is typically difficult to pattern and etch. Accordingly, copper features are typically formed using a damascene or dual damascene processes. In damascene processes, features such as vias and/or trenches, are defined within the dielectric material and subsequently filled with copper. The copper is deposited both into the opening in the dielectric feature and onto the surrounding field on top of the dielectric layer. The copper deposited onto the field may be subsequently removed to leave the copper filled feature formed within the dielectric or reduced, left on to become subsequently patterned and etched to become the next metal line layer of the IC device.
  • damascene processes features such as vias and/or trenches, are defined within the dielectric material and subsequently filled with copper.
  • the copper is deposited both into the opening in the dielectric feature and onto the surrounding field on top of the dielectric layer.
  • the copper deposited onto the field may be subsequently removed to leave the copper filled feature formed within the dielectric or reduced, left on to become subsequently patterned and etched to become the next metal line layer of the IC device.
  • the copper or copper alloy film deposited on the field (top of the dielectric) may be removed or planarized by using such methods as chemical mechanical polishing (CMP), plasma etching and or wet etching. Copper film removal and planarization difficulties are dependant upon the thickness uniformity of the copper layer.
  • CMP chemical mechanical polishing
  • the ECP processes may not produce copper metal layers of uniform thickness on top of the dielectric layer, particularly at and near the field locations above the copper-filled via and/or trench features within the dielectric layer. At these field locations, above the copper-filled vias and/or trenches, the deposited copper layer thickness is usually greater than the rest of the field due to an accelerated rate of copper deposition (ECP activity) at that particular field region. This accelerated deposition rate is attributed to excess electrochemical activity resulting from the copper deposition of the underlying via and/or trench features.
  • ECP activity accelerated rate of copper deposition
  • FIG. 1 illustrates the phenomena of non-uniform thickness deposition during the conventional ECP processing of areas over underlying via/trench type structures and areas with no underlying structures.
  • FIG. 1A is a cross-section of a portion of an IC semiconductor device 100 during fabrication.
  • the dielectric substrate 102 is shown with several damascene via/trench structures 104 having been fabricated into the dielectric substrate 102 .
  • These via/trench structures 104 have been fabricated so that subsequent ECP processing will deposit a copper based metal film both over the dielectric and into the structures 104 , filling them to completion with continued deposition to obtain a desired thickness of the copper based film onto the surrounding field on top of the dielectric substrate 102 .
  • the positions of the black dots 106 of the figure represent the relative concentration and distribution of the active accelerant component of the ECP chemicals that are used for the deposition process. It is noted that the distribution of the ECP accelerant 106 is fairly evenly distributed across the multi-dimensioned open surface of the dielectric 102 at the start of the actual ECP deposition, both across the top of the field and within the open damascene via/trench structures 104 .
  • FIG. 1B illustrates how the previously even distribution of the ECP accelerant 106 changes as the via/trench structures 104 are filled during the ECP process.
  • the ECP accelerants 106 that were located within these open structures migrate upwards.
  • the resultant migration of the ECP accelerants 106 produces a non-uniform distribution of the ECP accelerants 106 across the changing top surface of the open dielectric substrate 102 . It is this excess and uneven distribution of the ECP accelerant 106 during the ECP deposition processing that causes the non-uniform final thickness of a deposited copper-based film 108 .
  • FIG. 1C illustrates the final non-uniformity of the copper-based film 108 .
  • the final copper metal film 108 is shown on top of the dielectric substrate 102 .
  • the thickness of the copper film 108 over the dielectric substrate 102 areas without any underlying via/trench structures 104 is generally consistent and uniform.
  • the thickness of the copper film portion 110 located above the underlying, filled via/trench structures 104 is significantly thicker than the surrounding field areas without any underlying via/trench structures. This increased copper thickness region 110 corresponds to the locations of higher concentration, excess ECP accelerants 106 that were shown in FIG. 1B .
  • a macro copper layer uniformity problem may occur across the entire wafer substrate by which the IC devices are built upon.
  • ECP chemicals e.g., accelerants
  • the wafers may experience a thickness variation from wafer edge to wafer center.
  • the wafer center tends to experience a higher rate of copper metal deposition than the wafer edge, thus often producing wafers with the copper metal layers thicker at the center versus the edge.
  • FIG. 2 illustrates the typical relationship of final plating thickness, shown as the y-axis of the graph, as a function of the process wafer location, shown as the x-axis of the graph.
  • the graph shows the typical relationship with wafer center locations having an overall thicker final film thickness at locations at the wafer edge.
  • Typical IC fabrication flows commonly address the micro uniformity issue of the copper layer thickness non-uniformity on top of the field (dielectric) above the regions with light versus dense underlying via/trench features by simply depositing a thick copper film and then relying upon a long and carefully controlled metal planarization/etching process to obtain a flat final copper metal layer.
  • This method of deposition and planarization/etching undesirably adds processing time, wastes copper and is dependant upon tight controls of the planarization/etching processes.
  • waste and strict control requirements increase the ICs' fabrication costs and cycle times, as well as the decrease of IC production throughput rates.
  • the macro non-uniformity issue of the copper layer thickness across the wafer areas may be minimized with careful optimization and control of machine process parameters such as wafer revolution speed during the ECP process.
  • the varying of process parameters during the ECP deposition may undesirably induce film composition variations within the final copper metal film.
  • the varying values of the process parameters may be more difficult to monitor and control.
  • the desired level of the copper layer thickness, uniformity, planarity and composition may still not be obtained.
  • the copper metal layer deposited during the ECP processing is planar as formed, i.e., it includes uniform thickness both over the various topography and fields of the individual IC devices, as well as throughout the semiconductor wafer that includes many IC devices.
  • this disclosure provides an improved method and process for the ECP deposition of copper metal layers upon a semiconductor substrate surface such that the final deposited film is planar across the semiconductor wafer.
  • accelerants are deposited onto the top surface of a dielectric substrate having one or more damascene structures, and the dielectric substrate submerged in an electrolyte. Copper is then deposited onto the top surface of the dielectric substrate and filling the one or more damascene structures and coating a portion of the dielectric substrate. The copper is then deplated for a predetermined period of time to remove an excess portion of the accelerant and a portion of the copper to yield a uniform top surface of the copper.
  • FIGS. 1A through 1C are cross-sectional views of a conventional IC device during conventional ECP deposition processing.
  • FIG. 2 is a graph showing the relationship between final plating thickness and the plating location within the processed wafer for the conventional ECP deposition process.
  • FIGS. 3A through 3D are cross-sectional views of an IC device during ECP deposition processing using the ideal method and process in accordance with one embodiment of the present invention.
  • FIG. 4 is a flow chart summarizing the ECP method and processing steps as described in accordance with an embodiment of the present invention.
  • the present disclosure provides a detailed description of an improved method and process for the ECP deposition of copper metal layers upon a semiconductor substrate surface such that the final deposited film is planar and uniform both at the micro uniformity scale, across the various topography and fields of the individual IC devices, as well the macro uniformity scale, across the semiconductor wafer of many IC devices.
  • the improved method and process implements a deplating step, in-situ within the ECP processing, such that excess chemical accelerant components of the ECP chemistry are removed leaving a uniform, even distribution of the components to provide a uniform, planar final deposited copper metal film layer.
  • FIG. 3 illustrates an exemplary method and process of the present invention.
  • FIG. 3A is a cross-section of a portion of an IC semiconductor device 300 during fabrication.
  • the dielectric substrate 302 is shown with several damascene via/trench structures 304 having been fabricated into the dielectric substrate 302 .
  • These via/trench structures 304 have been fabricated so that subsequent ECP processing will deposit a copper based metal film both into the structures 304 , filling them to completion with continued deposition to obtain a desired thickness of the copper based film onto the surrounding field on top of the dielectric substrate 302 .
  • the positions of the black dots 306 of the figure represent the relative concentration and distribution of the active accelerant component of the ECP chemicals that are used for the deposition process.
  • the accelerants are advantageously included as a component of the ECP electrolyte solution.
  • Accelerants commonly used in the ECP of copper include bis(3-sulfopropyl)disulfide, mercapto-propane-sulfonic acid and thiourea. It is noted that the distribution of the ECP accelerant 306 is fairly evenly distributed across the multi-dimensioned open surface of the dielectric 302 at the start of the actual ECP deposition, both across the top of the field and within the open damascene via/trench structures 304 .
  • FIG. 3B illustrates how the previously even distribution of the ECP accelerant 306 changes as the via/trench structures 304 are filled during the ECP process.
  • the accelerants 306 that were located within these open structures migrate upwards.
  • the resultant migration of the ECP accelerants produces a non-uniform distribution of the accelerants 306 across the changing top surface of the open dielectric substrate 302 . It is this excess of accelerants over the via/trench structures 304 and the uneven distribution of ECP accelerant 306 during the ECP deposition processing that would cause the non-uniform final thickness of the deposited copper-based film 308 using conventional methods.
  • the method and process of the present invention provides for the ECP deposition to halt at or near the point at which the damascene via/trench structures 304 are filled and before the bulk deposition of the copper film onto the remaining field areas of the open dielectric substrate 302 begins.
  • a thin copper metal film 308 may be depositing on the remaining field of the open dielectric substrate 302 (shown in FIG. 3B ) during the ECP deposition step that fills the via/trench structures 304 in various exemplary embodiments.
  • the deplating process is now performed onto the partially ECP deposited copper metal film 308 .
  • the deplating process of the present disclosure is performed in-situ, utilizing the same equipment and hardware of the ECP process.
  • a reverse polarity of the power applied in the ECP process is applied to the same ECP electrodes thereby causing the ECP's electrolysis process to operate in reverse for a pre-determined short period of time.
  • the copper metal film 308 which is already deposited onto the wafer's dielectric substrate 302 is removed until the deplating process is stopped.
  • the copper film 308 is preferentially removed from portions where the initial deposition produced localized thick portions of the copper film 308 .
  • the reversed chemical electrolysis also removes the non-uniformly distributed excess chemical accelerants 306 off of the deposited copper metal film substrate 308 .
  • the accelerants are preferably removed from regions of high concentration such as over via/trench structures 304 .
  • the remaining accelerants 306 are distributed fairly evenly and uniformly across the open surface of the exposed copper metal film 308 , both over the top of the field areas without underlying damascene via/trench structures 304 and field areas with underlying damascene via/trench structures.
  • the disclosed deplating process and equipment configurations and parameters are changed and controlled by the ECP process tools as a process recipe step.
  • the disclosed deplating process is fairly short in time, e.g. 3 to 12 seconds and typically approximately 5 seconds, much shorter than that of the combined total ECP copper metal film deposition times. Other deplating times may be used in other exemplary embodiments.
  • FIG. 3C illustrates a cross-sectional view after completion of the deplating step.
  • the deplated copper metal film 308 both over the top of the field areas without underlying damascene via/trench structures 304 and field areas over underlying damascene via/trench structures, is now a little thinner than prior to the deplating process.
  • the remaining ECP accelerants 306 are now distributed fairly evenly and uniformly across the entirety of the open surface of the exposed, deplated copper metal film 308 .
  • the method of the present invention further provides for the completion of the ECP copper metal film deposition to obtain the final copper thickness required by the IC devices.
  • the ECP equipment and hardware is once again changed via a similar process recipe step as created for the deplating process.
  • the previously reversed polarity of the power to the ECP electrodes is now changed back to the original power configuration so that the ECP copper deposition onto the production wafers resumes.
  • the ECP copper deposition then continues to obtain the required final thickness of the copper metal film which may vary according to device requirements.
  • the second ECP step may be used to plate about 3000-7000 A of copper in one embodiment, but other thicknesses may be used in other exemplary embodiments.
  • 3D shows the cross-sectional view of the IC device after completion of the ECP final deposition process step with a planar final copper metal film 308 of uniform thickness. It is the even, uniformly distributed accelerants 306 left on the surface of the partially deposited copper metal film 308 after the deplating process step shown as FIG. 3C that enables the subsequent ECP copper metal film deposition to provide a final film with a uniform thickness.
  • the final planar, uniform thickness exists both over the top of the field areas without underlying damascene via/trench structures 304 and field areas with underlying damascene via/trench structures, i.e., the same height with respect to the substrate 302 .
  • FIG. 4 is a flow chart summarizing the process sequence of an exemplary method of the present invention.
  • the first process step 402 of the present method is the ECP deposition of the copper metal film that stops about when the open damascene via/trench structures of the dielectric substrate layer are filled. Once the damascene structures are filled, the ECP deposition process is stopped.
  • the next process step is the deplating process step 404 .
  • the deplating process step 404 is then performed for a pre-determined deplating time.
  • the deplating process time may have been previously determined through process and device characterization studies to determine the required and optimum performance of the combined ECP deposition and deplating steps.
  • the second ECP deposition step 406 is performed.
  • the completed second ECP deposition step 406 provides the final copper metal film of a planar layer with uniform thickness over all areas of the dielectric field, both above underlying damascene via/trench structures and over areas without any underlying damascene via/trench structures.
  • These three sequential steps 402 , 404 and 406 may be considered as a single ECP process method comprising a deposition step and an in-situ deplating step, followed by another deposition step.
  • the method and process of using a deplating process step between ECP deposition steps greatly improves the planarity and thickness uniformity of plated copper metal films deposited upon the semiconductor substrate surface. This improvement of planarity and thickness uniformity can be obtained on substrates with various levels of topography and underlying structures. Such planarity and uniformity improvements resolve both micro and macro uniformity issues experienced using conventional ECP processes.
  • Implementation of the method and process of the present invention may eliminate the requirement to define and maintain special varying process, tool parameters which could lead to inconsistent and difficult-to-control ECP film compositions.
  • the method and process of the present invention may also eliminate the requirements for special, separate planarization/etch processing upon an overly thick deposited ECP film just to obtain film planarity.
  • the method and process of the present invention may be easily implemented within existing ECP fabrication tools and tool configurations of existing and future IC fabrication facilities and operations. Various, commercially available tools may be used.
  • the disclosed method and process may be defined as a single new ECP process recipe within the ECP fabrication tools as a recipe comprised of at least 3 individual sequential steps: deposition, deplating and deposition. It is noted that for further planarization optimizations and future process and devices technologies, the disclosed method and process may be incorporated into embodiments where multiple deposition, deplating process steps, combinations and sequences may be required.
  • the implementation of the disclosed method and structure will improve IC device quality, yields and production throughput rates. Such improvements will translate into significant cost improvements for a given production facility to maintain highly competitive cost and output advantages over other manufacturers of similar product devices and technologies. As result, advanced device generations and performance levels may be more easily achieved and attained.
  • the present disclosure provides several examples to illustrate the flexibility of how the disclosed method and deplating process may be used and implemented.
  • the above disclosure provides different embodiments or examples for implementing different features of the disclosure. Specific examples of components and processes are described and are intended to be exemplary and not intended to limit the disclosure from that described in the claims.

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  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US11/103,917 2005-04-11 2005-04-11 Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing Abandoned US20060226014A1 (en)

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US11/103,917 US20060226014A1 (en) 2005-04-11 2005-04-11 Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing
TW094137450A TWI304225B (en) 2005-04-11 2005-10-26 Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing
CN200510126140A CN100577890C (zh) 2005-04-11 2005-11-30 改善电镀薄膜均匀性的电镀方法

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Cited By (2)

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KR20150093620A (ko) * 2014-02-07 2015-08-18 어플라이드 머티어리얼스, 인코포레이티드 반도체 기판들을 위한 전해 플레이팅 방법들
US10154598B2 (en) 2014-10-13 2018-12-11 Rohm And Haas Electronic Materials Llc Filling through-holes

Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN108103566B (zh) * 2017-12-28 2021-02-02 上海冠众光学科技有限公司 一种金属薄膜退镀方法及系统
TWI688746B (zh) * 2018-12-17 2020-03-21 揚博科技股份有限公司 基板厚度檢測與自動修正系統及基板厚度檢測與自動修正方法

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CN1283848C (zh) * 2001-10-16 2006-11-08 新光电气工业株式会社 小直径孔镀铜的方法
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US6524461B2 (en) * 1998-10-14 2003-02-25 Faraday Technology Marketing Group, Llc Electrodeposition of metals in small recesses using modulated electric fields
US6432821B1 (en) * 2000-12-18 2002-08-13 Intel Corporation Method of copper electroplating
US6881318B2 (en) * 2001-07-26 2005-04-19 Applied Materials, Inc. Dynamic pulse plating for high aspect ratio features
US6989328B2 (en) * 2003-02-17 2006-01-24 Nec Electronics Corporation Method of manufacturing semiconductor device having damascene interconnection

Cited By (3)

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Publication number Priority date Publication date Assignee Title
KR20150093620A (ko) * 2014-02-07 2015-08-18 어플라이드 머티어리얼스, 인코포레이티드 반도체 기판들을 위한 전해 플레이팅 방법들
KR102169555B1 (ko) * 2014-02-07 2020-10-23 어플라이드 머티어리얼스, 인코포레이티드 반도체 기판들을 위한 전해 플레이팅 방법들
US10154598B2 (en) 2014-10-13 2018-12-11 Rohm And Haas Electronic Materials Llc Filling through-holes

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CN100577890C (zh) 2010-01-06
CN1847464A (zh) 2006-10-18
TWI304225B (en) 2008-12-11
TW200636803A (en) 2006-10-16

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