US20060043476A1 - Junction varactor with high q factor - Google Patents

Junction varactor with high q factor Download PDF

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Publication number
US20060043476A1
US20060043476A1 US10/711,140 US71114004A US2006043476A1 US 20060043476 A1 US20060043476 A1 US 20060043476A1 US 71114004 A US71114004 A US 71114004A US 2006043476 A1 US2006043476 A1 US 2006043476A1
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United States
Prior art keywords
gate
well
junction varactor
diffusion region
ion diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/711,140
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English (en)
Inventor
Ching-Hung Kao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
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United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US10/711,140 priority Critical patent/US20060043476A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAO, CHING-HUNG
Priority to CNB2005100702062A priority patent/CN100391010C/zh
Publication of US20060043476A1 publication Critical patent/US20060043476A1/en
Priority to US11/760,789 priority patent/US7378327B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0811—MIS diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0808—Varactor diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/93—Variable capacitance diodes, e.g. varactors

Definitions

  • the present invention relates generally to a varactor, and more particularly, to a PN-junction varactor having improved quality factor (Q factor).
  • a varactor is, essentially, a variable voltage capacitor.
  • the capacitance of a varactor when within its operating parameters, decreases as a voltage applied to the device increases.
  • Varactors are typically employed in voltage-controlled oscillators (VCOs) where a frequency of an oscillator is controlled by an applied current or voltage. In such instances, the VCOs are used when a variable frequency is required, or when a signal needs to be synchronized to a reference signal.
  • VCOs voltage-controlled oscillators
  • varactors Numerous varactors have been developed and are employed in integrated circuit technologies, for example, PN-diodes, Schottky diodes or MOS-diodes as a varactor in bipolar, CMOS and BiCMOS technologies.
  • PN-diodes PN-diodes
  • MOS-diodes MOS-diodes
  • two varactor structures are most frequently used: the PN-junction varactor and the MOS varactor.
  • the PN-junction varactor is predominantly used in LC oscillators. Both these structures can be implemented using standard CMOS processes.
  • a prior art PN diode varactor is illustrated in a cross-sectional view.
  • a substrate 10 includes an N-well 12 , and a plurality of isolation structures 14 , such as field oxide layer or shallow trench isolation (STI), on surfaces of the N-well 12 and the substrate 10 .
  • the isolation structures 14 define a plurality of predetermined regions on the N-well 12 to form at least an N-type doping region 16 and a P-type doping region 18 , thus completing a diode structure having a PN junction.
  • a depletion region occurs in the PN junction of the diode and acts as a dielectric, so that the N-type doping region 16 and the P-type doping region 18 separated by the dielectric form an equivalent capacitor.
  • a width of the depletion region varies to change the equivalent capacitance of the varactor.
  • a prior art MOS varactor is illustrated in a cross-sectional view.
  • the prior art MOS varactor is formed on an N-well 22 .
  • the prior art MOS varactor includes a polysilicon gate structure 26 serving as an anode of the MOS varactor, a gate oxide layer 28 between the gate structure 26 and the N-well 22 , and two N + doped regions 24 on both sides of the gate structure 26 , wherein the N + doped regions 24 , which are implanted in the N-well 22 , serve as a cathode of the MOS varactor.
  • N type lightly doped drain regions 25 are also provided.
  • the main drawback of the prior art PN junction varactor as set forth in FIG. 1 is a low maximum to minimum capacitance ratio and small quality factor (Q factor).
  • the MOS varactor does not suffer on this account, with a high maximum to minimum capacitance ratio of roughly four to one for a typical 0.25 ⁇ m CMOS process.
  • the MOS varactor's ratio increases in deep submicron processes due to the thinner gate oxide used.
  • the MOS varactor's transition from maximum to minimum capacitance is abrupt. This gives a MOS varactor a small, highly non-linear voltage control range.
  • a junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the first ion diffusion region serving as an anode of the junction varactor; and a second ion diffusion region with a second conductivity type located in the ion well at the other side of the gate finger, the second ion diffusion region serving as a cathode of the junction varactor.
  • the gate of the junction varactor is biased to a gate voltage V G that is not equal to 0 volt.
  • FIG. 1 is a cross-sectional schematic diagram illustrating a prior art PN junction varactor
  • FIG. 2 is a cross-sectional schematic diagram illustrating a prior art MOS varactor
  • FIG. 3 is a schematic top view showing the layout of a junction varactor in accordance with one preferred embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional diagram showing the junction varactor along line AA of FIG. 3 ;
  • FIGS. 5-8 are schematic cross-sectional diagrams showing the process steps for making the junction varactor as set forth in FIG. 4 according to this invention.
  • FIG. 9 is a schematic cross-sectional diagram showing a junction varactor according to another preferred embodiment of this invention.
  • FIG. 3 is a schematic top view showing the basic layout of a junction varactor 80 in accordance with one preferred embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional diagram showing the junction varactor 80 along line AA of FIG. 3
  • the junction varactor 80 is formed on an N-well 100 , which may be formed on a commercially available P type silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the N-well 100 is electrically isolated by shallow trench isolation (STI) 200 .
  • STI shallow trench isolation
  • the substrate is an SOI substrate
  • the STI 200 reaches down to a buried oxide layer and thus renders the N-well 100 in a floating status.
  • the junction varactor 80 further comprises an elongated gate finger 101 lying across the N-well 100 , and a gate finger 102 situated at one side of the gate finger 101 .
  • the gate finger 102 which overlies the N-well 100 , is arranged substantially in parallel with the gate finger 101 .
  • Both of the gate finger 101 and gate finger 102 have vertical sidewalls, on which spacers 101 a and 102 a are formed.
  • the gate finger 101 and gate finger 102 may be formed of polysilicon or metals.
  • a gate dielectric layer 101 b and a gate dielectric layer 102 b are provided under the gate fingers 101 and 102 , respectively.
  • a P + doping region 112 which serves as an anode of the junction varactor 80 , is formed in the N-well 100 between the gate fingers 101 and 102 .
  • the P + doping region 112 is contiguous with P-type lightly doped drains (PLDD) 113 that extend laterally to under the spacers 101 a and 102 a.
  • PLDD P-type lightly doped drains
  • an N + doping region 114 is provided in the N-well 100 .
  • An N-type lightly doped drain (NLDD) 121 that is merged with the N + doping region 114 extends laterally to the gate 101 .
  • an N + doping region 116 is provided in the N-well 100 .
  • an NLDD 122 that is merged with the N + doping region 116 extends laterally to the gate 102 .
  • the N+doping region 114 is electrically coupled to the N + doping region 116 by interconnection, and together serves as a cathode of the junction varactor 80 . Furthermore, to reduce sheet resistance of the varactor 80 , a salicide layer 103 is optionally provided on the exposed surface of the P + doping region 112 , the N + doping region 114 , and the N + doping region 116 .
  • the present invention junction varactor has a lower resistance because there is no STI formed between the anode and cathode of the varactor. Therefore, the present invention junction varactor has a higher Q factor and better performance.
  • the gate fingers 101 and 102 are preferably biased to a pre-selected voltage V G .
  • the pre-selected voltage V G is a positive voltage such as V CC .
  • the positive voltage provided to gate fingers 101 and 102 results in accumulated electrons in the channel regions that are located under the gate fingers 101 and 102 , thereby further reducing resistance of the varactor 80 .
  • the capacitance of the junction varactor may be tuned in an extended tuning range.
  • FIG. 5 illustrates the first step used in forming the inventive junction varactor.
  • a substrate (not explicitly shown) is provided, on which an N-well 100 is formed by any method known in the art, for example, ion implantation.
  • the N-well 100 is isolated by STI (not shown).
  • an insulation layer (not explicitly shown) such as thermally grown gate oxide layer is formed on the surface of the N-well 100 .
  • a layer of polysilicon is deposited over the insulation layer, and then patterned to form gate structures 101 and 102 using conventional lithographic and dry etching processes.
  • the deposition of the polysilicon layer may be fulfilled by conventional LPCVD.
  • the gates may be made of metals.
  • an NLDD ion implantation process is carried out to dope ions such as arsenic into the N-well 100 at one side of the gate 101 and at one side of the gate 102 , thereby forming an NLDD region 121 and NLDD region 122 .
  • a PLDD ion implantation process is carried out to dope ions such as boron into the N-well 100 in the area between the gate 101 and the gate 102 , thereby forming a PLDD region 113 .
  • spacers 101 a and 102 a are formed on sidewalls of the gates 101 and 102 , respectively.
  • an N + ion implantation process is carried out to dope a high dosage of ions such as arsenic into the N-well 100 at one side of the gate 101 and at one side of the gate 102 , thereby forming N + region 114 and N + region 116 .
  • the junction varactor 80 as set forth in FIG. 4 is produced.
  • FIG. 9 depicts a schematic cross-sectional view of junction varactor 800 according to another preferred embodiment of this invention.
  • the junction varactor 800 is formed on a P-well 200 .
  • the junction varactor 800 comprises an elongated gate finger 201 lying across the P-well 200 , and a gate finger 202 situated at one side of the gate finger 201 .
  • the gate finger 202 which overlies the P-well 200 , is arranged substantially in parallel with the gate finger 201 .
  • Both of the gate finger 201 and gate finger 202 have vertical sidewalls, on which spacers 201 a and 202 a are formed.
  • the gate finger 201 and gate finger 202 may be formed of polysilicon or metals.
  • a gate dielectric layer 201 b and a gate dielectric layer 202 b are provided under the gate fingers 201 and 202 , respectively.
  • An N + doping region 212 which serves as an anode of the junction varactor 800 , is formed in the P-well 200 between the gate fingers 201 and 202 .
  • the N + doping region 212 is contiguous with N-type lightly doped drains (NLDD) 213 that extend laterally to under the spacers 201 a and 202 a.
  • NLDD N-type lightly doped drains
  • a P + doping region 214 is provided in the P-well 100 .
  • a P-type lightly doped drain (PLDD) 221 that is merged with the P + doping region 214 extends laterally to the gate 201 .
  • PLDD lightly doped drain
  • a P + doping region 216 is provided in the P-well 200 .
  • a PLDD 222 that is merged with the P + doping region 216 extends laterally to the gate 202 .
  • the P + doping region 214 is electrically coupled to the P + doping region 216 by interconnection, and together serves as a cathode of the junction varactor 800 .
  • a salicide layer 203 is optionally provided on the exposed surface of the N + doping region 212 , the P + doping region 214 , and the P+doping region 216 .
  • the gate fingers 201 and 202 are preferably biased to a pre-selected voltage V G .
  • the pre-selected voltage V G is V SS .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
US10/711,140 2004-08-27 2004-08-27 Junction varactor with high q factor Abandoned US20060043476A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/711,140 US20060043476A1 (en) 2004-08-27 2004-08-27 Junction varactor with high q factor
CNB2005100702062A CN100391010C (zh) 2004-08-27 2005-05-10 结可变电容
US11/760,789 US7378327B2 (en) 2004-08-27 2007-06-10 Method for fabricating a junction varactor with high Q factor

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US10/711,140 US20060043476A1 (en) 2004-08-27 2004-08-27 Junction varactor with high q factor

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070184594A1 (en) * 2005-11-15 2007-08-09 Nowak Edward J Schottky barrier diode and method of forming a schottky barrier diode
US20110062555A1 (en) * 2009-09-14 2011-03-17 International Business Machines Incorporated Semiconductor structure having varactor with parallel dc path adjacent thereto
US20110186933A1 (en) * 2008-01-31 2011-08-04 Texas Instruments Incorporated Schottky diode with silicide anode and anode-encircling p-type doped region
US20120043590A1 (en) * 2010-08-17 2012-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Linear-Cap Varactor Structures for High-Linearity Applications

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US20080191285A1 (en) * 2007-02-09 2008-08-14 Chih-Hsin Ko CMOS devices with schottky source and drain regions
US20090072891A1 (en) * 2007-09-14 2009-03-19 Srinivas Perisetty Varactor-based charge pump
US7741187B2 (en) * 2007-09-20 2010-06-22 Chartered Semiconductor Manufacturing, Ltd. Lateral junction varactor with large tuning range
US8405123B2 (en) * 2008-10-27 2013-03-26 National Semiconductor Corporation Split-gate ESD diodes with elevated voltage tolerance
CN101834134B (zh) * 2009-03-12 2012-03-21 中芯国际集成电路制造(上海)有限公司 提高金属-氧化物半导体变容二极管的品质因子的方法
CN102412291B (zh) * 2011-03-04 2013-09-11 上海华虹Nec电子有限公司 锗硅BiCMOS工艺中的可变电容及制造方法
CN102244000B (zh) * 2011-06-23 2016-07-06 上海华虹宏力半导体制造有限公司 半导体器件、变容二极管及其形成方法
CN104576765B (zh) * 2014-12-26 2018-01-26 上海集成电路研发中心有限公司 防漏光存储电容结构及其制备方法

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US6882029B1 (en) * 2003-11-27 2005-04-19 United Microelectronics Corp. Junction varactor with high Q factor and wide tuning range
US7056761B1 (en) * 2003-03-14 2006-06-06 National Semiconductor Corporation Avalanche diode with breakdown voltage controlled by gate length

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US7053465B2 (en) * 2000-11-28 2006-05-30 Texas Instruments Incorporated Semiconductor varactor with reduced parasitic resistance
US7081663B2 (en) * 2002-01-18 2006-07-25 National Semiconductor Corporation Gate-enhanced junction varactor with gradual capacitance variation
CN1237615C (zh) * 2002-02-10 2006-01-18 台湾积体电路制造股份有限公司 一种二极管结构及其静电放电防护电路
US6576974B1 (en) * 2002-03-12 2003-06-10 Industrial Technology Research Institute Bipolar junction transistors for on-chip electrostatic discharge protection and methods thereof
JP4636785B2 (ja) * 2003-08-28 2011-02-23 パナソニック株式会社 半導体装置及びその製造方法
US6949440B2 (en) * 2003-11-11 2005-09-27 United Microelectronics Corp. Method of forming a varactor
US6943399B1 (en) * 2004-04-13 2005-09-13 United Microelectronics Corp. Varactor and differential varactor

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Publication number Priority date Publication date Assignee Title
US6576958B2 (en) * 2001-01-03 2003-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process
US7056761B1 (en) * 2003-03-14 2006-06-06 National Semiconductor Corporation Avalanche diode with breakdown voltage controlled by gate length
US6882029B1 (en) * 2003-11-27 2005-04-19 United Microelectronics Corp. Junction varactor with high Q factor and wide tuning range

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070184594A1 (en) * 2005-11-15 2007-08-09 Nowak Edward J Schottky barrier diode and method of forming a schottky barrier diode
US8377810B2 (en) * 2005-11-15 2013-02-19 International Business Machines Corporation Schottky barrier diode and method of forming a Schottky barrier diode
US8642453B2 (en) 2005-11-15 2014-02-04 International Business Machines Corporation Schottky barrier diode and method of forming a Schottky barrier diode
US20110186933A1 (en) * 2008-01-31 2011-08-04 Texas Instruments Incorporated Schottky diode with silicide anode and anode-encircling p-type doped region
US8129814B2 (en) * 2008-01-31 2012-03-06 Texas Instruments Incorporated Schottky diode with silicide anode and anode-encircling P-type doped region
US20110062555A1 (en) * 2009-09-14 2011-03-17 International Business Machines Incorporated Semiconductor structure having varactor with parallel dc path adjacent thereto
US8232624B2 (en) 2009-09-14 2012-07-31 International Business Machines Corporation Semiconductor structure having varactor with parallel DC path adjacent thereto
US8598683B2 (en) 2009-09-14 2013-12-03 International Business Machines Corporation Semiconductor structure having varactor with parallel DC path adjacent thereto
US20120043590A1 (en) * 2010-08-17 2012-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Linear-Cap Varactor Structures for High-Linearity Applications
CN102376781A (zh) * 2010-08-17 2012-03-14 台湾积体电路制造股份有限公司 半导体可变电容器组件及变容器组件
US8373248B2 (en) * 2010-08-17 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Linear-cap varactor structures for high-linearity applications

Also Published As

Publication number Publication date
US7378327B2 (en) 2008-05-27
CN100391010C (zh) 2008-05-28
US20070232010A1 (en) 2007-10-04
CN1741285A (zh) 2006-03-01

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