US20050285676A1 - Slew rate enhancement circuitry for folded cascode amplifier - Google Patents

Slew rate enhancement circuitry for folded cascode amplifier Download PDF

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US20050285676A1
US20050285676A1 US10/878,849 US87884904A US2005285676A1 US 20050285676 A1 US20050285676 A1 US 20050285676A1 US 87884904 A US87884904 A US 87884904A US 2005285676 A1 US2005285676 A1 US 2005285676A1
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transistor
input
coupled
current
source
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Mark Jones
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Texas Instruments Inc
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Texas Instruments Inc
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Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JONES, MARK A.
Priority to PCT/US2005/023698 priority patent/WO2006005040A2/fr
Publication of US20050285676A1 publication Critical patent/US20050285676A1/en
Priority to US11/401,492 priority patent/US7342450B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H03F3/45094—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3022—CMOS common source output SEPP amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3066—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor the collectors of complementary power transistors being connected to the output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/372—Noise reduction and elimination in amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45248—Indexing scheme relating to differential amplifiers the dif amp being designed for improving the slew rate

Definitions

  • the present invention relates generally to improving the slew rate of a folded cascode amplifier while also maintaining low noise operation.
  • the “slew rate” of an amplifier is a measure of how fast the amplifier can charge up a large capacitor that is connected to an output conductor of the amplifier in response to a large, rapid increase or decrease (such as a step function increase or decrease) of the input voltage applied to the amplifier.
  • the slew rate is a measure of the maximum rate of change of the output voltage in response to an input step function, and is normally, but not necessarily, limited by charging the compensation capacitors.
  • a high slew rate generally is a desirable characteristic of an amplifier, especially an operational amplifier, and especially a high-speed CMOS operational amplifier.
  • One technique for increasing the slew rate of an amplifier is to increase the bias current of the input stage, but that has a tendency to increase the bandwidth of the amplifier and leads to a need to increase the compensation capacitance of the amplifier to improve circuit stability, which tends to decrease the slew rate.
  • increasing the input stage bias current requires a commensurate increase in the second stage current (to avoid turning the second stage off, which in turn adds to the total input referred noise.
  • FIG. 1 is a schematic diagram of an operational amplifier including a conventional simple folded cascode input stage 19 A which drives a class AB output stage 20 A similar to the one described in the above-mentioned Monticelli U.S. Pat. No. 4,570,128.
  • FIG. 2 is a schematic diagram of another operational amplifier including a conventional complementary folded cascode input stage 19 which drives a class AB output stage 20 that is slightly different than class AB output stage 20 A shown in FIG. 1 .
  • the present invention increases a slew rate of a folded-cascode operational amplifier by applying a large, rapid transition of an input signal between the bases of a first input transistor having a gate coupled to a first input voltage (Vin+), and emitter coupled to a tail current source ( 15 ), and a collector ( 12 ) coupled to a collector of a first current source transistor and an emitter of a first cascode transistor and a second input transistor having a base coupled to a second input voltage (Vin ⁇ ), and emitter coupled to the tail current source ( 15 ), and a collector ( 11 ) coupled to a collector of a second current source transistor and an emitter of a second cascode transistor and amplifying an excess of tail current steered by the first input transistor into the input of a first slew boost circuit ( 13 ) over a current flowing in a first current source transistor and applying the amplified excess current to boost the slew rate of a class AB output stage in accordance with
  • invention provides an operational amplifier including a differential input stage ( 19 ) and a class AB output stage ( 20 ).
  • the differential input stage includes a first input transistor (MP 9 ) having a gate coupled to a first input voltage (Vin+), a source coupled to a tail current source ( 15 ), and a drain ( 12 ) coupled to a drain of a first current source transistor (MN 4 ) and a source of a first cascode transistor (MN 3 ), and a second input transistor (MP 10 ) having a gate coupled to a second input voltage (Vin ⁇ ), a source coupled to the tail current source ( 15 ), and a drain ( 11 ) coupled to a drain of a second current source transistor (MN 5 ) and a source of a second cascode transistor (MN 6 ).
  • the class AB output stage includes a pull-up transistor (MP 0 ) and current mirror circuitry (MP 1 ,MP 3 ,MP 4 ,MP 14 ) coupling a gate of the pull-up transistor (MP 0 ) to a drain of the second cascode transistor (MN 6 ) and a pull-down transistor (MN 1 ) including a gate coupled to a drain of the first cascode transistor (MN 3 ).
  • a second slew boost circuit ( 14 ) includes an input coupled to the drain ( 11 ) of the second input transistor (MP 10 ) and an output coupled to the source ( 12 ) of the first cascode transistor (MN 3 ) for amplifying an excess of tail current steered by the second input transistor (MP 10 ) into the input of the second slew boost circuit ( 14 ) over a current flowing in the second current source transistor (MN 5 ) and applying the amplified excess to boost the slew rate of the class AB output stage in accordance with a second polarity of the difference between the first (Vin+) and second (Vin ⁇ ) input voltages.
  • the first slew boost circuit ( 13 ) includes a first current mirror circuit including a first control transistor (MN 91 ) having a source connected to a first reference conductor (GROUND) and a gate and drain coupled to the input of the first slew boost circuit and to a gate of a first current mirror output transistor (MN 92 ) having a source connected to the first reference voltage (GROUND) and a drain coupled to the source of the second cascode transistor (MN 6 ), and wherein the second slew boost circuit ( 14 ) includes a second current mirror circuit including a second control transistor (MN 0 ) having a source connected to the first reference voltage (GROUND) and a gate and drain coupled to the input of the second slew boost circuit and to a gate of a second current mirror output transistor (MN 2 ) having a source connected to the first reference voltage (GROUND) and a drain coupled to the source of the first cascode transistor (MN 3 ).
  • an operational amplifier in another embodiment, includes a differential input stage ( 19 A) and a class AB output stage ( 20 A).
  • the differential input stage ( 19 A) includes a first input transistor (MP 9 ) having a gate coupled to a first input voltage (Vin+), a source coupled to a tail current source ( 15 ), and a drain ( 12 ) coupled to a drain of a first current source transistor (MN 4 ) and a source of a first cascode transistor (MN 3 ), and a second input transistor (MP 10 ) having a gate coupled to a second input voltage (Vin ⁇ ), a source coupled to the tail current source ( 15 ), and a drain ( 11 ) coupled to a drain of a second current source transistor (MN 5 ) and a source of a second cascode transistor (MN 6 ).
  • the class AB output stage ( 20 A) includes a pull-up transistor (MP 0 ), a pull-down transistor (MN 1 ), a first bias transistor (MN 11 ) coupled between a gate of the pull-up transistor (MP 0 ) and a gate of the pull-down transistor (MN 1 ), the gate of the pull-down transistor (MN 1 ) being coupled to a drain of the first cascode transistor (MN 3 ).
  • a first slew boost circuit ( 13 A) includes an input coupled to the drain ( 12 ) of the first input transistor (MP 9 ) and an output coupled by means of a current mirror coupling circuit (MP 18 ,MP 19 ,MP 20 ,MP 21 ) to the gate of the pull-up transistor (MP 0 ) for amplifying an excess of tail current steered into the input of the first slew boost circuit ( 13 A) over a current flowing in the first current source transistor (MN 4 ) and applying the amplified excess to boost the slew rate of the class AB output stage in accordance with a first polarity of the difference between the first (Vin+) and second (Vin ⁇ ) input voltages.
  • a second slew boost circuit ( 14 A) includes an input coupled to the drain ( 11 ) of the second input transistor (MP 10 ) and an output coupled by means of a cascode coupling transistor (MN 18 ) to the gate of the pull-down transistor (MN 1 ) for amplifying an excess of tail current steered into the input of the second slew boost circuit ( 14 ) over a current flowing in the second current source transistor (MN 5 ) and applying the amplified excess to boost the slew rate of the class AB output stage in accordance with a second polarity of the difference between the first (Vin+) and second (Vin ⁇ ) input voltages.
  • the first slew boost circuit ( 13 A) includes a first current mirror circuit including a first control transistor (MN 91 ) having a source connected to a first reference conductor (GROUND) and a gate and drain coupled to the input of the first slew boost circuit and to a gate of a first current mirror output transistor (MN 92 ) having a source connected to the first reference voltage (GROUND) and a drain coupled to an input of the current mirror coupling circuitry (MP 18 ,MP 19 ,MP 20 ,MP 21 ) and wherein the second slew boost circuit ( 14 A) includes a second current mirror circuit including a second control transistor (MN 0 ) having a source connected to the first reference voltage (GROUND) and a gate and drain coupled to the input of the second slew boost circuit and to a gate of a second current mirror output transistor (MN 2 ) having a source connected to the first reference voltage (GROUND) and a drain coupled to a source of the cascode coupling
  • FIG. 1 is a schematic diagram of a prior art operational amplifier having a simple folded cascode input stage driving a class AB output stage
  • FIG. 2 is a schematic diagram of a prior art operational amplifier having a complementary folded cascode input stage driving a class AB output stage.
  • FIG. 3 is a schematic diagram of an operational amplifier similar to that of prior art FIG. 2 and further including slew boost circuitry in accordance with one embodiment of the invention.
  • FIG. 4 is a schematic diagram of an operational amplifier similar to that of prior art FIG. 1 and further including slew boost circuitry in accordance with another embodiment of the invention.
  • FIG. 5 is a diagram of the output voltage Vout of the described embodiment of the invention for the purpose of comparing the performance of the invention with the performance of the prior art.
  • FIG. 6 is a schematic diagram of an operational amplifier similar to that of prior art FIG. 2 , and including the slew boost circuitry shown in FIG. 4 .
  • FIG. 7 is schematic diagram of an embodiment of the invention implemented using bipolar transistors rather than field effect transistors to provide a bipolar integrated circuit version of the amplifier shown in FIG. 4 .
  • the two current mirrors are activated by “excess current” from the input transistors of the input stage caused by a large, rapid transition of the input voltage applied to gates of the input transistors.
  • a current source e.g., transistor MN 4 or transistor MN 5
  • the corresponding current mirror turns on proportionally, and therefore drives amplified “excess” current into or out of a compensation capacitor to provide increased slewing speed.
  • the transition between normal operation and slewing operation is stable because the excess slewing current is proportional to the differential input voltage in the transition region.
  • operational amplifier 10 includes a conventional complementary folded cascode input stage 19 which drives a class AB output stage 20 .
  • the input stage 19 includes a pair of P-channel input transistors MP 9 and MP 10 having their sources connected to a tail current source 15 .
  • the gates of input transistors MP 9 and MP 10 are connected to Vin+ and Vin ⁇ .
  • the drain of input transistor MP 10 is connected by conductor 11 to the drain of a N-channel current source transistor MN 5 , the source of which is connected to ground.
  • the drain of input transistor MP 9 is connected by conductor 12 to the drain of a N-channel current source transistor MN 4 , the source of which is connected to ground.
  • the gates of current source transistors MN 4 and MN 5 are connected by conductor 22 to the gate and drain of a N-channel current mirror control transistor MN 8 , the source of which is also connected to ground.
  • a current source 21 connected between VDD and conductor 22 supplies a control current through transistor MN 8 .
  • the drains of current source transistors MN 4 and MN 5 are connected to the sources of N-channel cascode transistors MN 3 and MN 6 , respectively.
  • the gates of cascode transistors MN 3 and MN 6 are connected to a reference voltage VB 1 .
  • the drain of cascode transistor MN 3 is connected by conductor 17 to the gate of N-channel output transistor MN 1 of class AB output stage 20 .
  • the drain of cascode transistor MN 6 is connected by conductor 16 to the drain of a P-channel cascode transistor MP 14 and the gates of P-channel current mirror transistors MP 4 and MP 3 , the sources of which are connected to VDD.
  • the drain of current source transistor MP 3 is connected to the source of a P-channel cascode transistor MP 1 , the drain of which is connected by conductor 18 to the gates of a P-channel output transistor MP 0 of class AB output stage 20 .
  • the gates of cascode transistors MP 1 and MP 14 are connected to a reference voltage VB 2 .
  • Class AB output stage 20 includes the above-mentioned output transistors MP 0 and MN 1 , the drains of which are connected by conductor 27 to the output terminal on which the output voltage Vout is produced and also to the junction between one terminal of each of compensation capacitors C 0 and C 1 .
  • the source of output transistor MP 0 is connected to VDD, and the source of output transistor MN 1 is connected to ground.
  • the other terminal of compensation capacitor C 0 is connected to conductor 18 , and the other terminal of compensation capacitor C 1 is connected to conductor 17 .
  • Class AB output stage 20 also includes a N-channel transistor MN 11 having its source connected to conductor 17 and its drain connected to conductor 18 .
  • the gate of transistor MN 11 is connected to the junction between a current source 23 and the drain of a N-channel diode-connected transistor MN 12 .
  • the source of transistor MN 12 is connected to the gate and drain of a diode-connected N-channel transistor MN 13 , the source of which is connected to ground.
  • Current source 23 has another terminal connected to VDD.
  • a P-channel transistor MP 11 has its source connected to conductor 18 and its drain connected to conductor 17 .
  • the gate of transistor MP 11 is connected to the junction between one terminal of a current source 24 and the gate and drain of a P-channel diode-connected transistor MP 16 .
  • the source of transistor MP 16 is connected to the gate and drain of a P-channel diode-connected transistor MP 15 , the source of which is connected to VDD.
  • Current source 24 has another terminal connected to ground.
  • the circuitry including transistors MN 11 , MN 12 , MN 13 , MP 11 , MP 15 and MP 16 and current sources 23 and 24 operates to maintain a DC bias voltage between conductors 17 and 18 so as to cause essentially the same quiescent current to flow through output transistors MP 0 and MN 1 .
  • the use of the basic Montecelli class AB output stage as shown in FIGS. 3 and 4 is exemplary, but various other class AB output stages also could be used in conjunction with the present invention.
  • operational amplifier 10 further includes a negative slew boost circuit 13 including a current mirror which includes a diode-connected N-channel transistor MN 91 having its source connected to ground and its gate and drain connected to conductor 12 and also to the gate of a N-channel current source transistor MN 92 having its source connected to ground and its drain connected to conductor 11 .
  • Operational amplifier 10 also includes a positive slew boost circuit 14 including a current mirror that includes a diode-connected N-channel transistor MN 0 having its source connected to ground and its gate and drain connected to conductor 11 and also to the gate of a N-channel current source transistor MN 2 having its source connected to ground and its drain connected to conductor 12 .
  • a positive slew boost circuit 14 including a current mirror that includes a diode-connected N-channel transistor MN 0 having its source connected to ground and its gate and drain connected to conductor 11 and also to the gate of a N-channel current source transistor MN 2 having its source connected to ground and its drain connected to conductor 12 .
  • negative slew boost as indicated in block 13 in FIG. 3 refers to boosting the slew rate of Vout on conductor 27 during a negative-going transition of Vout
  • the magnitude of tail current 15 of complementary folded cascode input stage 19 is larger than the magnitude of the current flowing in either of current source transistors MN 4 and MN 5 .
  • the magnitude of tail current source 15 needs to be greater than the magnitude of the constant currents flowing through current source transistors MN 5 and MN 4 , and also needs to be less than twice the magnitude of that constant current, because otherwise, the steady-state operation would leave cascode transistors MN 3 and MN 6 with zero current.
  • tail current 15 is steered through one of input transistors MP 9 or MP 10 into the drain of one of current source transistors MN 5 or MN 4 , respectively.
  • there will be an “excess” of current over the amount of current that either of transistors MN 5 or MN 4 is capable of sinking. That excess current will flow through one of diode-connected transistors MN 91 or MN 0 , depending on the polarity of the input signal (Vin Vin+minus Vin ⁇ ) being applied to input stage 19 .
  • the excess current is “gained up” by the current mirror of the corresponding one of negative slew boost circuit 13 and positive slew boost circuit 14 in accordance with the ratio of the channel-width-to-channel-length ratio of MN 0 to that of MN 2 or the ratio of the channel-width-to-channel-length ratio of MN 91 to that of MN 92 .
  • the gained-up result is used as a slew boost current.
  • a relatively constant voltage difference is maintained between conductors 17 and 18 as pull-up transistor MP 0 is turned on “harder” and pull-down transistor MN 1 is turned on “less hard”.
  • Vout is increasing while the voltage on conductor 18 is decreasing, compensation capacitor C 0 is being discharged while compensation capacitor C 1 is being charged.
  • the limited amount of constant current flowing in transistors MN 4 and MN 5 sharply limits the amount of current available to accomplish the required discharging of compensation capacitor C 0 and the required charging of compensation capacitor C 1 , and therefore also sharply limits the slew rates of class AB output stage 20 .
  • the channel-width-to-channel-length ratio of transistors MN 4 and MN 5 must be increased to increase the constant current in each transistor so that more current is available for charging and discharging compensation capacitors C 0 and C 1 in order to provide faster slew rates. But that substantially increases the operating noise level of prior art folded cascode operational amplifiers.
  • the excess current through transistor MP 10 over the constant current in transistor MN 5 flows through transistor MN 0 of positive slew boost circuit 14 and is gained up by the W/L ratio of MN 2 to that of transistor MN 0 .
  • the gained-up excess current flows through cascode transistor MN 3 and, in effect, “re-injects” it with the correct polarity to appropriately charge compensation capacitor C 1 and discharge compensation capacitor C 0 .
  • the operation is essentially similar if Vin ⁇ goes substantially positive relative to Vin+ so that the tail current 15 is steered through transistor MP 9 and the excess current flows through transistor MN 91 of negative slew boost circuit 13 , is gained up by transistor MN 92 , flows through cascode transistor MN 6 and conductor 16 , and then is mirrored through cascode transistor MP 1 by P-channel current mirror circuitry including transistors MP 4 and MP 3 .
  • the gained-up, mirrored excess current through cascode transistor MP 1 is injected into conductor 18 with the correct polarity to appropriately charge compensation capacitor C 0 and discharge compensation capacitor C 1 .
  • the slew rate of operational amplifier 10 will be increased.
  • increasing the gain of the slew boost circuits 13 and 14 is equivalent to increasing the gm of the input transistor pair MP 9 ,MP 10 during the slewing operation, and the gain margin of the operational amplifier 10 limits the overall amplifier gain to a value that is low enough to avoid circuit instability. Note that the technique of the present invention becomes increasingly effective for input transistors MP 9 and MP 10 which have low gate-to-drain capacitances.
  • the various geometry ratios of input transistors MP 9 and MP 10 , current source transistors MN 4 and MN 5 , and cascode transistors MN 3 and MN 6 should be selected so that the voltages of conductors 11 and 12 are less than one MOS threshold voltage above ground during normal operation, so that slew boost circuits 13 and 14 are completely off except during rapid input voltage transitions that result in a need for positive slewing or negative slewing operation at Vout conductor 27 . This prevents slew boost circuits 13 and 14 from contributing any undesirable noise or offset in operational amplifier 10 .
  • the constant current flowing through transistors MN 4 and MN 5 can be relatively small compared to the prior art.
  • the thermal noise contribution of transistors MN 4 and MN 5 is proportional to their transconductance gm, which is proportional to the constant current flowing through them.
  • FIG. 4 another operational amplifier embodiment 10 A of the present invention includes a conventional complementary folded cascode input stage 19 A which drives a class AB output stage 20 A, essentially the same as shown in prior art FIG. 1 .
  • Input stage 19 A includes P-channel input transistors MP 9 and MP 10 having their sources connected to tail current source 15 .
  • the gates of input transistors MP 9 and MP 10 are connected to Vin+and Vin ⁇ .
  • the drain of input transistor MP 10 is connected by conductor 11 to the drain of channel current source transistor MN 5 , the source of which is connected to ground.
  • the drain of input transistor MP 9 is connected by conductor 12 to the drain of N-channel current source transistor MN 4 , the source of which is connected to ground.
  • the gates of current source transistors MN 4 and MN 5 are connected by conductor 16 to the drain of a N-channel cascode transistor MN 6 and one terminal of a current source 29 , the other terminal of which is connected to VDD.
  • the drains of current source transistors MN 4 and MN 5 are connected to the sources of N-channel cascode transistors MN 3 and MN 6 , respectively.
  • the gates of cascode transistors MN 3 and MN 6 are connected to a reference voltage VB 1 .
  • the drain of cascode transistor MN 3 is connected by conductor 17 to the gates of output transistor MN 1 of class AB output stage 20 A.
  • Class AB output stage 20 A of FIG. 4 includes a current source 30 having one terminal connected to conductor 18 and another conductor connected to VDD, and the rest of class AB output stage 20 A is identical to output stage 20 of FIG. 3 .
  • constant current source 30 in FIG. 4 is replaced in FIG. 3 by transistors MP 3 , MP 4 , MP 1 and MP 14 which constitute a current source that handles both DC current and signal current.
  • the differential input to class AB output stage 20 A is advantageous in that it doubles the AC signal current gain into class AB output stage 20 compared to the single ended input class AB output stage 20 A in subsequently described FIG. 4 .
  • operational amplifier 10 A of FIG. 4 includes a negative slew boost circuit 13 A including a current mirror which includes diode-connected N-channel transistor MN 91 having its source connected to ground and its gate and drain connected to conductor 12 and to the gate of a N-channel current source transistor MN 92 .
  • Transistor MN 92 has its source connected to ground.
  • the drain of transistor MN 92 is connected to the drain of a P-channel cascode transistor MP 20 and to the gates of P-channel current mirror transistors MP 18 and MP 19 , the sources of which are connected to VDD.
  • the drain of current mirror transistor MP 18 is connected to the source of cascode transistor MP 20 .
  • the drain of current mirror transistor MP 19 is connected to the source of P-channel cascode transistor MP 21 .
  • the gates of cascode transistors MP 20 and MP 21 are connected to a second reference voltage VB 2 .
  • the drain of cascode transistor MP 21 is connected to conductor 18 .
  • Operational amplifier 10 A also includes a positive slew boost circuit 14 A including a current mirror that includes diode-connected N-channel transistor MN 0 having its source connected to ground and its gate and drain connected to conductor 11 and to the gate of N-channel current source transistor MN 2 having its source connected to ground and its drain connected the source of a N-channel cascode transistor MN 18 .
  • the gate of cascode transistor MN 18 is connected to VB 1 mentioned above.
  • the drain of cascode transistor MN 18 is connected to conductor 17 .
  • the magnitude of the tail current 15 of complementary folded cascode input stage 19 A in FIG. 4 is larger than the magnitude of the current flowing in either of current source transistors MN 4 and MN 5 . Consequently, under input signal overload conditions wherein most or all of tail current 15 is steered through one of input transistors MP 9 or MP 10 into the drain of one of current source transistors MN 5 or MN 4 , respectively, there will be an excess current over the amount of current that either of current source transistors MN 5 or MN 4 is capable of sinking.
  • the negative slew boost circuit 13 A of FIG. 4 is coupled to conductor 18 by means of an additional current mirror circuit including P-channel transistors MP 18 and MP 19 and P-channel cascode transistors MP 20 and MP 21
  • positive slew boost circuit 14 A is coupled to conductor 17 by means of additional cascode transistor MN 18 , so as to feed amplified slew boost currents directly to aid in charging into discharging of compensation capacitors C 0 and C 1 , respectively, during slewing operation.
  • This arrangement allows use of relatively small, fast transistors MN 18 and MP 21 as slew boost devices.
  • the simulated waveforms shown in FIG. 5 illustrate the much faster slew up and slew down rates for the embodiment shown in FIG. 4 than for the prior art, with 8 picofarad values for compensation capacitors C 0 and C 1 .
  • the slew rates are relatively independent of the output capacitance connected to output conductor 27 .
  • the solid line waveform in FIG. 5 shows a simulated waveform of Vout of the circuit shown in FIG. 4 including the slew boost circuitry of the present invention
  • the dashed line waveform in FIG. 5 shows a simulated waveform of Vout of the prior art circuit shown in FIG. 2 .
  • the rise time or slew up time of the rising edge A 1 of Vout for the present invention is much faster than the corresponding slew up time for the rising edge A 2 of Vout of the same circuit without the slew boost circuitry of the present invention.
  • the fall time or slew down time of the falling edge B 1 of Vout for the present invention is also much faster than the corresponding slew down time for the falling edge B 2 of Vout for the same circuit without the slew boost circuitry of the present invention.
  • FIG. 6 shows another embodiment of the invention wherein operational amplifier 10 C utilizes the same slew boost circuits 13 A and 14 A shown in FIG. 4 in place of the slew boost circuits 13 and 14 , respectively, shown in FIG. 3 .
  • transistors MP 3 and MP 4 are relatively large transistors, in order to reduce 1/f noise, and therefore are relatively slow in operation, usually too slow to be effective for use in slew boosting operation.
  • This leads to providing the embodiment of FIG. 6 in which large P-channel current mirror transistors are utilized for signal propagation, and the above described gain boost circuits 13 A and 14 A are used for slew boosting. Since the transistors used for slew boosting in gain boost circuits 13 A and 14 A in the embodiment of FIG. 6 are relatively small, no difficult design trade-offs are involved.
  • FIG. 7 illustrates such a bipolar integrated circuit amplifier similar to the one shown in FIG. 6 .
  • complementary folded-cascode input stage 19 B is similar to complementary folded cascode input stage 19 at shown in FIG. 6 .
  • Negative slew boost circuit 13 B is similar to negative slew boost circuit 13 A of FIG. 6
  • positive slew boost circuit 14 B is similar to positive slew boost circuit 14 A of FIG. 6 .
  • Conductors 17 A and 18 A of FIG. 7 correspond to conductors 17 and 18 , respectively, of FIG. 6 .
  • Bipolar class AB output stage 20 B is described in commonly assigned U.S. Pat. No. 6,542,032 issued Apr. 1, 2003 to Escobar-Bowser et al.
  • some folded cascode amplifiers have both a P-channel pair of differentially coupled input transistors and a N-channel pair of input transistors, and that the above described slew boost current mirror circuits could be connected to the drains of the differentially coupled N-channel input transistors as well as the differentially coupled P-channel input transistors.
  • An advantage of the present invention is that the technique is readily adaptable for use in a wide variety of operational amplifier circuits to greatly improve their slew rates with very little additional circuitry and with very little use of additional circuit chip area and without adversely affecting their operational parameters.
  • the described embodiments of present invention have low noise during normal operation, provide lower operating current in the second stage than in the input stage, and can be easily added to existing two-stage folded cascode amplifier designs without modifying the input stages. Also, the two current mirror circuits function to, in effect, provide a clamping voltage for the second stage cascode nodes, which decreases recovery time after a slewing event.

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US10/878,849 2004-06-28 2004-06-28 Slew rate enhancement circuitry for folded cascode amplifier Abandoned US20050285676A1 (en)

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Application Number Priority Date Filing Date Title
US10/878,849 US20050285676A1 (en) 2004-06-28 2004-06-28 Slew rate enhancement circuitry for folded cascode amplifier
PCT/US2005/023698 WO2006005040A2 (fr) 2004-06-28 2005-06-28 Circuit d'augmentation du taux de montee destine a un amplificateur cascode plie
US11/401,492 US7342450B2 (en) 2004-06-28 2006-04-11 Slew rate enhancement circuitry for folded cascode amplifier

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US20070139350A1 (en) * 2005-12-19 2007-06-21 Keiko Kawaguchi Amplification circuit, driver circuit for display, and display
WO2007140392A2 (fr) * 2006-05-31 2007-12-06 Texas Instruments Incorporated Procédés et dispositifs d'amélioration de balayage pour amplificateurs faible puissance
US20080180559A1 (en) * 2007-01-31 2008-07-31 Micron Technology, Inc. Apparatus, methods and systems for amplifier
US7414473B1 (en) * 2006-07-27 2008-08-19 Linear Technology Corporation Class AB folded-cascode amplifier having cascode compensation
US20080272844A1 (en) * 2006-07-27 2008-11-06 Linear Technology Corporation Class ab folded-cascode amplifier having cascode compensation
WO2009007346A1 (fr) * 2007-07-09 2009-01-15 Texas Instruments Deutschland Gmbh Générateur de courant de polarisation
WO2011047352A3 (fr) * 2009-10-16 2011-06-30 Qualcomm Incorporated Techniques de polarisation d'un amplificateur
EP2543141A1 (fr) * 2010-03-02 2013-01-09 Indian Institute Of Technology Amplificateur opérationnel à vitesse de balayage améliorée
US20130063116A1 (en) * 2011-09-14 2013-03-14 Fairchild Semiconductor Corporation True reverse current blocking system
US9054657B2 (en) 2013-09-30 2015-06-09 Texas Instruments Incorporated Reducing a settling time after a slew condition in an amplifier
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US9236912B2 (en) 2011-11-22 2016-01-12 Fairchild Semiconductor Corporation Dual input single output power multiplexer for near field communication application
US9236375B2 (en) 2011-09-14 2016-01-12 Fairchild Semiconductor Corporation Load switch with true reverse current blocking
US9622303B1 (en) 2015-09-22 2017-04-11 Nxp B.V. Current mirror and constant-current LED driver system for constant-current LED driver IC device
US9634617B2 (en) 2014-07-02 2017-04-25 Texas Instruments Incorporated Multistage amplifier circuit with improved settling time
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US10004117B2 (en) 2015-09-22 2018-06-19 Nxp B.V. Amplifier for a constant-current LED driver circuit and constant-current LED driver IC device
US10284157B2 (en) * 2016-12-28 2019-05-07 Texas Instruments Incorporated Analog driver with built-in wave shaping
TWI675548B (zh) * 2014-08-22 2019-10-21 美商英特希爾美國公司 用於摺疊式疊接放大器的跨導增益的快速回復方案
CN110752829A (zh) * 2019-09-23 2020-02-04 航天科工微电子系统研究院有限公司 应用于5G WiFi通信低噪声放大器的偏置电路、放大器电路
US20200321932A1 (en) * 2019-04-08 2020-10-08 Texas Instruments Incorporated Slew boost circuit for an operational amplifier
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US20220382306A1 (en) * 2019-10-18 2022-12-01 Sg Micro Corp Low dropout linear regulator with high power supply rejection ratio
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US7449952B2 (en) * 2007-03-14 2008-11-11 Ili Technology Corp. Amplifying circuit having a pull-up circuit and a pull-down circuit for increasing slew rate
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US7570113B2 (en) * 2007-09-24 2009-08-04 Texas Instruments Incorporated Overload recovery circuit for folded cascode amplifiers
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US9100007B2 (en) * 2011-12-23 2015-08-04 Analog Devices, Inc. Cascode amplifier
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US8890612B2 (en) 2012-10-19 2014-11-18 Freescale Semiconductor, Inc. Dynamically biased output structure
US10931240B2 (en) 2019-01-11 2021-02-23 Analog Devices International Unlimited Company Amplifier with reduced power consumption and improved slew rate
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US11626841B2 (en) 2020-07-10 2023-04-11 Texas Instruments Incorporated High quiescent current control
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TWI773474B (zh) * 2021-08-03 2022-08-01 新唐科技股份有限公司 放大器電路

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US20050083129A1 (en) * 2003-10-16 2005-04-21 Hirokazu Tsurumaki High frequency power amplifier circuit and electronic component for high frequency power amplifier
US7443245B2 (en) 2003-10-16 2008-10-28 Renesas Technology Corporation High frequency power amplifier circuit and electronic component for high frequency power amplifier
US7304539B2 (en) * 2003-10-16 2007-12-04 Renesas Technology Corporation High frequency power amplifier circuit and electronic component for high frequency power amplifier
US7629851B2 (en) 2003-10-16 2009-12-08 Renesas Technology Corp. High frequency power amplifier circuit and electronic component for high frequency power amplifier
US20090072906A1 (en) * 2003-10-16 2009-03-19 Hirokazu Tsurumaki High frequency power amplifier circuit and electronic component for high frequency power amplifier
US8139015B2 (en) * 2005-12-19 2012-03-20 Sony Corporation Amplification circuit, driver circuit for display, and display
US20070139350A1 (en) * 2005-12-19 2007-06-21 Keiko Kawaguchi Amplification circuit, driver circuit for display, and display
WO2007140392A3 (fr) * 2006-05-31 2008-12-24 Texas Instruments Inc Procédés et dispositifs d'amélioration de balayage pour amplificateurs faible puissance
WO2007140392A2 (fr) * 2006-05-31 2007-12-06 Texas Instruments Incorporated Procédés et dispositifs d'amélioration de balayage pour amplificateurs faible puissance
US7414473B1 (en) * 2006-07-27 2008-08-19 Linear Technology Corporation Class AB folded-cascode amplifier having cascode compensation
US20080272844A1 (en) * 2006-07-27 2008-11-06 Linear Technology Corporation Class ab folded-cascode amplifier having cascode compensation
US7639078B2 (en) 2006-07-27 2009-12-29 Linear Technology Corporation Class AB folded-cascode amplifier having cascode compensation
US7990452B2 (en) * 2007-01-31 2011-08-02 Aptina Imaging Corporation Apparatus, methods and systems for amplifier
US20080180559A1 (en) * 2007-01-31 2008-07-31 Micron Technology, Inc. Apparatus, methods and systems for amplifier
US8441308B2 (en) 2007-07-09 2013-05-14 Texas Instruments Incorporated Bias current generator
US20090039945A1 (en) * 2007-07-09 2009-02-12 Matthias Arnold Bias Current Generator
WO2009007346A1 (fr) * 2007-07-09 2009-01-15 Texas Instruments Deutschland Gmbh Générateur de courant de polarisation
CN102549917A (zh) * 2009-10-16 2012-07-04 高通股份有限公司 放大器偏压技术
EP2784935A3 (fr) * 2009-10-16 2014-10-29 Qualcomm Incorporated Techniques de polarisation d'amplificateur
WO2011047352A3 (fr) * 2009-10-16 2011-06-30 Qualcomm Incorporated Techniques de polarisation d'un amplificateur
EP2543141A1 (fr) * 2010-03-02 2013-01-09 Indian Institute Of Technology Amplificateur opérationnel à vitesse de balayage améliorée
EP2543141A4 (fr) * 2010-03-02 2014-07-09 Indian Inst Technology Amplificateur opérationnel à vitesse de balayage améliorée
US9236375B2 (en) 2011-09-14 2016-01-12 Fairchild Semiconductor Corporation Load switch with true reverse current blocking
US20130063116A1 (en) * 2011-09-14 2013-03-14 Fairchild Semiconductor Corporation True reverse current blocking system
US9236912B2 (en) 2011-11-22 2016-01-12 Fairchild Semiconductor Corporation Dual input single output power multiplexer for near field communication application
CN105027433A (zh) * 2013-01-15 2015-11-04 美商楼氏电子有限公司 具有转换速率控制的缩放运算放大器
US9054657B2 (en) 2013-09-30 2015-06-09 Texas Instruments Incorporated Reducing a settling time after a slew condition in an amplifier
US9634617B2 (en) 2014-07-02 2017-04-25 Texas Instruments Incorporated Multistage amplifier circuit with improved settling time
US9973161B2 (en) 2014-07-02 2018-05-15 Texas Instruments Incorporated Multistage amplifier circuit with improved settling time
TWI675548B (zh) * 2014-08-22 2019-10-21 美商英特希爾美國公司 用於摺疊式疊接放大器的跨導增益的快速回復方案
US9622303B1 (en) 2015-09-22 2017-04-11 Nxp B.V. Current mirror and constant-current LED driver system for constant-current LED driver IC device
US10004117B2 (en) 2015-09-22 2018-06-19 Nxp B.V. Amplifier for a constant-current LED driver circuit and constant-current LED driver IC device
US10284157B2 (en) * 2016-12-28 2019-05-07 Texas Instruments Incorporated Analog driver with built-in wave shaping
CN107154785A (zh) * 2017-06-29 2017-09-12 广州慧智微电子有限公司 一种控制电路、功率放大电路及方法
US20200321932A1 (en) * 2019-04-08 2020-10-08 Texas Instruments Incorporated Slew boost circuit for an operational amplifier
US10924074B2 (en) * 2019-04-08 2021-02-16 Texas Instruments Incorporated Slew boost circuit for an operational amplifier
US11595011B2 (en) 2019-04-08 2023-02-28 Texas Instruments Incorporated Slew boost circuit for an operational amplifier
US11894817B2 (en) 2019-04-08 2024-02-06 Texas Instruments Incorporated Slew boost circuit for an operational amplifier
CN110752829A (zh) * 2019-09-23 2020-02-04 航天科工微电子系统研究院有限公司 应用于5G WiFi通信低噪声放大器的偏置电路、放大器电路
CN112564676A (zh) * 2019-09-25 2021-03-26 圣邦微电子（北京）股份有限公司 一种比较器电路
US20220382306A1 (en) * 2019-10-18 2022-12-01 Sg Micro Corp Low dropout linear regulator with high power supply rejection ratio
US11994887B2 (en) * 2019-10-18 2024-05-28 Sg Micro Corp Low dropout linear regulator with high power supply rejection ratio
EP4350989A1 (fr) * 2022-09-14 2024-04-10 Semiconductor Components Industries, LLC Circuit d'amplification de vitesse de balayage

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US20060181350A1 (en) 2006-08-17
WO2006005040A3 (fr) 2006-06-15
WO2006005040A2 (fr) 2006-01-12

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