US20050151163A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- US20050151163A1 US20050151163A1 US11/026,542 US2654205A US2005151163A1 US 20050151163 A1 US20050151163 A1 US 20050151163A1 US 2654205 A US2654205 A US 2654205A US 2005151163 A1 US2005151163 A1 US 2005151163A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 110
- 238000004519 manufacturing process Methods 0.000 title claims description 40
- 239000000758 substrate Substances 0.000 claims abstract description 116
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 109
- 238000009413 insulation Methods 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 2
- 230000003068 static effect Effects 0.000 claims description 2
- 230000008901 benefit Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Definitions
- This invention relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device comprising a CMOS (Complementary Metal Oxide Semiconductor) device, a memory device and the like on the same substrate and a manufacturing method thereof.
- CMOS Complementary Metal Oxide Semiconductor
- a strained-Si layer on a semiconductor substrate and forming a MOS transistor on the strained-Si layer has been carried out.
- a banded structure of Si is varied by applying a tensile strain to Si.
- the strained-Si layer is formed by forming, for example, a Si 1 ⁇ x Ge x layer (hereinafter called a SiGe layer) having a greater lattice constant than Si on a semiconductor substrate and forming a Si layer thereon by epitaxial growth, to apply a sufficiently great tensile strain to Si. If a MOS transistor is formed on the strained-Si layer thus formed, carrier mobility is improved.
- a Si 1 ⁇ x Ge x layer hereinafter called a SiGe layer
- SiGe layer Si 1 ⁇ x Ge x layer
- CMOS device In accordance with high integration of a semiconductor device, a semiconductor device having a CMOS device with a memory device or an analog device on the same substrate is manufactured. If a semiconductor substrate having a strained-Si layer is used in such a semiconductor device, the carrier mobility of the CMOS device can be improved as explained above.
- CMOS device capable of compensating for high charge carrier mobility by using strained silicon is disclosed (see Jpn. Pat. Appln. KOKAI Publication No. 10-107294).
- a semiconductor device comprising a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.
- a semiconductor device comprising a silicon substrate having a first area, a second area adjacent to the first area, and a protrusion arranged in the first area, a relaxed layer which is provided on the silicon substrate in the second area and which has a lattice constant greater than a lattice constant of the silicon substrate, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.
- a method of manufacturing a semiconductor device comprising preparing a substrate having a first area and a second area adjacent to the first area, forming on the substrate a relaxed layer which has a lattice constant greater than a lattice constant of silicon, coating the relaxed layer of the second area with a resist film, etching the relaxed layer by using the resist film as a mask, removing the resist film, forming a first silicon layer on the substrate in the first area, and forming a strained-Si layer on the relaxed layer by epitaxial growth.
- a method of manufacturing a semiconductor device comprising preparing a silicon substrate having a first area and a second area adjacent to the first area, coating the silicon substrate in the first area with a resist film, etching the silicon substrate by using the resist film as a mask to form a protrusion on the silicon substrate, removing the resist film, forming a relaxed layer which has a lattice constant greater than a lattice constant of the silicon substrate, on the silicon substrate in the second area, and forming a strained-Si layer on the relaxed layer by epitaxial growth.
- FIG. 1 is a cross-sectional view showing main portions of a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 1 ;
- FIG. 3 is a cross-sectional view showing the manufacturing method subsequently to FIG. 2 ;
- FIG. 4 is a cross-sectional view showing the manufacturing method subsequently to FIG. 3 ;
- FIG. 5 is a cross-sectional view showing the manufacturing method subsequently to FIG. 4 ;
- FIG. 6 is a cross-sectional view showing the manufacturing method subsequently to FIG. 5 ;
- FIG. 7 is a cross-sectional view showing devices provided on the semiconductor device shown in FIG. 1 ;
- FIG. 8 is a cross-sectional view showing a structure of a SiGe layer 2 shown in FIG. 1 ;
- FIG. 9 is a cross-sectional view showing the semiconductor device of FIG. 1 having a SOI structure
- FIG. 10 is a cross-sectional view showing main portions of a semiconductor device according to a second embodiment of the present invention.
- FIG. 11 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 10 ;
- FIG. 12 is a cross-sectional view showing the manufacturing method subsequently to FIG. 11 ;
- FIG. 13 is a cross-sectional view showing the manufacturing method subsequently to FIG. 12 ;
- FIG. 14 is a cross-sectional view showing the manufacturing method subsequently to FIG. 13 ;
- FIG. 15 is a cross-sectional view showing the semiconductor device of FIG. 10 having a SOI structure
- FIG. 16 is a cross-sectional view showing the semiconductor device of FIG. 15 in which SiGe layer 10 reaches a Si substrate 1 ;
- FIG. 17 is a cross-sectional view showing main portions of a semiconductor device according to a third embodiment of the present invention.
- FIG. 18 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 17 ;
- FIG. 19 is a cross-sectional view showing the manufacturing method subsequently to FIG. 18 ;
- FIG. 20 is a cross-sectional view showing the manufacturing method subsequently to FIG. 19 ;
- FIG. 21 is a cross-sectional view showing the manufacturing method subsequently to FIG. 20 ;
- FIG. 22 is a cross-sectional view showing the manufacturing method subsequently to FIG. 21 ;
- FIG. 23 is a cross-sectional view showing the semiconductor device of FIG. 17 further having a Si layer 9 on an insulation layer 8 ;
- FIG. 24 is a cross-sectional view showing main portions of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 25 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 24 ;
- FIG. 26 is a cross-sectional view showing the manufacturing method subsequently to FIG. 25 ;
- FIG. 27 is a cross-sectional view showing the manufacturing method subsequently to FIG. 26 ;
- FIG. 28 is a cross-sectional view showing the manufacturing method subsequently to FIG. 27 ;
- FIG. 29 is a cross-sectional view showing the manufacturing method subsequently to FIG. 28 ;
- FIG. 30 is a cross-sectional view showing the semiconductor device of FIG. 24 having a SOI structure
- FIG. 31 is a cross-sectional view showing main portions of a semiconductor device according to a fifth embodiment of the present invention.
- FIG. 32 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 31 ;
- FIG. 33 is a cross-sectional view showing the manufacturing method subsequently to FIG. 32 ;
- FIG. 34 is a cross-sectional view showing the manufacturing method subsequently to FIG. 33 ;
- FIG. 35 is a cross-sectional view showing the manufacturing method subsequently to FIG. 34 ;
- FIG. 36 is a cross-sectional view showing the semiconductor device of FIG. 31 having a SOI structure
- FIG. 37 is a cross-sectional view showing the semiconductor device of FIG. 36 in which the SiGe layer 10 reaches the Si substrate 1 ;
- FIG. 38 is a cross-sectional view showing the semiconductor device of FIG. 17 further having a buffer film 20 .
- FIG. 1 is a cross-sectional view showing main portions of a semiconductor device according to a first embodiment of the present invention.
- a memory device and/or an analog device, and a digital device are mounted together on the semiconductor device.
- the analog device implies a device which gives a great influence to the characteristics and reliability of the semiconductor device when the current leak or noise occurs.
- the digital device implies a device which gives a small influence to the characteristics and reliability of the semiconductor device when the current leak or noise occurs.
- the memory device includes a DRAM, an SRAM (Static Random Access Memory), a flash memory and the like.
- the analog device includes a capacitor, a small-leak type transistor or amplifying element processing a greatly noise-influenced high-frequency signal, and the like.
- the digital device includes a CMOS device, a logic circuit and the like.
- an area where the memory device and/or the analog device (hereinafter referred to as “analog device and the like”) is formed is called an analog area, and an area where the digital device is formed is called a digital area.
- a Si layer 3 is formed on the analog area of a Si substrate 1 which is formed of, for example, silicon (Si).
- a SiGe layer 2 having a greater lattice constant than Si is formed on the digital area of the Si substrate 1 .
- a strained-Si layer 4 having substantially the same lattice constant as the lattice constant of the surface of the SiGe layer 2 is formed on the SiGe layer 2 .
- the semiconductor device shown in FIG. 1 is thus formed.
- the SiGe layer 2 is formed on the Si substrate 1 by, for example, epitaxial growth.
- the SiGe layer 2 has a thickness of, for example, 0.3 to 0.5 ⁇ m. Specifically, the thickness of the SiGe layer 2 is great enough to apply an adequate tensile strain to the strained-Si layer 4 and cause no defect in the SiGe layer 2 .
- a protection layer 5 is deposited on the SiGe layer 2 .
- the protection layer 5 is formed of, for example, SiN.
- the protection layer 5 is used to prevent Si from being formed on the surface of the SiGe layer 2 when the Si layer is formed during the after-treatment.
- a resist film 6 is applied to the surface of the protection layer 5 , and is subjected to patterning by lithography so as to expose the protection layer 5 of the analog area.
- the protection layer 5 is etched by wet etching using the resist film 6 as a mask, in FIG. 3 .
- the SiGe layer 2 on the Si substrate 1 is entirely etched by using the resist film 6 as a mask. The SiGe layer 2 is thus formed on the digital area alone.
- the resist film 6 is removed as shown in FIG. 4 .
- a Si layer 7 having a greater thickness than the SiGe layer 2 is formed by epitaxial growth, on the Si substrate 1 , as shown in FIG. 5 .
- the protection layer 5 is etched by wet etching as shown in FIG. 6 .
- the surfaces of the SiGe layer 2 and the Si layer 7 are flattened by CMP (Chemical Mechanical Polishing) to become plane.
- the CMP step may be omitted.
- Si is subjected to epitaxial growth on the SiGe layer 2 and the Si layer 7 in FIG. 1 .
- the strained-Si layer 4 is thereby formed on the SiGe layer 2 .
- the Si layer 3 (including the Si layer 7 ) is formed on the Si layer 7 .
- the semiconductor device shown in FIG. 1 is thus formed.
- the Si layer 3 and the strained-Si layer 4 having a greater lattice constant than the Si layer 3 can be formed on the same substrate.
- the leak current and noise can be reduced for the analog device and the like while the carrier mobility can be improved for the CMOS device, by forming the analog device and the like on the Si layer 3 and forming the CMOS device and the like on the strained-Si layer 4 .
- FIG. 7 is a cross-sectional view showing an example of the semiconductor device comprising the devices.
- a device isolation area including an STI (Shallow Trench Isolation) is formed on the semiconductor device.
- the CMOS device is formed on the strained-Si layer 4 (i.e. the digital area).
- the CMOS device includes a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an N-type MOSFET.
- An N-well 32 formed by diffusing a low-concentration N-type impurity is provided in the strained-Si layer 4 .
- a gate electrode 30 A is provided on the strained-Si layer 4 via a gate insulation film 30 B.
- a source/drain area 31 formed by implanting a high-concentration P-type impurity is provided in the N-well 32 provided on each of both sides of the gate electrode 30 A. The P-type MOSFET is thus formed.
- a P-well 35 formed by diffusing a low-concentration P-type impurity is provided in the strained-Si layer 4 .
- a gate electrode 33 A is provided on the strained-Si layer 4 via a gate insulation film 33 B.
- a source/drain area 34 formed by implanting a high-concentration N-type impurity is provided in the P-well 35 provided on each of both sides of the gate electrode 33 A. The N-type MOSFET is thus formed.
- the DRAM is formed on the Si layer 3 (i.e. the analog area).
- a trench capacitor 36 is provided on the Si layer 3 .
- a MOSFET 37 is also provided on the Si layer 3 .
- a source area of the MOSFET 37 is connected to the trench capacitor 36 .
- a metal layer 39 (bit line) is provided over the Si layer 3 .
- the metal layer 39 is connected to a drain area of the MOSFET 37 via a contact plug 38 .
- a password line 40 is also provided on the Si layer 3 through an insulation film.
- a junction capacitor is formed on the Si layer 3 .
- a lower electrode 41 is provided in the Si layer 3 .
- a capacitor dielectric film 42 is provided on the lower electrode 41 .
- An upper electrode 43 is provided on the capacitor dielectric film 42 so as to be exposed from the surface of the Si layer 3 .
- the CMOS device, the DRAM and the like can be formed on the same substrate, the leak current and noise can be reduced for the DRAM and the capacitor while the carrier mobility can be improved for the CMOS device.
- FIG. 8 is a cross-sectional view showing the structure of the SiGe layer 2 .
- the SiGe layer 2 of the present embodiment includes a buffer layer 2 A and a lattice-relaxed layer 2 B.
- the buffer layer 2 A is formed of silicon germanium S 1 ⁇ x Ge x in which the concentration of Ge is increased in the growth direction.
- the lattice-relaxed layer 2 B is formed of silicon germanium S 1 ⁇ x Ge x including Ge at a constant concentration.
- the dislocation between the SiGe layer 2 and the Si substrate 1 surface can be reduced by forming the SiGe layer 2 in this manner. Similarly, the dislocation between the SiGe layer 2 and the strained-Si layer 4 can be reduced.
- the lattice-relaxed layer 2 B may be formed on the Si substrate 1 .
- the buffer layer 2 A may not be required.
- the substrate may have a SOI (Silicon On Insulator) structure.
- FIG. 9 is a cross-sectional view showing the semiconductor device having the SOI structure.
- An insulation layer 8 is provided on the Si substrate 1 .
- the insulation layer 8 is formed of, for example, SiO 2 .
- a Si layer 9 is provided on the insulation layer 8 .
- the structure of the Si layer 3 , the SiGe layer 2 and the strained-Si layer 4 formed on the Si layer 9 is the same as that shown in FIG. 1 .
- a method of forming the Si layer 3 , the SiGe layer 2 and the strained-Si layer 4 are the same as the forming method explained with reference to FIG. 1 .
- the insulation layer 8 is first deposited on the Si substrate 1 . Then the Si layer 9 is formed on the insulation layer 8 .
- An existing SOI substrate may be prepared and used.
- the leak current and noise can be reduced for the analog device and the like while the carrier mobility can be improved for the CMOS device, by forming the analog device and the like on the Si layer 3 and forming the CMOS device and the like on the strained-Si layer 4 .
- the parasitic capacitance of the substrate can be reduced by employing the SOI structure.
- the operation speed of the CMOS device can be thereby enhanced.
- the analog area where the analog device and the like are formed, and the digital area where the digital device is formed are separated on the same Si substrate 1 .
- the Si layer 3 is formed in the analog area of the Si substrate 1 while the strained-Si layer 4 is formed in the digital area thereof.
- the analog device and the like, and the digital device can be therefore formed on the same substrate. If the analog device and the like, and the digital device are formed on the same substrate, the leak current and noise can be reduced for the analog device and the like while the carrier mobility can be improved for the CMOS device.
- the SiGe layer 2 includes the buffer layer 2 A and the lattice-relaxed layer 2 B. The dislocation between the SiGe layer 2 and the layers which are in contact therewith can be therefore reduced.
- the operation speed of the CMOS device can be further enhanced by reducing the parasitic capacitance.
- FIG. 10 is a cross-sectional view showing main portions of a semiconductor device according to a second embodiment of the present invention.
- the Si substrate 1 has a protrusion 1 A.
- the protrusion 1 A is formed in the analog area of the Si substrate 1 .
- the protrusion 1 A is also formed of the same material as the Si substrate 1 .
- a SiGe layer 10 is formed in the digital area of the Si substrate 1 .
- the SiGe layer 10 has a top surface exposed, and is embedded in the Si substrate 1 .
- the structure of the SiGe layer 10 is the same as that of the SiGe layer 2 of the first embodiment.
- a Si layer 11 is formed on the protrusion 1 A.
- a strained-Si layer 12 having substantially the same lattice constant as the lattice constant of the surface of the SiGe layer 10 is formed on the SiGe layer 10 .
- the semiconductor device shown in FIG. 10 is thus formed.
- a protection layer 13 is deposited on the Si substrate 1 .
- the protection layer 13 is formed of, for example, SiN.
- the protection layer 13 is used to prevent SiGe from being formed on the surface of the Si substrate 1 when the SiGe layer is formed during the after-treatment.
- a resist film 14 is applied to the surface of the protection layer 13 , and is subjected to patterning by lithography so as to expose the protection layer 13 of the digital area.
- the protection layer 13 is etched by using the resist film 14 as a mask, in FIG. 12 .
- the Si substrate 1 is etched to a predetermined depth by using the resist film 14 as a mask.
- the predetermined depth corresponds to the thickness of the SiGe layer 10 .
- the thickness of the SiGe layer 10 is great enough to apply an adequate tensile strain to the strained-Si layer 12 and cause no defect in the SiGe layer 10 .
- the protrusion 1 A is thus formed.
- the resist film 14 is removed.
- the SiGe layer 10 is formed on the Si substrate 1 of the digital area by epitaxial growth such that the top surface of the SiGe layer 10 is higher than the top surface of the protrusion 1 A as shown in FIG. 13 .
- the protection layer 13 is etched by wet etching as shown in FIG. 14 .
- the surfaces of the SiGe layer 10 and the protrusion 1 A are flattened by CMP (Chemical Mechanical Polishing) to become plane.
- CMP Chemical Mechanical Polishing
- Si is subjected to epitaxial growth on the SiGe layer 10 and the protrusion 1 A in FIG. 10 .
- the strained-Si layer 12 is thereby formed on the SiGe layer 10 .
- the Si layer 11 is formed on the protrusion 1 A.
- the semiconductor device shown in FIG. 10 is thus formed.
- the Si layer 11 and the strained-Si layer 12 having a greater lattice constant than the Si layer 11 can be formed on the same substrate.
- the leak current and noise can be reduced for the analog device and the like while the carrier mobility can be improved for the CMOS device, by forming the analog device and the like on the Si layer 11 and forming the CMOS device and the like on the strained-Si layer 12 .
- the devices shown in FIG. 7 are formed on the semiconductor device shown in FIG. 10 , the characteristics of the devices can be improved.
- the other advantage is also the same as that of the first embodiment.
- the structure of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
- the semiconductor device can be effectively manufactured by selecting the manufacturing method of the first embodiment or that of the second embodiment in accordance with the extent of the analog area and the digital area.
- the Si substrate 1 may have the SOI (Silicon On Insulator) structure.
- FIG. 15 is a cross-sectional view showing the semiconductor device having the SOI structure.
- the insulation layer 8 is provided on the Si substrate 1 .
- the insulation layer 8 is formed of, for example, SiO 2 .
- the Si layer 9 is provided on the insulation layer 8 .
- the other constituent elements are the same as those of FIG. 10 .
- FIG. 16 is a cross-sectional view showing the semiconductor device of FIG. 15 in which the SiGe layer 10 reaches the Si substrate 1 .
- An example of a method of manufacturing the semiconductor device shown in FIG. 16 is explained below.
- the Si layer 9 of the digital area is etched by using the resist film 14 shown in FIG. 11 as a mask, on a SOI substrate (not shown), and the insulation layer 8 is etched to expose the Si substrate 1 . Then the resist film 14 is removed.
- the SiGe layer 10 having a higher top surface than the top surface of the Si layer 9 of the analog area is formed on the Si substrate 1 of the digital area by epitaxial growth.
- the following steps of the manufacturing method are the same as those of the manufacturing method shown in FIG. 10 .
- the Si layer 11 and the strained-Si layers 12 having a greater lattice constant than the Si layer 11 can be formed on the same substrate.
- the parasitic capacitance can be reduced by employing the SOI structure and the operation speed of the devices formed on the Si layer 11 and the Si layer 9 can be thereby enhanced.
- FIG. 17 is a cross-sectional view showing main portions of a semiconductor device according to a third embodiment of the present invention.
- a Si layer 16 is provided in the analog area of the Si substrate 1 .
- the insulation layer 8 formed of, for example, SiO 2 is provided in the digital area of the Si substrate 1 .
- a SiGe layer 15 is provided on the insulation layer 8 .
- the structure of the SiGe layer 15 is the same as that of the SiGe layer 2 of the first embodiment.
- a Si layer 17 having substantially the same lattice constant as that of the top surface of the SiGe layer 15 is provided on the SiGe layer 15 .
- the semiconductor device shown in FIG. 17 is thus formed.
- the insulation layer 8 is formed on the Si substrate 1 .
- the Si layer 9 is formed on the insulation layer 8 .
- An existing SOI substrate may be prepared and used.
- the SiGe layer 15 is formed on the Si layer 9 by epitaxial growth.
- the protection layer 5 formed of SiN is deposited on the SiGe layer 15 .
- the semiconductor device is annealed in FIG. 19 .
- Ge in the SiGe layer 15 is thermally diffused to the Si layer 9 and the Si layer 9 becomes the SiGe layer 15 , by the annealing.
- the resist film 6 is applied to the surface of the protection layer 5 , and is subjected to patterning by lithography so as to expose the protection layer 5 of the analog area.
- the protection layer 5 is etched by using the resist film 6 as a mask, in FIG. 20 .
- the SiGe layer 15 is also etched by using the resist film 6 as a mask.
- the insulation layer 8 is also etched by using the resist film 6 as a mask. The surface of the Si substrate 1 in the analog area is thus exposed.
- the resist film 6 is removed as shown in FIG. 21 .
- a Si layer 18 is formed on the Si substrate 1 by epitaxial growth such that the top surface of the Si layer 18 is higher than the top surface of the SiGe layer 15 .
- the protection layer 5 is etched by wet etching. The surfaces of the SiGe layer 15 and the Si layer 18 are flattened by the CMP to become plane.
- Si is subjected to epitaxial growth on the SiGe layer 15 and the Si layer 18 as shown in FIG. 17 .
- the Si layer 17 is thereby formed on the SiGe layer 15 .
- the Si layer 16 (including the Si layer 18 ) is formed on the Si substrate 1 of the analog area.
- the semiconductor device of FIG. 17 is thus formed.
- the insulation layer 8 can be formed below the Si layer 17 of the digital area alone. Therefore, since the parasitic capacitance can be reduced, the operation speed of the CMOS device can be enhanced.
- FIG. 23 is a cross-sectional view showing the semiconductor device having the Si layer 9 on the insulation layer 8 .
- the same advantage as that of the present embodiment can be obtained. Moreover, it is possible to prevent a defect from being caused in an interface between the Si layer 9 and the SiGe layer 15 as compared with a case where the SiGe layer 15 is stacked on the Si layer 9 .
- FIG. 24 is a cross-sectional view showing main portions of a semiconductor device according to a fourth embodiment of the present invention.
- the Si layer 3 is provided in the analog area of the Si substrate 1 .
- the SiGe layer 2 is provided in the digital area of the Si substrate 1 .
- a buffer film 19 is provided between the Si layer 3 and the SiGe layer 2 to prevent a fault from being caused at a bonding portion between the Si layer 3 and the SiGe layer 2 .
- the buffer film 19 is formed of a material such as SiN, which can absorb the stress caused by the SiGe layer 2 or the fault resulting from the SiGe layer 2 .
- the strained-Si layer 4 is provided on the SiGe layer 2 .
- the semiconductor device of FIG. 24 is thus formed.
- the SiGe layer 2 is formed on the Si substrate 1 by epitaxial growth.
- the protection layer 5 is deposited on the SiGe layer 2 .
- the resist film 6 is applied to the surface of the protection layer 5 , and is subjected to patterning by lithography so as to expose the protection layer 5 of the analog area.
- the protection layer 5 is etched by using the resist film 6 as a mask, in FIG. 26 .
- the SiGe layer 2 is also etched by using the resist film 6 as a mask. Then, the resist film 6 is removed.
- the buffer film 19 formed of, for example, SiN is deposited on the entire surface of the semiconductor device.
- the buffer film 19 on the Si substrate 1 and the protection layer 5 is etched by anisotropic etching in FIG. 27 .
- the buffer film 19 is thereby formed on side surfaces of the SiGe layer 2 alone.
- the Si layer 7 having a greater thickness than the SiGe layer 2 is formed on the Si substrate 1 by epitaxial growth, as shown in FIG. 28 .
- the protection layer 5 is etched by the wet etching.
- the surfaces of the SiGe layer 2 and the Si layer 7 are flattened by the CMP to become plane.
- Si is subjected to epitaxial growth on the SiGe layer 2 and the Si layer 7 as shown in FIG. 24 .
- the strained-Si layer 4 is thereby formed on the SiGe layer 2 .
- the Si layer 3 (including the Si layer 7 ) is formed on the Si layer 7 .
- Si is not subjected to epitaxial growth on the buffer film 19 .
- the buffer film 19 By thinning the buffer film 19 , however, cavities are not generated between the Si layer 3 and the strained-Si layer 4 , due to extension of Si from the SiGe layer 2 and the Si layer 7 .
- the semiconductor device shown in FIG. 24 is thus formed.
- the composition ratio of Ge in the SiGe layer 2 becomes larger toward the top surface of the layer.
- the lattice constant of the SiGe layer 2 becomes larger toward the top surface.
- a fault may occur at the bonding portion between the SiGe layer 2 and the Si layer 3 .
- the buffer film 19 is provided between the SiGe layer 2 and the Si layer 3 .
- the buffer film 19 absorbs the stress caused by the SiGe layer 2 or the fault resulting from the SiGe layer 2 .
- the buffer film 19 also prevents the stress caused by the SiGe layer 2 or the like from being applied to the bonding portion between the SiGe layer 2 and the Si layer 3 .
- the fault between the SiGe layer 2 and the Si layer 3 can be thereby reduced.
- the Si substrate 1 may have the SOI structure.
- FIG. 30 is a cross-sectional view showing the semiconductor device having the SOI structure. With this structure, the same advantages as those of the semiconductor device described with reference to FIG. 9 can be obtained.
- FIG. 31 is a cross-sectional view showing main portions of a semiconductor device according to a fifth embodiment of the present invention.
- the Si substrate 1 has the protrusion 1 A.
- the protrusion 1 A is formed in the analog area of the Si substrate 1 .
- the SiGe layer 10 is formed in the digital area of the Si substrate 1 .
- the SiGe layer 10 has a top surface exposed, and is embedded in the Si substrate 1 .
- a buffer film 20 is provided between the protrusion 1 A and the SiGe layer 10 .
- the buffer film 20 is formed of, for example, SiN.
- the Si layer 11 is formed on the protrusion 1 A.
- the strained-Si layer 12 is formed on the SiGe layer 10 .
- the semiconductor device shown in FIG. 31 is thus formed.
- the protection layer 13 is deposited on the Si substrate 1 .
- the resist film 14 is applied to the surface of the protection layer 13 , and is subjected to patterning by lithography so as to expose the protection layer 13 of the digital area.
- the protection layer 13 is etched by using the resist film 14 as a mask, in FIG. 33 .
- the Si substrate 1 is etched to a predetermined depth by using the resist film 14 as a mask. The protrusion 1 A is thus formed.
- the buffer film 20 formed of, for example, SiN is deposited on the entire surface of the semiconductor device.
- the buffer film 20 on the Si substrate 1 and the protection layer 13 is etched by anisotropic etching.
- the buffer film 20 is thus formed on both sides of the protrusion 1 A.
- the SiGe layer 10 is formed on the Si substrate 1 of the digital area by epitaxial growth such that the top surface of the SiGe layer 10 is higher than the top surface of the protrusion 1 A.
- the protection layer 13 is etched by wet etching.
- the surfaces of the SiGe layer 10 and the protrusion 1 A are flattened by the CMP to become plane.
- Si is subjected to epitaxial growth on the SiGe layer 10 and the protrusion 1 A in FIG. 31 .
- the strained-Si layer 12 is thereby formed on the SiGe layer 10 .
- the Si layer 11 is formed on the protrusion 1 A.
- Si is not subjected to epitaxial growth on the buffer film 20 .
- the buffer film 19 By thinning the buffer film 19 , however, cavities are not generated between the Si layer 11 and the strained-Si layer 12 , due to extension of Si from the SiGe layer 10 and the protrusion 1 A, The semiconductor device shown in FIG. 31 is thus formed.
- the buffer film 20 is provided between the SiGe layer 10 and the protrusion 1 A. Therefore, the fault generated at the bonding portion between the SiGe layer 10 and the protrusion 1 A can be reduced.
- the Si substrate 1 may have the SOI structure.
- FIG. 36 is a cross-sectional view showing the semiconductor device having the SOI structure. With this structure, the same advantages as those of the semiconductor device described with reference to FIG. 15 can be obtained.
- FIG. 37 is a cross-sectional view showing the semiconductor device of FIG. 36 in which the SiGe layer 10 reaches the insulation layer 8 .
- the semiconductor device of the third embodiment shown in FIG. 17 may have the buffer film 20 .
- FIG. 38 is a cross-sectional view showing the semiconductor device of FIG. 17 further having the buffer film 20 .
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Priority Applications (2)
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US11/889,420 US7737466B1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
US11/889,451 US20070290208A1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (2)
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JP2004001075A JP2005197405A (ja) | 2004-01-06 | 2004-01-06 | 半導体装置とその製造方法 |
JP2004-001075 | 2004-01-06 |
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US11/889,420 Division US7737466B1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
US11/889,451 Division US20070290208A1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
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US11/889,420 Expired - Fee Related US7737466B1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
US11/889,451 Abandoned US20070290208A1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
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US11/889,420 Expired - Fee Related US7737466B1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
US11/889,451 Abandoned US20070290208A1 (en) | 2004-01-06 | 2007-08-13 | Semiconductor device and manufacturing method thereof |
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US (3) | US20050151163A1 (ko) |
JP (1) | JP2005197405A (ko) |
KR (1) | KR100604393B1 (ko) |
CN (1) | CN100377352C (ko) |
TW (1) | TWI258856B (ko) |
Cited By (4)
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US20050218455A1 (en) * | 2004-03-30 | 2005-10-06 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device, layout and manufacturing method |
US20080064157A1 (en) * | 2004-03-30 | 2008-03-13 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device, layout and manufacturing method |
CN102347235A (zh) * | 2010-08-04 | 2012-02-08 | 中国科学院微电子研究所 | 应变半导体沟道形成方法和半导体器件 |
US8575654B2 (en) * | 2010-08-04 | 2013-11-05 | Institute of Microelectronics, Chinese Academy of Sciences | Method of forming strained semiconductor channel and semiconductor device |
Families Citing this family (2)
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US7384829B2 (en) * | 2004-07-23 | 2008-06-10 | International Business Machines Corporation | Patterned strained semiconductor substrate and device |
JP5269478B2 (ja) * | 2008-05-26 | 2013-08-21 | 株式会社東芝 | 半導体装置 |
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Also Published As
Publication number | Publication date |
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KR20050072398A (ko) | 2005-07-11 |
JP2005197405A (ja) | 2005-07-21 |
CN100377352C (zh) | 2008-03-26 |
CN1638126A (zh) | 2005-07-13 |
TWI258856B (en) | 2006-07-21 |
KR100604393B1 (ko) | 2006-07-25 |
US7737466B1 (en) | 2010-06-15 |
US20070290208A1 (en) | 2007-12-20 |
TW200525729A (en) | 2005-08-01 |
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