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US20050139478A1 - Apparatus and method for electrolytically depositing copper on a semiconductor workpiece - Google Patents

Apparatus and method for electrolytically depositing copper on a semiconductor workpiece Download PDF

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US20050139478A1
US20050139478A1 US11067278 US6727805A US2005139478A1 US 20050139478 A1 US20050139478 A1 US 20050139478A1 US 11067278 US11067278 US 11067278 US 6727805 A US6727805 A US 6727805A US 2005139478 A1 US2005139478 A1 US 2005139478A1
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copper
layer
seed
process
bath
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US11067278
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LinLin Chen
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Semitool Inc
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Semitool Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
    • C23C28/322Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer only coatings of metal elements only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10Electroplating with more than one layer of the same or of different metals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76868Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors
    • H01L2221/1073Barrier, adhesion or liner layers
    • H01L2221/1084Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089Stacks of seed layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method

Abstract

This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This Application is a continuation of U.S. application Ser. No. 09/885,232 filed on Jun. 20, 2001 now U.S. Pat. No. 6,811,675. U.S. application Ser. No. 09/885,232 is a Continuation of U.S. application Ser. No. 09/387,033 filed on Aug. 31, 1999, now U.S. Pat. No. 6,290,833. U.S. application Ser. No. 09/387,033 is a Continuation of application International Application No. PCT/US99/06306 filed on Mar. 22, 1999. PCT/US99/06306 is a continuation-in-part of U.S. application Ser. No. 09/045,245, filed on Mar. 20, 1998, and claims the benefit of U.S. Provisional Application No. 60/085,675 filed on May 15, 1998.
  • BACKGROUND OF THE INVENTION
  • [0002]
    In the fabrication of microelectronic devices, application of one or more metallization layers is often an important step in the overall fabrication process. The metallization may be used in the formation of discrete microelectronic components, such as read/write heads, but is more often used to interconnect components formed on a workpiece, such as a semiconductor workpiece. For example, such structures are used to interconnect the devices of an integrated circuit.
  • [0003]
    A basic understanding of certain terms used herein will assist the reader in understanding the disclosed subject matter. To this end, basic definitions of certain terms, as used in the present disclosure, are set forth below.
      • Single Metallization Level is defined as a composite level of a workpiece that is exterior to the substrate. The composite level comprises one or more metal structures.
      • Substrate is defined as a base layer of material over which one or more metallization levels are disposed. The substrate may be, for example, a semiconductor wafer, a ceramic block, etc.
      • Workpiece is defined as an object that at least comprises a substrate, and may include further layers of material or manufactured components, such as one or more metallization levels, disposed on the substrate.
  • [0007]
    An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor. Devices which may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
  • [0008]
    Delays in propagation of electrical signals between devices on a single die limit the performance of integrated circuits. More particularly, these delays limit the speed at which an integrated circuit may process these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
  • [0009]
    For each interconnect path, signal propagation delay may be characterized by a time delay T. See E. H. Stevens, Interconnect Technology, QMC, Inc., July 1993. An approximate expression for the time delay, T, as it relates to the transmission of a signal between transistors on an integrated circuit is given below.
    τ=RC[1+(V SAT /RI SAT)]
  • [0010]
    In this equation, R and C are, respectively, an equivalent resistance and capacitance for the interconnect path and ISAT and VSAT are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path. The path resistance is proportional to the resistivity, ρ, of the conductor material. The path capacitance is proportional to the relative dielectric permittivity, Ke, of the dielectric material. A small value of τ requires that the interconnect line carry a current density sufficiently large to make the ratio VSAT/RISAT small. It follows therefore, that a low-ρ conductor which can carry a high current density and a low Ke dielectric must be utilized in the manufacture of high-performance integrated circuits.
  • [0011]
    To meet the foregoing criterion, copper interconnect lines within a low-Ke dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See “Copper Goes Mainstream: Low-k to Follow”, Semiconductor International, November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 μΩcm.; resistivities of aluminum-alloy films are in the range of 3.0 to 3.5 μΩcm.
  • [0012]
    Despite the advantageous properties of copper, it has not been as widely used as an interconnect material as one would expect. This is due, at least in part, to the difficulty of depositing copper metallization and, further, due to the need for the presence of barrier layer materials. The need for a barrier layer arises from the tendency of copper to diffuse into silicon junctions and alter the electrical characteristics of the semiconductor devices formed in the substrate. Barrier layers made of, for example, titanium nitride, tantalum nitride, etc., must be laid over the silicon junctions and any intervening layers prior to depositing a layer of copper to prevent such diffusion.
  • [0013]
    A number of processes for applying copper metallization to semiconductor workpieces have been developed in recent years. One such process is chemical vapor deposition (CVD), in which a thin copper film is formed on the surface of the barrier layer by thermal decomposition and/or reaction of gas phase copper compositions. A CVD process can result in conformal copper coverage over a variety of topological profiles, but such processes are expensive when used to implement an entire metallization layer.
  • [0014]
    Another known technique, physical vapor deposition (PVD), can readily deposit copper on the barrier layer with relatively good adhesion when compared to CVD processes. One disadvantage of PVD processes, however, is that they result in poor (non-conformal) step coverage when used to fill microstructures, such as vias and trenches, disposed in the surface of the semiconductor workpiece. For example, such non-conformal coverage results in less copper deposition at the bottom and especially on the sidewalls of trenches in the semiconductor devices.
  • [0015]
    Inadequate deposition of a PVD copper layer into a trench to form an interconnect line in the plane of a metallization layer is illustrated in FIG. 1. As illustrated, the upper portion of the trench is effectively “pinched off” before an adequate amount of copper has been deposited within the lower portions of the trench. This result in an open void region that seriously impacts the ability of the metallization line to carry the electrical signals for which it was designed.
  • [0016]
    Electrochemical deposition of copper has been found to provide the most cost-effective manner in which to deposit a copper metallization layer. In addition to being economically viable, such deposition techniques provide substantially conformal copper films that are mechanically and electrically suitable for interconnect structures. These techniques, however, are generally only suitable for applying copper to an electrically conductive layer. As such, an underlying conductive seed layer is generally applied to the workpiece before it is subject to an electrochemical deposition process. Techniques for electrodeposition of copper on a barrier layer material have not heretofore been commercially viable.
  • [0017]
    The present inventors have recognized that there exists a need to provide copper metallization processing techniques that 1) provide conformal copper coverage with adequate adhesion to the barrier layer, 2) provide adequate deposition speeds, and 3) are commercially viable. These needs are met by the apparatus and processes of the present invention as described below.
  • BRIEF SUMMARY OF THE INVENTION
  • [0018]
    This invention employs a novel approach to the copper metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. The resulting copper layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting copper seed layer provide an excellent conformal copper coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, copper layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
  • [0019]
    The disclosed process, as noted above, is applicable to a wide range of steps used in the manufacture of a metallization layer in a workpiece. The workpiece may, for example, be a semiconductor workpiece that is processed to form integrated circuits or other microelectronic components. Without limitation as to the applicability of the disclosed invention, a process for enhancing a seed layer is described.
  • [0020]
    A process for applying a metallization interconnect structure to a workpiece having a barrier layer deposited on a surface thereof is also set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer has a thickness of less than or equal to about 500 Angstroms and may be formed from any material that can serve as a seed layer for subsequent metal deposition. Such metals include, for example, copper, copper alloys, aluminum, aluminum alloys, nickel, nickel alloys, etc. The ultra-thin seed layer is then enhanced by depositing additional metal thereon in a separate deposition step to provide an enhanced seed layer that is suitable for use in a primary metal deposition. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
  • [0021]
    In accordance with a specific embodiment of the process, a copper-containing metallization interconnect structure is formed. To this end, the ultra-thin seed layer is enhanced by subjecting the semiconductor workpiece to an electrochemical copper deposition process in which an alkaline bath having a complexing agent is employed. The copper complexing agent may be at least one complexing agent selected from a group consisting of EDTA, ED, and a polycarboxylic acid such as citric acid or salts thereof.
  • [0022]
    Various plating bath compositions suitable for blanket plating, fill-plating of recessed micro-structures, and seed layer enhancement plating are also set forth. A preferred solution for electroplating copper for seed layer enhancement comprises copper sulfate, boric acid, and a complexing agent. The complexing agent is preferably selected from the group consisting of ED, EDTA, and a polycarboxylic acid, such as citric acid. This solution is also suitable for blanket plating and fill-plating of recessed micro-structures.
  • [0023]
    A plating solution that improves the resistivity of the resulting copper film is also set forth. The plating solution preferably comprises copper sulfate, ammonium sulfate, and ethylene glycol. This solution is also suitable for blanket plating and fill-plating of recessed micro-structures.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • [0024]
    FIG. 1 is a cross-sectional view illustrating an interconnect line formed completely by PVD copper.
  • [0025]
    FIGS. 2A-2E are cross-sectional views through a semiconductor workpiece illustrating the various layers of material as they are applied in accordance with one embodiment of the present invention.
  • [0026]
    FIG. 3 is a schematic representation of an apparatus suitable for enhancing an ultra-thin seed layer.
  • [0027]
    FIG. 4A is a graph illustrating the current-potential curves of a plating solution using a polycarboxylic acid, such as citric acid, as a complexing agent.
  • [0028]
    FIG. 4B is a graph illustrating the current-potential curves of a plating solution using EDTA, an amine-containing plating solution, as the complexing agent.
  • [0029]
    FIG. 4C is a graph of sheet resistance change with annealing temperature for copper films deposited from a bath solution with and without ammonium sulfate.
  • [0030]
    FIG. 4D is a graph illustrating plating solution conductivity as a function of ethylene glycol concentration in collating solutions with and without ammonium sulfate.
  • [0031]
    FIG. 5 is a scanning eletromicrograph photograph illustrating an ultra-thin seed layer.
  • [0032]
    FIG. 6A is a scanning eletromicrograph photograph illustrating an ultra-thin seed layer that has been enhanced in a citric acid bath.
  • [0033]
    FIG. 6B is a scanning eletromicrograph photograph illustrating an ultra-thin seed layer that has been enhanced in an EDTA bath.
  • [0034]
    FIG. 7 is a schematic representation of a section of a semiconductor manufacturing line suitable for implementing the disclosed seed layer enhancement steps.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0035]
    This invention employs a novel approach to applying copper metallization to a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electrolytic copper bath is used to electroplate copper onto a seed layer, electroplate copper directly onto a barrier layer material, or enhance an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD. Additionally, a method for applying a metallization layer will be disclosed. Although the disclosed method may be used in connection with a substantial number of different metal compositions, the specific embodiment disclosed herein is directed to the application of a copper-containing metallization layer. To this end, an alkaline electrolytic copper bath is used to enhance an ultra-thin copper seed layer which has been deposited on a barrier layer using a deposition process such as PVD. The enhanced copper seed layer provides an excellent conformal copper coating that allows trenches and vias to be subsequently filled with a copper layer having good uniformity using electrochemical deposition techniques.
  • [0036]
    A cross-sectional view of a micro-structure, such as trench 5, that is to be filled with copper metallization is illustrated in FIG. 2A and will be used to describe the seed layer enhancement aspects of the present invention. As shown, a thin barrier layer 10 of, for example, titanium nitride or tantalum nitride is deposited over the surface of a semiconductor device or, as illustrated in FIG. 2A, over a layer of a dielectric 8, such as silicon dioxide. The barrier layer 10 acts to prevent the migration of copper to any semiconductor device formed in the substrate. Any of the various known techniques, such as CVD or PVD, can be used to deposit the barrier layer depending on the particular barrier material being used. Preferably, the thickness for the barrier layer is approximately 100 to 300 Angstroms.
  • [0037]
    After the deposition of the barrier layer, an ultra-thin copper seed layer 15 is deposited on the barrier layer 10. The resulting structure is illustrated in FIG. 2B. Preferably, the copper seed layer 15 is formed using a vapor deposition technique, such as CVD or PVD. In order to have adequate adhesion and copper coverage, a relatively thick (1000 Angstroms) copper seed layer is usually required. Such a thick seed layer leads to problems with close-off of small geometry trenches, however, when a PVD deposition process is employed for applying the seed layer.
  • [0038]
    Contrary to traditional thoughts regarding seed layer application, the copper seed layer 15 of the illustrated embodiment is ultra-thin, having a thickness of about 50 to about 500 Angstroms, preferably about 100 to about 250 Angstroms, and most preferably about 200 Angstroms. The ultra-thin copper seed layer can be deposited using a CVD or a PVD process, or a combination of both. PVD is the preferred application process, however, because it can readily deposit copper on the barrier layer 10 with relatively good adhesion. By depositing an ultra-thin seed layer of copper, rather than the relatively thick seed layer used in the prior art, pinching off of the trenches can be avoided.
  • [0039]
    The use of an ultra-thin seed layer 15 generally introduces its own set of problems. One of the most significant of these problems is the fact that such ultra-thin layers do not generally coat the barrier layer 10 in a uniform manner. Rather, voids or non-continuous seed layer regions on the sidewalls, such as at 20, are often present in an ultra-thin seed layer 15 thereby resulting in the inability to properly apply a subsequent electrochemically deposited copper layer in the regions 20. Further, ultra-thin seed layers tend to include spikes, such as at 21, that impact the uniformity of the subsequent electrolytically deposited metal layer. Such spikes 21 result in high potential regions at which the copper deposits at a higher rate than at other, more level regions. As such, the seed layer 15 is not fully suitable for the traditional electroplating techniques typically used after application of a seed layer.
  • [0040]
    The present inventors have found that an ultra-thin seed layer can be employed if it is combined with a subsequent electrochemical seed layer enhancement technique. To this end, the semiconductor workpiece is subject to a subsequent process step in which a further amount of copper 18 is applied to the ultra-thin seed layer to thereby enhance the seed layer. A seed layer enhanced by the additional deposition of copper is illustrated in FIG. 2C. As shown in FIG. 2C, the void or non-continuous regions 20 of FIG. 2B have been filled thereby leaving substantially all of the barrier layer 10 covered with copper.
  • [0041]
    Preferably, the seed layer enhancement process continues until a sidewall step coverage, i.e., the ratio of the seed layer thickness at the bottom sidewall regions 22 to the nominal thickness of the seed layer at the exteriorly disposed side 23 of the workpiece, achieves a value of at least 10%. More preferably, the sidewall step coverage is at least about 20%. Such sidewall step coverage values are present in substantially all of the recessed structures of the semiconductor workpiece. It will be recognized, however, that certain recessed structures distributed within the semiconductor workpiece may not reach these sidewall step coverage values. For example, such structures disposed at the peripheral edges of a semiconductor wafer may not reach these step coverage values. Similarly, defects or contaminants at the situs of certain recessed structures may prevent them from reaching the desired coverage values. The nominal thickness of the enhanced seed layer at the exteriorly disposed side of the workpiece is preferably in the range of 500 angstroms to 1600 angstroms.
  • [0042]
    Although the embodiment of the process disclosed herein is described in connection with copper metallization, it is understood that the basic principle of the enhancement of an ultra-thin seed layer prior to the bulk deposition thereof can be applied to other metals or alloys that are capable of being electroplated. Such metals include iron, nickel, cobalt, zinc, copper-zinc, nickel-iron, cobalt-iron, etc.
  • [0043]
    A schematic representation of an apparatus 25 suitable for enhancing the ultra-thin copper seed layer is illustrated in FIG. 3. It will be recognized that this apparatus is also suitable for applying a blanket plating layer and/or full-fill plating of recessed micro-structures. As shown, a semiconductor workpiece, such as a semiconductor wafer 30, is positioned face down in a bath 35 of electroplating solution. One or more contacts 40 are provided to connect the wafer 30 to a plating power supply 45 as a cathode of an electroplating cell. An anode 50 is disposed in the bath 35 and is connected to the plating power supply 45. Preferably, a diffuser 55 is disposed between the anode 50 and the wafer/cathode 30. The wafer 30 may be rotated about axis 60 during the enhancement process. Mode 50 may be provided with a dielectric shield 65 at a backside thereof which faces an incoming stream of plating bath fluid.
  • [0044]
    As noted above, certain aspects of the present invention relate to new and useful plating solutions. These solutions can be used for blanket plating, full-fill of the recessed micro-structures, seed layer enhancement, etc. The preferred electrolytic bath solution for enhancing the seed layer is an alkaline copper bath in which copper ions are complexed with a complexing agent. A preferred composition and range of concentrations for the various components of the plating bath include the following:
      • 1. Copper sulfate: 0.03M to 0.25M (preferably, 0.04);
      • 2. Complexing agent: complex to metal ratios from 1 to 4, preferably 2;
      • 3. Boric acid: 0.01M to 0.5M, preferably 0.05M, and
      • 4. pH: 5-13, preferably 9.5.
  • [0049]
    A preferred source of copper ions is copper sulfate (CUSO4). The concentration of copper sulfate in the bath is preferably within the range of 0.03 to 0.25 M, and is more preferably about 0.1 M.
  • [0050]
    Complexing agents that are suitable for use in the present invention form a stable complex with copper ions and prevent the precipitation of copper hydroxide. Ethylene diamine tetracetic acid (EDTA), ethylene diamine (ED), citric acid, and their salts have been found to be particularly suitable copper complexing agents. The molar ratio of complexing agent to copper sulfate in the bath is preferably within the range of 1 to 4, and is preferably about 2. Such complexing agents can be used alone, in combination with one another, or in combination with one or more further complexing agents.
  • [0051]
    The electrolytic bath is preferably maintained at a pH of at least 9.0. Potassium hydroxide, ammonium hydroxide, tetramethylammonium hydroxide, or sodium hydroxide is utilized to adjust and maintain the pH at the desired level of 9.0 or above. A preferred pH for a citric acid or ED bath is about 9.5, while a preferred pH for an EDTA bath is about 12.5. As noted above, the complexing agent assists in preventing the copper from precipitating at the high pH level.
  • [0052]
    Additional components can be added to the alkaline copper bath. For example, boric acid H3BO3 aids in maintaining the pH at 9.5 when citric acid or ED is used as the complexing agent, and provides brighter copper deposits when added to an electrolytic bath containing EDTA as the complexing agent. If boric acid is added, its concentration in the bath is preferably within the range of 0.01 to 0.5 M.
  • [0053]
    In general, the temperature of the bath can be within the range of 20 to 35° C., with 25° C. being a preferred temperature. The current density for electrolytically depositing copper to enhance the copper seed layer can be 1 to 5 milliamps/cm2, while a plating time of about 1 to about 5 minutes is sufficient to enhance the copper seed layer. The plating waveform may be, for example, a forward periodic pulse having a period of 2 msec at a 50% duty cycle.
  • [0054]
    An amine free acid complexing agent, for example, a polycarboxylic acid, such as citric acid, and salts thereof, is preferable to the use of EDTA or ED. EDTA and ED include amine groups. These amine groups often remain on the surface of the semiconductor workpiece after rinsing and drying of the wafer. Subsequent processes, particularly such processes as photolithographic processes, may be corrupted by the reactions resulting from the presence of these amine groups. The amine groups may, for example, interfere with the chemical reactions associated with the exposing and/or curing of photoresist materials. As such, amine free complexing agents are particularly suitable in processes in which a photolithographic process follows an electrodeposition process.
  • [0055]
    A further advantage of using a polycarboxylic acid, such as citric acid, stems from the fact that the magnitude of the voltage potential at which the copper is plated is greater than the magnitude of the voltage potential at which the copper is plated in a bath containing EDTA. This is illustrated in FIGS. 4A and 4B where FIG. 4A is a current-potential graph for a citric acid bath, and FIG. 4B is a current-potential graph for an EDTA bath. Electroplating takes place at the voltage where the corresponding current increases abruptly. This plating voltage is referred to as the deposition potential, which is approximately −1.25 volts as shown in FIG. 4A for a bath employing citric acid as the complexing agent, and is approximately −1.0 volts as shown in FIG. 4B for a bath employing EDTA as the complexing agent. The current peaks (70 70′ for the bath containing a citric acid, and 72, 72′ for the bath containing the EDTA) are the limiting currents which are mainly determined by mass transfer and the concentration of copper ions in the plating solutions. As illustrated, the magnitude of the current and the particular plating potential is slightly dependent on the substrate material. The different substrate results are illustrated in FIGS. 4A and 4B, where 70 and 72 are the curves for a copper substrate material, and 70′ and 72′ are curves for a copper substrate material comprised of copper with a copper oxide coating. It is noted that additional peaks occur on oxidized copper in the same electrolytes. These peaks are related to the electrochemical reduction of copper oxide to metallic copper before the alkaline electrochemical copper deposition.
  • [0056]
    It is believed that a copper layer plated at a higher plating potential in an alkaline bath provides greater adhesion to the underlying barrier layer than a copper layer plated at a lower plating potential in an acid bath. For copper to adhere to the barrier material, it is thought that copper ions must impinge on the barrier surface with sufficient energy to penetrate a thin oxidized or contaminated layer at the barrier surface. It is therefore believed that a copper layer deposited at a higher magnitude plating potential adhere is better to the exposed barrier layer during the plating process when compared to a layer plated using a smaller magnitude plating potential. This factor, combined with the inter-copper chemical bond between the PVD copper and the electrochemically deposited copper provides for an enhanced seed layer having excellent electrical as well as barrier adhesion properties. Such characteristics are also desirable for films used in blanket plating, full-fill plating, pattern plating, etc.
  • [0057]
    It has been found that the resistivity of the deposited copper film is directly related to the resistivity of the plating bath solution. Additives that assist in lowering the resistivity of the solution therefore provide a corresponding reduction in the resistivity of the deposited film.
  • [0058]
    Experimental results indicate that addition of ammonium sulfate significantly reduces the resistivity of the plating bath solution and, as such, the deposited film. The sheet resistance obtained for different amounts of ammonium sulfate are compared in the graph FIG. 4C. As can be seen, the highest sheet resistance, either with or without annealing at high temperatures, was obtained in the bath containing no ammonium sulfate. If ammonium hydroxide was used to adjust pH in which a trace amount of ammonium sulfate is introduced to the bath, the sheet resistance was reduced from 76 to 23. As the concentration of ammonium sulfate increased from 0.1 M to 0.5 M, the sheet resistance continuously decreased in a corresponding manner.
  • [0059]
    Although ammonium sulfate assists in reducing the sheet resistance of the deposited copper layer, experimental results indicate that it reduces the conformality of the resulting copper film. However, the addition of ethylene glycol to the ammonium sulfate containing solution substantially increases the conformality of the resulting deposit. FIG. 4D illustrates the relationship between the concentration of ethylene glycol and the conductivity of a plating solution containing 0.2M of ammonium sulfate.
  • [0060]
    A preferred composition and range of concentrations for the various components of a plating bath having ammonium sulfate include the following:
      • 1. Copper sulfate: 0.03M to 0.5M (preferably, 0.25M);
      • 2. Complexing agent: complex to metal ratios from 1 to 4, preferably 2 using ED;
      • 3. Ammonium sulfate: 0.01M to 0.5M, preferably 0.3M; and
      • 4. Boric acid: 0.00 to 0.5M, preferably 0.2M.
        As noted above, such a bath composition can be used for blanket plating, pattern plating, full-fill plating, and seed layer enhancement.
  • [0065]
    With reference again to the specific seed layer enhanced aspects of the present invention, the enhanced seed layer of FIG. 2C is suitable for subsequent electrochemical copper deposition. This subsequent copper deposition may take place in an alkaline bath within the apparatus employed to enhance the seed layer. This may be followed by a low-temperature annealing process that assists in lowering the resistivity of the deposited copper. Such a low-temperature annealing process preferably takes place at a temperature below about the 250 degrees Celsius and, more preferably, below about 100 degrees Celsius. When a low-K dielectric material is employed to isolate the copper structures, the upper annealing temperature limit should be chosen to be below the degradation temperature of the dielectric material.
  • [0066]
    Although the foregoing alkaline bath compositions may be used for the entire electrochemical deposition process, subsequent copper deposition may take place in an acid environment where plating rates are substantially higher than corresponding rates associated with alkaline plating baths. To this end, the semiconductor workpiece is preferably transferred to an apparatus wherein the workpiece is thoroughly rinsed with deionized water and then transferred to an apparatus similar to that of FIG. 3 wherein the plating bath is acidic. For example, one suitable copper bath comprises 170 g/l H2SO4, 17 g/l copper and 70 ppm Chloride ions with organic additives. The organic additives are not absolutely necessary to the plating reaction. Rather, the organic additives may be used to produce desired film characteristics and provide better filling of the recessed structures on the wafer surface. The organic additives may include levelers, brighteners, wetting agents and ductility enhancers. It is during this deposition process that the trench 5 is substantially filled with a further layer of electrochemically deposited copper 22. The resulting filled cross-section is illustrated in FIG. 2D. After being filled in this manner, the barrier layer and the copper layers disposed above the trench are removed using any suitable process thereby leaving only the trench 5 with the copper metallization and associated barrier material as shown in FIG. 2E.
  • [0067]
    Use of an alkaline electrolytic bath to enhance the copper seed layer has particular advantages over utilizing acid copper baths without seed layer enhancement. After deposition of the PVD copper seed layer, the copper seed layer is typically exposed to an oxygen-containing environment. Oxygen readily converts metallic copper to copper oxide. If an acid copper bath is used to plate copper onto the seed layer after exposure of the seed layer to an oxygen containing environment, the acid copper bath would dissolve copper oxide that had formed, resulting in voids in the seed layer and poor uniformity of the copper layer deposited on the seed layer. Use of an alkaline copper bath in accordance with the disclosed embodiment avoids the problem by advantageously reducing any copper oxide at the surface of the seed layer to metallic copper. Another advantage of the alkaline copper bath is that the plated copper has much better adhesion to the barrier layer than that plated from an acid copper bath. Additional advantages of the seed layer enhancement aspects of the present invention can be seen from the following Example.
  • EXAMPLE 1
  • [0068]
    Comparison of Acid Copper Plating With and Without Seed Layer Enhancement
  • [0069]
    Semiconductor wafers 1, 2 and 3 were each coated with a 200 Angstrom PVD copper seed layer. In accordance with the present invention, wafers 1 and 2 had seed layer enhancement from citric acid and EDTA baths, respectively, the compositions of which are set forth below:
      • Bath for Wafer 1: 0.1 M Cu SO4+0.2 M Citric acid+0.05 M H3B03 in D.I. water at pH 9.5, temperature 25° C.
      • Bath for Wafer 2: 0.1 M Cu SO4+0.2 M EDTA acid+0.05 H3BO3 in D.I. water at pH 12.5, temperature 25° C.
      • Wafer 3 did not have any seed layer enhancement.
  • [0073]
    The three wafers were then plated with a 1.5 micron copper layer from an acid copper bath under identical conditions. The following Table compares the uniformities, as deduced from sheet resistance measurements, of the three wafers after the deposition of a copper layer having a nominal thickness of 1.5 microns.
    TABLE 1
    Non-uniformity
    Enhancement Current Standard deviation
    Wafer Bath Density (%. 1o)
    1 Citrate 3 min. at 7.321
    2 mA/cm2
    2 EDTA 3 min. at 6.233
    2 mA/cm2
    3 None 0 46.10
  • [0074]
    As can be seen from the results in Table 1 above, seed layer enhancement in accordance with the disclosed process provides excellent uniformity (6 to 7%) compared to that without seed layer enhancement (46%). This is consistent with observations during visual examination of the wafer after 1.5 micron electroplated copper had been deposited. Such visual examination of the wafer revealed the presence of defects at wafer electrode contact points on the wafer without seed layer enhancement.
  • [0075]
    FIGS. 5, 6A and 6B are photographs taken using a SEM. In FIG. 5, an ultra-thin seed layer has been deposited on the surface of a semiconductor wafer, including micro-structures, such as trenches 85. As shown, void regions are present at the lower corners of the trenches. In FIG. 6A, the seed layer has been enhanced in the manner described above in a bath containing citric acid as the complexing agent. This enhancement resulted in a conformal copper seed layer that is very suited for subsequent electrochemical deposition of copper metallization.
  • [0076]
    FIG. 6B illustrates a seed layer that has been enhanced in a bath containing EDTA as the complexing agent. The resulting seed layer includes larger grain sizes that project as spikes from the sidewalls of the trenches. These sidewall grain projections make subsequent electrochemical deposition filling of the trenches more difficult since they localize a higher plating rate resulting in non-uniformity of the subsequent electrochemical deposition. This effect is particularly noticeable in recessed micro-structures having small dimensions. As such, a complexing agent such as citric acid is more preferable when filling small micro-structures. Results comparable for copper baths containing citric acid have also been achieved using ED as the complexing agent.
  • [0077]
    FIG. 7 is a schematic representation of a section of a semiconductor manufacturing line 90 suitable for implementing the foregoing processes. The line 90 includes a vapor deposition tool or tool set 95 and an electrochemical copper deposition tool or tool set 100. Transfer of wafers between the tools/tool sets 95 and 100 may be implemented manually or through an automated transfer mechanism 105. Preferably, automated transfer mechanism 105 transfers workpieces in a pod or similar environment. Alternatively, the transfer mechanism 105 may transfer wafers individually or in an open carrier through a clean atmosphere joining the tools/tool sets.
  • [0078]
    In operation, vapor deposition tool/tool set 95 is utilized to apply an ultra-thin copper seed layer over at least portions of semiconductor workpieces that are processed on line 90. Preferably, this is done using a PVD application process. Workpieces with the ultra-thin seed layer are then transferred to tool/tool set 100, either individually or in batches, where they are subject to electrochemical seed layer enhancement at, for example, processing station 110. Processing station 110 may be constructed in the manner set forth in FIG. 3. After enhancement is completed, the workpieces are subject to a full electrochemical deposition process in which copper metallization is applied to the workpiece to a desired interconnect metallization thickness. This latter process may take place at station 110, but preferably occurs at further processing station 115 which deposits the copper metallization in the presence of an acidic plating bath. Before transfer to station 115, the workpiece is preferably rinsed in DI water at station 112. Transfer of the wafers between stations 110, 112, and 115 may be automated by a wafer conveying system 120. The electrochemical deposition tool set 100 may be implemented using, for example, an LT-210™ model or an Equinox™ model plating tool available from Semitool, Inc., of Kalispell, Mont.
  • [0079]
    Numerous modifications may be made to the foregoing system without departing from the basic teachings thereof. Although the present invention has been described in substantial detail with reference to one or more specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the scope and spirit of the invention as set forth in the appended claims.

Claims (26)

  1. 1-5. (canceled)
  2. 6. A process for applying a metal structure to a workpiece comprising:
    providing a workpiece on which one or more microelectronic devices are to be formed, the workpiece having a barrier layer wherein at least a portion of a surface of the barrier layer is uncovered;
    providing a first electroplating bath including a source of copper ions as a principal species to be deposited, the first electroplating bath comprising an alkaline bath;
    exposing at least a portion of the surface of the barrier layer to the first electroplating bath; and
    applying electroplating power between at least one surface of the workpiece and an electrode disposed in electrical contact with the first electroplating bath to electroplate a copper seed layer directly onto at least a portion of the surface of the barrier layer in a first electrolytic deposition process, wherein power is applied during at least a portion of the first deposition process for a workpiece surface current density of between about 1.0 mA/cm2 and about 5.0 mA/cm2.
  3. 7. The process of claim 6, wherein power is applied during at least a portion of the first deposition process at a workpiece surface current density of about 2.0 mA/cm2.
  4. 8. The process of claim 6, wherein power is applied at a workpiece surface current density of between 1.0 mA/cm2 and 5.0 mA/cm2 over a time period of between 1.0 and 5.0 minutes.
  5. 9. The process of claim 6, wherein power is applied in periodic pulses during deposition.
  6. 10. The process of claim 9, wherein power is applied in forward pulses having a period of about 2 msec at a 50% duty cycle.
  7. 11. The process of claim 6, further comprising depositing additional copper onto the copper seed layer deposited in the first deposition process using a second deposition process that is different than the first electrolytic deposition process.
  8. 12. The process of claim 6, wherein the copper seed layer comprises a copper alloy.
  9. 13. The process of claim 11, wherein the second deposition process occurs in an acidic electrolytic bath.
  10. 14. The process of claim 11, wherein metal is deposited in the second deposition process at a higher rate than in the first deposition process.
  11. 15. The process of claim 6, wherein the source of copper ions comprises copper sulfate included at a level of from about 0.03 to about 0.25 M.
  12. 16. The process of claim 6, wherein the first electroplating bath further comprises boric acid and a metal ion complexing agent.
  13. 17. The process of claim 6, wherein the alkaline bath has a pH of at least about 9.0.
  14. 18. The process of claim 6, further comprising performing a second electroplating deposition using a second electroplating bath having a different composition than the first electroplating bath, to deposit additional copper onto the copper seed layer.
  15. 19. The process of claim 6, wherein the alkaline bath is pH adjusted with an alkaline agent comprising potassium hydroxide, tetramethylammonium hydroxide, sodium hydroxide, ammonium hydroxide, an organic hydroxide, or mixtures thereof.
  16. 20. The process of claim 16, wherein the metal ion complexing agent comprises EDTA, ED, polycarboxylic acid, or mixtures thereof.
  17. 21. The process of claim 19, wherein the complexing agent comprises ED and wherein the ED in the electrolytic bath has a concentration within the range of from about 0.03 to about 1.0 M.
  18. 22. The process of claim 16, wherein the complexing agent is citric acid.
  19. 23. The process of claim 6, wherein the source of metal ions comprises copper sulfate and the complexing agent comprises ED.
  20. 24. The process of claim 22, further comprising tetramethylammonium hydroxide in an amount sufficient to adjust the pH of the first electroplating bath to at least about 9.0.
  21. 25. A process for applying a metal structure to a workpiece comprising:
    providing a workpiece on which one or more microelectronic devices are to be formed, the workpiece having a barrier layer wherein at least a portion of a surface of the barrier layer is uncovered;
    providing a first electroplating bath including a source of copper ions to be deposited, a metal ion complexing agent and an alkaline agent in an amount sufficient to adjust the pH of the bath to at least about 9.0;
    exposing at least a portion of the surface of the barrier layer to the first electroplating bath; and
    applying electroplating power between at least one surface of the workpiece and an electrode disposed in electrical contact with the first electroplating bath to electroplate a copper seed layer directly onto at least a portion of the surface of the barrier layer in a first electrolytic deposition process, wherein power is applied during at least a portion of the first deposition process for a workpiece surface current density of between about 1.0 mA/cm2 and about 5.0 mA/cm2.
  22. 26. A process for applying a metal structure to a workpiece comprising:
    providing a first electroplating bath including a source of copper ions to be deposited as a seed layer during subsequent electroplating, boric acid, and a metal ion complexing agent;
    providing a workpiece having a barrier layer, wherein at least a portion of a surface of the barrier layer is exposed;
    exposing at least a portion of the surface of the barrier layer to the first electroplating bath; and
    applying electroplating power between at least one surface of the workpiece and an electrode disposed in electrical contact with the first electroplating bath to electroplate a copper seed layer directly onto at least a portion of the surface of the barrier layer in an electrolytic first deposition process, wherein power is applied during at least a portion of the first deposition process in periodic pulses.
  23. 27. The process of claim 26, wherein the electroplating power is applied during at least a portion of the first deposition process for a workpiece surface current density of between about 1.0 mA/cm2 and about 5.0 mA/cm2.
  24. 28. The process of claim 26, wherein power is applied in forward pulses having a period of about 2 msec at a 50% duty cycle.
  25. 29. The process of claim 26, wherein pulsed power is applied for a period of from about 1.0 to about 5.0 minutes.
  26. 30. The process of claim 26, further comprising depositing additional copper metal onto the copper seed layer using a second deposition process that is different from the first deposition process.
US11067278 1998-03-20 2005-02-25 Apparatus and method for electrolytically depositing copper on a semiconductor workpiece Abandoned US20050139478A1 (en)

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US09387033 US6290833B1 (en) 1998-03-20 1999-08-31 Method for electrolytically depositing copper on a semiconductor workpiece
US09885232 US6811675B2 (en) 1998-03-20 2001-06-20 Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US10980618 US20050173252A1 (en) 1998-03-20 2004-11-02 Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090087800A1 (en) * 2007-09-28 2009-04-02 Fujifilm Corporation Method and apparatus for producing conductive material

Families Citing this family (155)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7126195B1 (en) 1996-06-03 2006-10-24 Micron Technology, Inc. Method for forming a metallization layer
US6752584B2 (en) * 1996-07-15 2004-06-22 Semitool, Inc. Transfer devices for handling microelectronic workpieces within an environment of a processing machine and methods of manufacturing and using such devices in the processing of microelectronic workpieces
US6921467B2 (en) * 1996-07-15 2005-07-26 Semitool, Inc. Processing tools, components of processing tools, and method of making and using same for electrochemical processing of microelectronic workpieces
US7244677B2 (en) 1998-02-04 2007-07-17 Semitool. Inc. Method for filling recessed micro-structures with metallization in the production of a microelectronic device
US6565729B2 (en) 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
US6197181B1 (en) * 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
WO1999047731A1 (en) 1998-03-20 1999-09-23 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
EP1091024A4 (en) 1998-04-30 2006-03-22 Ebara Corp Method and device for plating substrate
US6582578B1 (en) 1999-04-08 2003-06-24 Applied Materials, Inc. Method and associated apparatus for tilting a substrate upon entry for metal deposition
CA2702148C (en) * 1999-01-06 2014-03-04 Genenews Inc. Method of profiling gene expression in a human subject having an infectious disease
US6221763B1 (en) * 1999-04-05 2001-04-24 Micron Technology, Inc. Method of forming a metal seed layer for subsequent plating
US8852417B2 (en) 1999-04-13 2014-10-07 Applied Materials, Inc. Electrolytic process using anion permeable barrier
US20060189129A1 (en) * 2000-03-21 2006-08-24 Semitool, Inc. Method for applying metal features onto barrier layers using ion permeable barriers
US6916412B2 (en) * 1999-04-13 2005-07-12 Semitool, Inc. Adaptable electrochemical processing chamber
US20060157355A1 (en) * 2000-03-21 2006-07-20 Semitool, Inc. Electrolytic process using anion permeable barrier
US8236159B2 (en) 1999-04-13 2012-08-07 Applied Materials Inc. Electrolytic process using cation permeable barrier
WO2000061498A3 (en) 1999-04-13 2001-01-25 Semitool Inc System for electrochemically processing a workpiece
US6159853A (en) * 1999-08-04 2000-12-12 Industrial Technology Research Institute Method for using ultrasound for assisting forming conductive layers on semiconductor devices
US6413858B1 (en) 1999-08-27 2002-07-02 Micron Technology, Inc. Barrier and electroplating seed layer
US6423200B1 (en) 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
US8372757B2 (en) 2003-10-20 2013-02-12 Novellus Systems, Inc. Wet etching methods for copper removal and planarization in semiconductor processing
US6440849B1 (en) * 1999-10-18 2002-08-27 Agere Systems Guardian Corp. Microstructure control of copper interconnects
EP1111096A3 (en) * 1999-12-15 2004-02-11 Shipley Company, L.L.C. Seed layer repair method
US6650957B1 (en) * 2000-01-03 2003-11-18 Advanced Micro Devices, Inc. Method and apparatus for run-to-run control of deposition process
US6376370B1 (en) 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6582579B1 (en) * 2000-03-24 2003-06-24 Nutool, Inc. Methods for repairing defects on a semiconductor substrate
EP1139396A3 (en) * 2000-03-31 2003-08-27 Texas Instruments Incorporated Fixture and method for uniform electroless metal deposition on integrated circuit bond pads
US6913680B1 (en) 2000-05-02 2005-07-05 Applied Materials, Inc. Method of application of electrical biasing to enhance metal deposition
US6808612B2 (en) 2000-05-23 2004-10-26 Applied Materials, Inc. Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio
US20050145499A1 (en) * 2000-06-05 2005-07-07 Applied Materials, Inc. Plating of a thin metal seed layer
US6709563B2 (en) * 2000-06-30 2004-03-23 Ebara Corporation Copper-plating liquid, plating method and plating apparatus
US20020090484A1 (en) * 2000-10-20 2002-07-11 Shipley Company, L.L.C. Plating bath
US6660153B2 (en) * 2000-10-20 2003-12-09 Shipley Company, L.L.C. Seed layer repair bath
US6824665B2 (en) * 2000-10-25 2004-11-30 Shipley Company, L.L.C. Seed layer deposition
US6660154B2 (en) 2000-10-25 2003-12-09 Shipley Company, L.L.C. Seed layer
US6797146B2 (en) 2000-11-02 2004-09-28 Shipley Company, L.L.C. Seed layer repair
EP1215305B1 (en) 2000-12-13 2010-05-05 Imec Method for preparing an electroplating bath and related copper plating process
US20040072423A1 (en) * 2001-01-12 2004-04-15 Jacob Jorne Methods and systems for electro-or electroless-plating of metal in high-aspect ratio features
JP2002289559A (en) * 2001-02-01 2002-10-04 Texas Instr Inc <Ti> Production method for integrated circuit
JP2004519557A (en) * 2001-02-23 2004-07-02 株式会社荏原製作所 Copper plating solution, plating method and a plating apparatus
US6730857B2 (en) 2001-03-13 2004-05-04 International Business Machines Corporation Structure having laser ablated features and method of fabricating
US6740221B2 (en) 2001-03-15 2004-05-25 Applied Materials Inc. Method of forming copper interconnects
CN1247824C (en) 2001-04-04 2006-03-29 皇家菲利浦电子有限公司 Back-end metallisation process
US6506668B1 (en) * 2001-06-22 2003-01-14 Advanced Micro Devices, Inc. Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
US6664122B1 (en) 2001-10-19 2003-12-16 Novellus Systems, Inc. Electroless copper deposition method for preparing copper seed layers
EP1453991A4 (en) * 2001-12-13 2007-12-05 Ebara Corp Electrolytic processing apparatus and method
WO2003060959A3 (en) * 2002-01-10 2004-03-25 Semitool Inc Method for applying metal features onto barrier layers using electrochemical deposition
WO2003063067A1 (en) * 2002-01-24 2003-07-31 Chatterbox Systems, Inc. Method and system for locating positions in printed texts and delivering multimedia information
US20040206634A1 (en) * 2002-01-31 2004-10-21 Mitsuhiko Shirakashi Electrolytic processing apparatus and substrate processing apparatus and method
WO2003085713A1 (en) * 2002-04-03 2003-10-16 Applied Materials, Inc. Homogeneous copper-tin alloy plating for enhancement of electro-migration resistance in interconnects
US6911136B2 (en) * 2002-04-29 2005-06-28 Applied Materials, Inc. Method for regulating the electrical power applied to a substrate during an immersion process
US20030201185A1 (en) * 2002-04-29 2003-10-30 Applied Materials, Inc. In-situ pre-clean for electroplating process
US6893505B2 (en) * 2002-05-08 2005-05-17 Semitool, Inc. Apparatus and method for regulating fluid flows, such as flows of electrochemical processing fluids
US6875331B2 (en) * 2002-07-11 2005-04-05 Applied Materials, Inc. Anode isolation by diffusion differentials
US7223323B2 (en) * 2002-07-24 2007-05-29 Applied Materials, Inc. Multi-chemistry plating system
US7128823B2 (en) * 2002-07-24 2006-10-31 Applied Materials, Inc. Anolyte for copper plating
US7247222B2 (en) * 2002-07-24 2007-07-24 Applied Materials, Inc. Electrochemical processing cell
US20040217005A1 (en) * 2002-07-24 2004-11-04 Aron Rosenfeld Method for electroplating bath chemistry control
US7025866B2 (en) * 2002-08-21 2006-04-11 Micron Technology, Inc. Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces
US7897198B1 (en) 2002-09-03 2011-03-01 Novellus Systems, Inc. Electroless layer plating process and apparatus
US20040118699A1 (en) * 2002-10-02 2004-06-24 Applied Materials, Inc. Homogeneous copper-palladium alloy plating for enhancement of electro-migration resistance in interconnects
DE10254815A1 (en) * 2002-11-23 2004-06-09 Infineon Technologies Ag A method for electrodepositing a metal, particularly of copper, using this method and integrated circuit arrangement
US7902062B2 (en) 2002-11-23 2011-03-08 Infineon Technologies Ag Electrodepositing a metal in integrated circuit applications
US7147767B2 (en) * 2002-12-16 2006-12-12 3M Innovative Properties Company Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor
US6858124B2 (en) * 2002-12-16 2005-02-22 3M Innovative Properties Company Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
US6884338B2 (en) * 2002-12-16 2005-04-26 3M Innovative Properties Company Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
US7198705B2 (en) * 2002-12-19 2007-04-03 Texas Instruments Incorporated Plating-rinse-plating process for fabricating copper interconnects
US20040154926A1 (en) * 2002-12-24 2004-08-12 Zhi-Wen Sun Multiple chemistry electrochemical plating method
US20040200725A1 (en) * 2003-04-09 2004-10-14 Applied Materials Inc. Application of antifoaming agent to reduce defects in a semiconductor electrochemical plating process
US20040206628A1 (en) * 2003-04-18 2004-10-21 Applied Materials, Inc. Electrical bias during wafer exit from electrolyte bath
US7473339B2 (en) * 2003-04-18 2009-01-06 Applied Materials, Inc. Slim cell platform plumbing
US7311810B2 (en) * 2003-04-18 2007-12-25 Applied Materials, Inc. Two position anneal chamber
US7297247B2 (en) * 2003-05-06 2007-11-20 Applied Materials, Inc. Electroformed sputtering target
US20040253386A1 (en) * 2003-06-13 2004-12-16 Sarojini Deevi Preparation of intermetallics by metallo-organic decomposition
KR100545192B1 (en) * 2003-06-19 2006-01-24 동부아남반도체 주식회사 Deposition stop time detect apparatus and copper wiring formation apparatus of semiconductor device using the same
US20060283716A1 (en) * 2003-07-08 2006-12-21 Hooman Hafezi Method of direct plating of copper on a ruthenium alloy
US20050006245A1 (en) * 2003-07-08 2005-01-13 Applied Materials, Inc. Multiple-step electrodeposition process for direct copper plating on barrier metals
US20070125657A1 (en) * 2003-07-08 2007-06-07 Zhi-Wen Sun Method of direct plating of copper on a substrate structure
US7273535B2 (en) * 2003-09-17 2007-09-25 Applied Materials, Inc. Insoluble anode with an auxiliary electrode
US7654221B2 (en) 2003-10-06 2010-02-02 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US20050109627A1 (en) * 2003-10-10 2005-05-26 Applied Materials, Inc. Methods and chemistry for providing initial conformal electrochemical deposition of copper in sub-micron features
US20050085031A1 (en) * 2003-10-15 2005-04-21 Applied Materials, Inc. Heterogeneous activation layers formed by ionic and electroless reactions used for IC interconnect capping layers
US20050081744A1 (en) * 2003-10-16 2005-04-21 Semitool, Inc. Electroplating compositions and methods for electroplating
US7972970B2 (en) 2003-10-20 2011-07-05 Novellus Systems, Inc. Fabrication of semiconductor interconnect structure
US7338908B1 (en) 2003-10-20 2008-03-04 Novellus Systems, Inc. Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage
US20050092616A1 (en) * 2003-11-03 2005-05-05 Semitool, Inc. Baths, methods, and tools for superconformal deposition of conductive materials other than copper
US20050092611A1 (en) * 2003-11-03 2005-05-05 Semitool, Inc. Bath and method for high rate copper deposition
US7205233B2 (en) 2003-11-07 2007-04-17 Applied Materials, Inc. Method for forming CoWRe alloys by electroless deposition
US7827930B2 (en) * 2004-01-26 2010-11-09 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US20050284751A1 (en) * 2004-06-28 2005-12-29 Nicolay Kovarsky Electrochemical plating cell with a counter electrode in an isolated anolyte compartment
US7214297B2 (en) 2004-06-28 2007-05-08 Applied Materials, Inc. Substrate support element for an electrochemical plating cell
US20060045666A1 (en) * 2004-07-09 2006-03-02 Harris Randy A Modular tool unit for processing of microfeature workpieces
JP4376903B2 (en) 2005-01-25 2009-12-02 日鉱金属株式会社 Electrolytic copper foil produced copper electrolyte and thereby comprises a compound having a specific skeleton as an additive
US20060162658A1 (en) * 2005-01-27 2006-07-27 Applied Materials, Inc. Ruthenium layer deposition apparatus and method
US7438949B2 (en) * 2005-01-27 2008-10-21 Applied Materials, Inc. Ruthenium containing layer deposition method
US7514353B2 (en) 2005-03-18 2009-04-07 Applied Materials, Inc. Contact metallization scheme using a barrier layer over a silicide layer
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US20060246217A1 (en) 2005-03-18 2006-11-02 Weidman Timothy W Electroless deposition process on a silicide contact
FR2890983B1 (en) * 2005-09-20 2007-12-14 Alchimer Sa Electrodeposition composition for coating a surface of a substrate by a metal.
FR2890984B1 (en) * 2005-09-20 2009-03-27 Alchimer Sa Electrodeposition method for coating a surface of a substrate by a metal.
WO2007035880A3 (en) * 2005-09-21 2007-10-25 Applied Materials Inc Method and apparatus for forming device features in an integrated electroless deposition system
US7456102B1 (en) 2005-10-11 2008-11-25 Novellus Systems, Inc. Electroless copper fill process
US7605082B1 (en) 2005-10-13 2009-10-20 Novellus Systems, Inc. Capping before barrier-removal IC fabrication method
US9127362B2 (en) 2005-10-31 2015-09-08 Applied Materials, Inc. Process kit and target for substrate processing chamber
US8647484B2 (en) 2005-11-25 2014-02-11 Applied Materials, Inc. Target for sputtering chamber
US7579274B2 (en) * 2006-02-21 2009-08-25 Alchimer Method and compositions for direct copper plating and filing to form interconnects in the fabrication of semiconductor devices
US7655126B2 (en) 2006-03-27 2010-02-02 Federal Mogul World Wide, Inc. Fabrication of topical stopper on MLS gasket by active matrix electrochemical deposition
EP1845554A3 (en) * 2006-04-10 2011-07-13 Imec A method to create super secondary grain growth in narrow trenches
US7799684B1 (en) 2007-03-05 2010-09-21 Novellus Systems, Inc. Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers
US20080264774A1 (en) * 2007-04-25 2008-10-30 Semitool, Inc. Method for electrochemically depositing metal onto a microelectronic workpiece
US8968536B2 (en) 2007-06-18 2015-03-03 Applied Materials, Inc. Sputtering target having increased life and sputtering uniformity
US7901552B2 (en) 2007-10-05 2011-03-08 Applied Materials, Inc. Sputtering target with grooves and intersecting channels
US8237892B1 (en) 2007-11-30 2012-08-07 Sipix Imaging, Inc. Display device with a brightness enhancement structure
US7830592B1 (en) * 2007-11-30 2010-11-09 Sipix Imaging, Inc. Display devices having micro-reflectors
US8118988B2 (en) * 2008-01-31 2012-02-21 Eci Technology, Inc. Analysis of copper ion and complexing agent in copper plating baths
US8703615B1 (en) 2008-03-06 2014-04-22 Novellus Systems, Inc. Copper electroplating process for uniform across wafer deposition and void free filling on ruthenium coated wafers
US8513124B1 (en) 2008-03-06 2013-08-20 Novellus Systems, Inc. Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers
US7964506B1 (en) * 2008-03-06 2011-06-21 Novellus Systems, Inc. Two step copper electroplating process with anneal for uniform across wafer deposition and void free filling on ruthenium coated wafers
US8437069B2 (en) * 2008-03-11 2013-05-07 Sipix Imaging, Inc. Luminance enhancement structure for reflective display devices
US8395836B2 (en) 2008-03-11 2013-03-12 Sipix Imaging, Inc. Luminance enhancement structure for reflective display devices
US8107254B2 (en) * 2008-11-20 2012-01-31 International Business Machines Corporation Integrating capacitors into vias of printed circuit boards
US8441414B2 (en) * 2008-12-05 2013-05-14 Sipix Imaging, Inc. Luminance enhancement structure with Moiré reducing design
US9025234B2 (en) * 2009-01-22 2015-05-05 E Ink California, Llc Luminance enhancement structure with varying pitches
CN102395712A (en) 2009-02-12 2012-03-28 技术研究及发展基金有限公司 A process for electroplating of copper
US8120836B2 (en) * 2009-03-09 2012-02-21 Sipix Imaging, Inc. Luminance enhancement structure for reflective display devices
US8714780B2 (en) * 2009-04-22 2014-05-06 Sipix Imaging, Inc. Display devices with grooved luminance enhancement film
JP5388191B2 (en) * 2009-05-26 2014-01-15 Jx日鉱日石金属株式会社 Plated and method of forming a through-silicon via
US8797633B1 (en) 2009-07-23 2014-08-05 Sipix Imaging, Inc. Display device assembly and manufacture thereof
US8456589B1 (en) 2009-07-27 2013-06-04 Sipix Imaging, Inc. Display device assembly
CN102484061B (en) 2009-09-02 2015-08-19 诺发系统有限公司 Isotropic etchant to reduce material consumption and waste generation
US8242384B2 (en) 2009-09-30 2012-08-14 International Business Machines Corporation Through hole-vias in multi-layer printed circuit boards
JP2011097038A (en) * 2009-10-02 2011-05-12 Ibiden Co Ltd Ceramic wiring substrate and manufacturing method of the same
US8432027B2 (en) * 2009-11-11 2013-04-30 International Business Machines Corporation Integrated circuit die stacks with rotationally symmetric vias
US8315068B2 (en) * 2009-11-12 2012-11-20 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same
US8310841B2 (en) 2009-11-12 2012-11-13 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same
US8258619B2 (en) * 2009-11-12 2012-09-04 International Business Machines Corporation Integrated circuit die stacks with translationally compatible vias
US9646947B2 (en) * 2009-12-22 2017-05-09 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Integrated circuit with inductive bond wires
US8168540B1 (en) 2009-12-29 2012-05-01 Novellus Systems, Inc. Methods and apparatus for depositing copper on tungsten
US20110192462A1 (en) * 2010-01-03 2011-08-11 Alchimer, S.A. Solar cells
US20110162701A1 (en) * 2010-01-03 2011-07-07 Claudio Truzzi Photovoltaic Cells
JP5750626B2 (en) * 2010-03-19 2015-07-22 石原ケミカル株式会社 Electrolytic copper plating method
US9714474B2 (en) * 2010-04-06 2017-07-25 Tel Nexx, Inc. Seed layer deposition in microscale features
US9017528B2 (en) 2011-04-14 2015-04-28 Tel Nexx, Inc. Electro chemical deposition and replenishment apparatus
US9005409B2 (en) 2011-04-14 2015-04-14 Tel Nexx, Inc. Electro chemical deposition and replenishment apparatus
US8575028B2 (en) 2011-04-15 2013-11-05 Novellus Systems, Inc. Method and apparatus for filling interconnect structures
CN102251269B (en) * 2011-08-19 2013-07-03 银都餐饮设备股份有限公司 Electrochemical surface treatment device
JP6021441B2 (en) 2012-05-25 2016-11-09 ラピスセミコンダクタ株式会社 Semiconductor device
US9303329B2 (en) 2013-11-11 2016-04-05 Tel Nexx, Inc. Electrochemical deposition apparatus with remote catholyte fluid management
WO2015108784A1 (en) * 2014-01-15 2015-07-23 The Board Of Trustees Of The Leland Stanford Junior University A method for plating fine grain copper deposit on metal substrate
KR20150130122A (en) * 2014-05-13 2015-11-23 삼성전기주식회사 Electrode structure
CN104313657A (en) * 2014-11-10 2015-01-28 临安振有电子有限公司 Electro-deposition device of through hole of HDI printed circuit board
DE102016113641A1 (en) 2016-07-25 2018-01-25 Christian-Albrechts-Universität Zu Kiel Aluminum-copper connector comprising a heterostructure and methods for making the heterostructure
JP6272431B2 (en) * 2016-10-04 2018-01-31 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof

Citations (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1526644A (en) * 1922-10-25 1925-02-17 Williams Brothers Mfg Company Process of electroplating and apparatus therefor
US2742412A (en) * 1952-07-05 1956-04-17 Metallic Industry Nv Electrolytic deposition of copper
US3309263A (en) * 1964-12-03 1967-03-14 Kimberly Clark Co Web pickup and transfer for a papermaking machine
US3495940A (en) * 1967-09-28 1970-02-17 Celanese Corp Production of high temperature resistant continuous filaments
US3716462A (en) * 1970-10-05 1973-02-13 D Jensen Copper plating on zinc and its alloys
US3798003A (en) * 1972-02-14 1974-03-19 E Ensley Differential microcalorimeter
US3878066A (en) * 1972-09-06 1975-04-15 Manfred Dettke Bath for galvanic deposition of gold and gold alloys
US3930963A (en) * 1971-07-29 1976-01-06 Photocircuits Division Of Kollmorgen Corporation Method for the production of radiant energy imaged printed circuit boards
US4072557A (en) * 1974-12-23 1978-02-07 J. M. Voith Gmbh Method and apparatus for shrinking a travelling web of fibrous material
US4082638A (en) * 1974-09-19 1978-04-04 Jumer John F Apparatus for incremental electro-processing of large areas
US4134802A (en) * 1977-10-03 1979-01-16 Oxy Metal Industries Corporation Electrolyte and method for electrodepositing bright metal deposits
US4137867A (en) * 1977-09-12 1979-02-06 Seiichiro Aigo Apparatus for bump-plating semiconductor wafers
US4246088A (en) * 1979-01-24 1981-01-20 Metal Box Limited Method and apparatus for electrolytic treatment of containers
US4259166A (en) * 1980-03-31 1981-03-31 Rca Corporation Shield for plating substrate
US4323433A (en) * 1980-09-22 1982-04-06 The Boeing Company Anodizing process employing adjustable shield for suspended cathode
US4378283A (en) * 1981-07-30 1983-03-29 National Semiconductor Corporation Consumable-anode selective plating apparatus
US4431361A (en) * 1980-09-02 1984-02-14 Heraeus Quarzschmelze Gmbh Methods of and apparatus for transferring articles between carrier members
US4437943A (en) * 1980-07-09 1984-03-20 Olin Corporation Method and apparatus for bonding metal wire to a base metal substrate
US4440597A (en) * 1982-03-15 1984-04-03 The Procter & Gamble Company Wet-microcontracted paper and concomitant process
US4443117A (en) * 1980-09-26 1984-04-17 Terumo Corporation Measuring apparatus, method of manufacture thereof, and method of writing data into same
US4495453A (en) * 1981-06-26 1985-01-22 Fujitsu Fanuc Limited System for controlling an industrial robot
US4495153A (en) * 1981-06-12 1985-01-22 Nissan Motor Company, Limited Catalytic converter for treating engine exhaust gases
US4500394A (en) * 1984-05-16 1985-02-19 At&T Technologies, Inc. Contacting a surface for plating thereon
US4566847A (en) * 1982-03-01 1986-01-28 Kabushiki Kaisha Daini Seikosha Industrial robot
US4576685A (en) * 1985-04-23 1986-03-18 Schering Ag Process and apparatus for plating onto articles
US4576689A (en) * 1979-06-19 1986-03-18 Makkaev Almaxud M Process for electrochemical metallization of dielectrics
US4585539A (en) * 1982-08-17 1986-04-29 Technic, Inc. Electrolytic reactor
US4634503A (en) * 1984-06-27 1987-01-06 Daniel Nogavich Immersion electroplating system
US4639028A (en) * 1984-11-13 1987-01-27 Economic Development Corporation High temperature and acid resistant wafer pick up device
US4648944A (en) * 1985-07-18 1987-03-10 Martin Marietta Corporation Apparatus and method for controlling plating induced stress in electroforming and electroplating processes
US4800818A (en) * 1985-11-02 1989-01-31 Hitachi Kiden Kogyo Kabushiki Kaisha Linear motor-driven conveyor means
US4898647A (en) * 1985-12-24 1990-02-06 Gould, Inc. Process and apparatus for electroplating copper foil
US4902398A (en) * 1988-04-27 1990-02-20 American Thim Film Laboratories, Inc. Computer program for vacuum coating systems
US4906341A (en) * 1987-09-24 1990-03-06 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and apparatus therefor
US4913085A (en) * 1985-01-01 1990-04-03 Esb Elektorstatische Spruh-Und Beschichtungsanlagen G.F. Vohringer Gmbh Coating booth for applying a coating powder to the surface of workpieces
US4988533A (en) * 1988-05-27 1991-01-29 Texas Instruments Incorporated Method for deposition of silicon oxide on a wafer
US4990224A (en) * 1988-12-21 1991-02-05 International Business Machines Corporation Copper plating bath and process for difficult to plate metals
US5000827A (en) * 1990-01-02 1991-03-19 Motorola, Inc. Method and apparatus for adjusting plating solution flow characteristics at substrate cathode periphery to minimize edge effect
US5078852A (en) * 1990-10-12 1992-01-07 Microelectronics And Computer Technology Corporation Plating rack
US5083364A (en) * 1987-10-20 1992-01-28 Convac Gmbh System for manufacturing semiconductor substrates
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US5178512A (en) * 1991-04-01 1993-01-12 Equipe Technologies Precision robot apparatus
US5178639A (en) * 1990-06-28 1993-01-12 Tokyo Electron Sagami Limited Vertical heat-treating apparatus
US5180273A (en) * 1989-10-09 1993-01-19 Kabushiki Kaisha Toshiba Apparatus for transferring semiconductor wafers
US5183377A (en) * 1988-05-31 1993-02-02 Mannesmann Ag Guiding a robot in an array
US5186594A (en) * 1990-04-19 1993-02-16 Applied Materials, Inc. Dual cassette load lock
US5284548A (en) * 1993-03-03 1994-02-08 Microelectronics And Computer Technology Corporation Process for producing electrical circuits with precision surface features
US5301700A (en) * 1992-03-05 1994-04-12 Tokyo Electron Limited Washing system
US5302464A (en) * 1991-03-04 1994-04-12 Kanegafuchi Kagaku Kogyo Kabushiki Kaisha Method of plating a bonded magnet and a bonded magnet carrying a metal coating
US5306895A (en) * 1991-03-26 1994-04-26 Ngk Insulators, Ltd. Corrosion-resistant member for chemical apparatus using halogen series corrosive gas
US5377708A (en) * 1989-03-27 1995-01-03 Semitool, Inc. Multi-station semiconductor processor with volatilization
US5388945A (en) * 1992-08-04 1995-02-14 International Business Machines Corporation Fully automated and computerized conveyor based manufacturing line architectures adapted to pressurized sealable transportable containers
US5391285A (en) * 1994-02-25 1995-02-21 Motorola, Inc. Adjustable plating cell for uniform bump plating of semiconductor wafers
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5405518A (en) * 1994-04-26 1995-04-11 Industrial Technology Research Institute Workpiece holder apparatus
US5409587A (en) * 1993-09-16 1995-04-25 Micron Technology, Inc. Sputtering with collinator cleaning within the sputtering chamber
US5482891A (en) * 1995-03-17 1996-01-09 Motorola, Inc. VCSEL with an intergrated heat sink and method of making
US5489341A (en) * 1993-08-23 1996-02-06 Semitool, Inc. Semiconductor processing with non-jetting fluid stream discharge array
US5500081A (en) * 1990-05-15 1996-03-19 Bergman; Eric J. Dynamic semiconductor wafer processing using homogeneous chemical vapors
US5501768A (en) * 1992-04-17 1996-03-26 Kimberly-Clark Corporation Method of treating papermaking fibers for making tissue
US5508095A (en) * 1993-11-16 1996-04-16 Scapa Group Plc Papermachine clothing
US5593545A (en) * 1995-02-06 1997-01-14 Kimberly-Clark Corporation Method for making uncreped throughdried tissue products without an open draw
US5597836A (en) * 1991-09-03 1997-01-28 Dowelanco N-(4-pyridyl) (substituted phenyl) acetamide pesticides
US5597460A (en) * 1995-11-13 1997-01-28 Reynolds Tech Fabricators, Inc. Plating cell having laminar flow sparger
US5600532A (en) * 1994-04-11 1997-02-04 Ngk Spark Plug Co., Ltd. Thin-film condenser
US5609239A (en) * 1994-03-21 1997-03-11 Thyssen Aufzuege Gmbh Locking system
US5711646A (en) * 1994-10-07 1998-01-27 Tokyo Electron Limited Substrate transfer apparatus
US5719447A (en) * 1993-06-03 1998-02-17 Intel Corporation Metal alloy interconnections for integrated circuits
US5723028A (en) * 1990-08-01 1998-03-03 Poris; Jaime Electrodeposition apparatus with virtual anode
US5723387A (en) * 1996-07-22 1998-03-03 Industrial Technology Research Institute Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates
US5731678A (en) * 1996-07-15 1998-03-24 Semitool, Inc. Processing head for semiconductor processing machines
US5730854A (en) * 1996-05-30 1998-03-24 Enthone-Omi, Inc. Alkoxylated dimercaptans as copper additives and de-polarizing additives
US5871626A (en) * 1995-09-27 1999-02-16 Intel Corporation Flexible continuous cathode contact circuit for electrolytic plating of C4, TAB microbumps, and ultra large scale interconnects
US5871805A (en) * 1996-04-08 1999-02-16 Lemelson; Jerome Computer controlled vapor deposition processes
US5882498A (en) * 1997-10-16 1999-03-16 Advanced Micro Devices, Inc. Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
US6028986A (en) * 1995-11-10 2000-02-22 Samsung Electronics Co., Ltd. Methods of designing and fabricating intergrated circuits which take into account capacitive loading by the intergrated circuit potting material
US6027631A (en) * 1997-11-13 2000-02-22 Novellus Systems, Inc. Electroplating system with shields for varying thickness profile of deposited layer
US6036836A (en) * 1996-12-20 2000-03-14 Peeters; Joris Antonia Franciscus Process to create metallic stand-offs on an electronic circuit
US6168695B1 (en) * 1999-07-12 2001-01-02 Daniel J. Woodruff Lift and rotate assembly for use in a workpiece processing station and a method of attaching the same
US6174796B1 (en) * 1998-01-30 2001-01-16 Fujitsu Limited Semiconductor device manufacturing method
US6174425B1 (en) * 1997-05-14 2001-01-16 Motorola, Inc. Process for depositing a layer of material over a substrate
US6179983B1 (en) * 1997-11-13 2001-01-30 Novellus Systems, Inc. Method and apparatus for treating surface including virtual anode
US6184068B1 (en) * 1994-06-02 2001-02-06 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor device
US6193859B1 (en) * 1997-11-13 2001-02-27 Novellus Systems, Inc. Electric potential shaping apparatus for holding a semiconductor wafer during electroplating
US6197181B1 (en) * 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
US6199301B1 (en) * 1997-01-22 2001-03-13 Industrial Automation Services Pty. Ltd. Coating thickness control
US20020008036A1 (en) * 1998-02-12 2002-01-24 Hui Wang Plating apparatus and method
US20020032499A1 (en) * 1999-04-13 2002-03-14 Wilson Gregory J. Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece
US20030038035A1 (en) * 2001-05-30 2003-02-27 Wilson Gregory J. Methods and systems for controlling current in electrochemical processing of microelectronic workpieces
US6531046B2 (en) * 1999-12-15 2003-03-11 Shipley Company, L.L.C. Seed layer repair method
US6672820B1 (en) * 1996-07-15 2004-01-06 Semitool, Inc. Semiconductor processing apparatus having linear conveyer system
US6678055B2 (en) * 2001-11-26 2004-01-13 Tevet Process Control Technologies Ltd. Method and apparatus for measuring stress in semiconductor wafers
US20040031693A1 (en) * 1998-03-20 2004-02-19 Chen Linlin Apparatus and method for electrochemically depositing metal on a semiconductor workpiece
US6699373B2 (en) * 1998-07-10 2004-03-02 Semitool, Inc. Apparatus for processing the surface of a microelectronic workpiece
US6709562B1 (en) * 1995-12-29 2004-03-23 International Business Machines Corporation Method of making electroplated interconnection structures on integrated circuit chips
US20040055877A1 (en) * 1999-04-13 2004-03-25 Wilson Gregory J. Workpiece processor having processing chamber with improved processing fluid flow

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2411674A (en) * 1943-03-04 1946-11-26 Little Inc A Art of electrodeposition of copper
NL291575A (en) 1962-04-16
US3328273A (en) 1966-08-15 1967-06-27 Udylite Corp Electro-deposition of copper from acidic baths
US3664933A (en) * 1969-06-19 1972-05-23 Udylite Corp Process for acid copper plating of zinc
US3684666A (en) * 1970-03-19 1972-08-15 Pfizer & Co C Copper electroplating in a citric acid bath
BE791401A (en) * 1971-11-15 1973-05-14 Monsanto Co Compositions and Electrochemical Processes
US3770598A (en) 1972-01-21 1973-11-06 Oxy Metal Finishing Corp Electrodeposition of copper from acid baths
US4022679A (en) * 1973-05-10 1977-05-10 C. Conradty Coated titanium anode for amalgam heavy duty cells
US4000046A (en) * 1974-12-23 1976-12-28 P. R. Mallory & Co., Inc. Method of electroplating a conductive layer over an electrolytic capacitor
JPS5216433A (en) 1975-07-30 1977-02-07 Furukawa Electric Co Ltd Method of producing very thin copper foil
US4279948A (en) 1978-05-25 1981-07-21 Macdermid Incorporated Electroless copper deposition solution using a hypophosphite reducing agent
US4272335A (en) 1980-02-19 1981-06-09 Oxy Metal Industries Corporation Composition and method for electrodeposition of copper
US4384930A (en) * 1981-08-21 1983-05-24 Mcgean-Rohco, Inc. Electroplating baths, additives therefor and methods for the electrodeposition of metals
US4449885A (en) * 1982-05-24 1984-05-22 Varian Associates, Inc. Wafer transfer system
US4451197A (en) * 1982-07-26 1984-05-29 Advanced Semiconductor Materials Die Bonding, Inc. Object detection apparatus and method
US4673469A (en) * 1984-06-08 1987-06-16 Mcgean-Rohco, Inc. Method of plating plastics
US4624749A (en) 1985-09-03 1986-11-25 Harris Corporation Electrodeposition of submicrometer metallic interconnect for integrated circuits
FR2587915B1 (en) * 1985-09-27 1987-11-27 Omya Sa Device for the fluid contacting being in the form of different phases
US4959278A (en) * 1988-06-16 1990-09-25 Nippon Mining Co., Ltd. Tin whisker-free tin or tin alloy plated article and coating technique thereof
US5021129A (en) 1989-09-25 1991-06-04 International Business Machines Corporation Multilayer structures of different electroactive materials and methods of fabrication thereof
CA2035970C (en) * 1990-02-09 1999-06-01 Eiji Hirai Process for surface treating titanium-containing metallic material
JPH04120290A (en) * 1990-02-26 1992-04-21 Ishihara Chem Co Ltd Copper electroplating solution
JP2524436B2 (en) * 1990-09-18 1996-08-14 インターナショナル・ビジネス・マシーンズ・コーポレイション The surface treatment method
US5115430A (en) 1990-09-24 1992-05-19 At&T Bell Laboratories Fair access of multi-priority traffic to distributed-queue dual-bus networks
US5151168A (en) * 1990-09-24 1992-09-29 Micron Technology, Inc. Process for metallizing integrated circuits with electrolytically-deposited copper
JP2768390B2 (en) 1990-12-11 1998-06-25 インターナショナル・ビジネス・マシーンズ・コーポレイション How to condition the substrate for electroless metal deposition
JPH0544075A (en) * 1991-08-15 1993-02-23 Nippon Riironaale Kk Copper striking method substituted for electroless copper plating
US5209817A (en) * 1991-08-22 1993-05-11 International Business Machines Corporation Selective plating method for forming integral via and wiring layers
JP3057186B2 (en) 1991-11-22 2000-06-26 横河電機株式会社 Waveform analyzer
US5252196A (en) * 1991-12-05 1993-10-12 Shipley Company Inc. Copper electroplating solutions and processes
US5372848A (en) * 1992-12-24 1994-12-13 International Business Machines Corporation Process for creating organic polymeric substrate with copper
US5302278A (en) * 1993-02-19 1994-04-12 Learonal, Inc. Cyanide-free plating solutions for monovalent metals
JPH06349952A (en) * 1993-06-14 1994-12-22 Oki Electric Ind Co Ltd Wiring forming method
US5472502A (en) 1993-08-30 1995-12-05 Semiconductor Systems, Inc. Apparatus and method for spin coating wafers and the like
JPH07193214A (en) * 1993-12-27 1995-07-28 Mitsubishi Electric Corp Via-hole and its formation
US5472592A (en) * 1994-07-19 1995-12-05 American Plating Systems Electrolytic plating apparatus and method
US5512319A (en) * 1994-08-22 1996-04-30 Basf Corporation Polyurethane foam composite
US5625233A (en) * 1995-01-13 1997-04-29 Ibm Corporation Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide
US5549808A (en) * 1995-05-12 1996-08-27 International Business Machines Corporation Method for forming capped copper electrical interconnects
US5741435A (en) * 1995-08-08 1998-04-21 Nano Systems, Inc. Magnetic memory having shape anisotropic magnetic elements
GB2305188B (en) * 1995-09-16 1997-11-12 Sung Soo Moon Process for plating palladium or palladium alloy onto iron-nickel alloy substrate
US5620581A (en) * 1995-11-29 1997-04-15 Aiwa Research And Development, Inc. Apparatus for electroplating metal films including a cathode ring, insulator ring and thief ring
JPH09157846A (en) * 1995-12-01 1997-06-17 Teisan Kk Temperature controller
DE69608669D1 (en) 1995-12-19 2000-07-06 Fsi International Chaska Electroless muster of metal film with spray processor
US5891513A (en) 1996-01-16 1999-04-06 Cornell Research Foundation Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications
US5674787A (en) 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5824599A (en) 1996-01-16 1998-10-20 Cornell Research Foundation, Inc. Protected encapsulation of catalytic layer for electroless copper interconnect
US5683568A (en) * 1996-03-29 1997-11-04 University Of Tulsa Electroplating bath for nickel-iron alloys and method
US5576052A (en) 1996-04-22 1996-11-19 Motorola, Inc. Method of metallizing high aspect ratio apertures
US6051284A (en) * 1996-05-08 2000-04-18 Applied Materials, Inc. Chamber monitoring and adjustment by plasma RF metrology
US5695810A (en) 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US5913147A (en) 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
JP3054746B2 (en) 1997-02-03 2000-06-19 奥野製薬工業株式会社 Electroplating method to non-conductive material
DE19821781C2 (en) * 1997-05-15 2002-07-18 Toyoda Gosei Kk Coating method and coating apparatus for producing three-dimensional metal objects
US5969422A (en) 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US6565731B1 (en) * 1997-06-03 2003-05-20 Shipley Company, L.L.C. Electroplating process
US5972192A (en) 1997-07-23 1999-10-26 Advanced Micro Devices, Inc. Pulse electroplating copper or copper alloys
US6053687A (en) * 1997-09-05 2000-04-25 Applied Materials, Inc. Cost effective modular-linear wafer processing
US5897368A (en) 1997-11-10 1999-04-27 General Electric Company Method of fabricating metallized vias with steep walls
US5932077A (en) 1998-02-09 1999-08-03 Reynolds Tech Fabricators, Inc. Plating cell with horizontal product load mechanism
WO1999047731A1 (en) 1998-03-20 1999-09-23 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US6113771A (en) * 1998-04-21 2000-09-05 Applied Materials, Inc. Electro deposition chemistry
US6497801B1 (en) * 1998-07-10 2002-12-24 Semitool Inc Electroplating apparatus with segmented anode array
CN1244722C (en) 1998-07-10 2006-03-08 塞米用具公司 Apparatus for copper plating using electroless plating and electroplating
DE19840109A1 (en) * 1998-09-03 2000-03-09 Agfa Gevaert Ag Color photographic material, e.g. film or paper, contains anilino pyrazolone magenta coupler and alpha-benzoyl-alpha-tetrazolylthio-acetamide development inhibitor releasing coupler
US6319831B1 (en) 1999-03-18 2001-11-20 Taiwan Semiconductor Manufacturing Company Gap filling by two-step plating
US6277607B1 (en) * 1999-05-24 2001-08-21 Sanjay Tyagi High specificity primers, amplification methods and kits
US7090751B2 (en) * 2001-08-31 2006-08-15 Semitool, Inc. Apparatus and methods for electrochemical processing of microelectronic workpieces
WO2003060959A3 (en) * 2002-01-10 2004-03-25 Semitool Inc Method for applying metal features onto barrier layers using electrochemical deposition

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1526644A (en) * 1922-10-25 1925-02-17 Williams Brothers Mfg Company Process of electroplating and apparatus therefor
US2742412A (en) * 1952-07-05 1956-04-17 Metallic Industry Nv Electrolytic deposition of copper
US3309263A (en) * 1964-12-03 1967-03-14 Kimberly Clark Co Web pickup and transfer for a papermaking machine
US3495940A (en) * 1967-09-28 1970-02-17 Celanese Corp Production of high temperature resistant continuous filaments
US3716462A (en) * 1970-10-05 1973-02-13 D Jensen Copper plating on zinc and its alloys
US3930963A (en) * 1971-07-29 1976-01-06 Photocircuits Division Of Kollmorgen Corporation Method for the production of radiant energy imaged printed circuit boards
US3798003A (en) * 1972-02-14 1974-03-19 E Ensley Differential microcalorimeter
US3878066A (en) * 1972-09-06 1975-04-15 Manfred Dettke Bath for galvanic deposition of gold and gold alloys
US4082638A (en) * 1974-09-19 1978-04-04 Jumer John F Apparatus for incremental electro-processing of large areas
US4072557A (en) * 1974-12-23 1978-02-07 J. M. Voith Gmbh Method and apparatus for shrinking a travelling web of fibrous material
US4137867A (en) * 1977-09-12 1979-02-06 Seiichiro Aigo Apparatus for bump-plating semiconductor wafers
US4134802A (en) * 1977-10-03 1979-01-16 Oxy Metal Industries Corporation Electrolyte and method for electrodepositing bright metal deposits
US4246088A (en) * 1979-01-24 1981-01-20 Metal Box Limited Method and apparatus for electrolytic treatment of containers
US4576689A (en) * 1979-06-19 1986-03-18 Makkaev Almaxud M Process for electrochemical metallization of dielectrics
US4259166A (en) * 1980-03-31 1981-03-31 Rca Corporation Shield for plating substrate
US4437943A (en) * 1980-07-09 1984-03-20 Olin Corporation Method and apparatus for bonding metal wire to a base metal substrate
US4431361A (en) * 1980-09-02 1984-02-14 Heraeus Quarzschmelze Gmbh Methods of and apparatus for transferring articles between carrier members
US4323433A (en) * 1980-09-22 1982-04-06 The Boeing Company Anodizing process employing adjustable shield for suspended cathode
US4443117A (en) * 1980-09-26 1984-04-17 Terumo Corporation Measuring apparatus, method of manufacture thereof, and method of writing data into same
US4495153A (en) * 1981-06-12 1985-01-22 Nissan Motor Company, Limited Catalytic converter for treating engine exhaust gases
US4495453A (en) * 1981-06-26 1985-01-22 Fujitsu Fanuc Limited System for controlling an industrial robot
US4378283A (en) * 1981-07-30 1983-03-29 National Semiconductor Corporation Consumable-anode selective plating apparatus
US4566847A (en) * 1982-03-01 1986-01-28 Kabushiki Kaisha Daini Seikosha Industrial robot
US4440597A (en) * 1982-03-15 1984-04-03 The Procter & Gamble Company Wet-microcontracted paper and concomitant process
US4585539A (en) * 1982-08-17 1986-04-29 Technic, Inc. Electrolytic reactor
US4500394A (en) * 1984-05-16 1985-02-19 At&T Technologies, Inc. Contacting a surface for plating thereon
US4634503A (en) * 1984-06-27 1987-01-06 Daniel Nogavich Immersion electroplating system
US4639028A (en) * 1984-11-13 1987-01-27 Economic Development Corporation High temperature and acid resistant wafer pick up device
US4913085A (en) * 1985-01-01 1990-04-03 Esb Elektorstatische Spruh-Und Beschichtungsanlagen G.F. Vohringer Gmbh Coating booth for applying a coating powder to the surface of workpieces
US4576685A (en) * 1985-04-23 1986-03-18 Schering Ag Process and apparatus for plating onto articles
US4648944A (en) * 1985-07-18 1987-03-10 Martin Marietta Corporation Apparatus and method for controlling plating induced stress in electroforming and electroplating processes
US4800818A (en) * 1985-11-02 1989-01-31 Hitachi Kiden Kogyo Kabushiki Kaisha Linear motor-driven conveyor means
US4898647A (en) * 1985-12-24 1990-02-06 Gould, Inc. Process and apparatus for electroplating copper foil
US4906341A (en) * 1987-09-24 1990-03-06 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device and apparatus therefor
US5083364A (en) * 1987-10-20 1992-01-28 Convac Gmbh System for manufacturing semiconductor substrates
US4902398A (en) * 1988-04-27 1990-02-20 American Thim Film Laboratories, Inc. Computer program for vacuum coating systems
US4988533A (en) * 1988-05-27 1991-01-29 Texas Instruments Incorporated Method for deposition of silicon oxide on a wafer
US5183377A (en) * 1988-05-31 1993-02-02 Mannesmann Ag Guiding a robot in an array
US4990224A (en) * 1988-12-21 1991-02-05 International Business Machines Corporation Copper plating bath and process for difficult to plate metals
US5377708A (en) * 1989-03-27 1995-01-03 Semitool, Inc. Multi-station semiconductor processor with volatilization
US5180273A (en) * 1989-10-09 1993-01-19 Kabushiki Kaisha Toshiba Apparatus for transferring semiconductor wafers
US5000827A (en) * 1990-01-02 1991-03-19 Motorola, Inc. Method and apparatus for adjusting plating solution flow characteristics at substrate cathode periphery to minimize edge effect
US5186594A (en) * 1990-04-19 1993-02-16 Applied Materials, Inc. Dual cassette load lock
US5500081A (en) * 1990-05-15 1996-03-19 Bergman; Eric J. Dynamic semiconductor wafer processing using homogeneous chemical vapors
US5178639A (en) * 1990-06-28 1993-01-12 Tokyo Electron Sagami Limited Vertical heat-treating apparatus
US5723028A (en) * 1990-08-01 1998-03-03 Poris; Jaime Electrodeposition apparatus with virtual anode
US5078852A (en) * 1990-10-12 1992-01-07 Microelectronics And Computer Technology Corporation Plating rack
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US5302464A (en) * 1991-03-04 1994-04-12 Kanegafuchi Kagaku Kogyo Kabushiki Kaisha Method of plating a bonded magnet and a bonded magnet carrying a metal coating
US5306895A (en) * 1991-03-26 1994-04-26 Ngk Insulators, Ltd. Corrosion-resistant member for chemical apparatus using halogen series corrosive gas
US5178512A (en) * 1991-04-01 1993-01-12 Equipe Technologies Precision robot apparatus
US5597836A (en) * 1991-09-03 1997-01-28 Dowelanco N-(4-pyridyl) (substituted phenyl) acetamide pesticides
US5301700A (en) * 1992-03-05 1994-04-12 Tokyo Electron Limited Washing system
US5501768A (en) * 1992-04-17 1996-03-26 Kimberly-Clark Corporation Method of treating papermaking fibers for making tissue
US5388945A (en) * 1992-08-04 1995-02-14 International Business Machines Corporation Fully automated and computerized conveyor based manufacturing line architectures adapted to pressurized sealable transportable containers
US5284548A (en) * 1993-03-03 1994-02-08 Microelectronics And Computer Technology Corporation Process for producing electrical circuits with precision surface features
US5719447A (en) * 1993-06-03 1998-02-17 Intel Corporation Metal alloy interconnections for integrated circuits
US5489341A (en) * 1993-08-23 1996-02-06 Semitool, Inc. Semiconductor processing with non-jetting fluid stream discharge array
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5409587A (en) * 1993-09-16 1995-04-25 Micron Technology, Inc. Sputtering with collinator cleaning within the sputtering chamber
US5508095A (en) * 1993-11-16 1996-04-16 Scapa Group Plc Papermachine clothing
US5391285A (en) * 1994-02-25 1995-02-21 Motorola, Inc. Adjustable plating cell for uniform bump plating of semiconductor wafers
US5609239A (en) * 1994-03-21 1997-03-11 Thyssen Aufzuege Gmbh Locking system
US5600532A (en) * 1994-04-11 1997-02-04 Ngk Spark Plug Co., Ltd. Thin-film condenser
US5405518A (en) * 1994-04-26 1995-04-11 Industrial Technology Research Institute Workpiece holder apparatus
US6184068B1 (en) * 1994-06-02 2001-02-06 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor device
US5711646A (en) * 1994-10-07 1998-01-27 Tokyo Electron Limited Substrate transfer apparatus
US5593545A (en) * 1995-02-06 1997-01-14 Kimberly-Clark Corporation Method for making uncreped throughdried tissue products without an open draw
US5482891A (en) * 1995-03-17 1996-01-09 Motorola, Inc. VCSEL with an intergrated heat sink and method of making
US5871626A (en) * 1995-09-27 1999-02-16 Intel Corporation Flexible continuous cathode contact circuit for electrolytic plating of C4, TAB microbumps, and ultra large scale interconnects
US6028986A (en) * 1995-11-10 2000-02-22 Samsung Electronics Co., Ltd. Methods of designing and fabricating intergrated circuits which take into account capacitive loading by the intergrated circuit potting material
US5597460A (en) * 1995-11-13 1997-01-28 Reynolds Tech Fabricators, Inc. Plating cell having laminar flow sparger
US6709562B1 (en) * 1995-12-29 2004-03-23 International Business Machines Corporation Method of making electroplated interconnection structures on integrated circuit chips
US5871805A (en) * 1996-04-08 1999-02-16 Lemelson; Jerome Computer controlled vapor deposition processes
US5730854A (en) * 1996-05-30 1998-03-24 Enthone-Omi, Inc. Alkoxylated dimercaptans as copper additives and de-polarizing additives
US6672820B1 (en) * 1996-07-15 2004-01-06 Semitool, Inc. Semiconductor processing apparatus having linear conveyer system
US5731678A (en) * 1996-07-15 1998-03-24 Semitool, Inc. Processing head for semiconductor processing machines
US5723387A (en) * 1996-07-22 1998-03-03 Industrial Technology Research Institute Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates
US6036836A (en) * 1996-12-20 2000-03-14 Peeters; Joris Antonia Franciscus Process to create metallic stand-offs on an electronic circuit
US6199301B1 (en) * 1997-01-22 2001-03-13 Industrial Automation Services Pty. Ltd. Coating thickness control
US6174425B1 (en) * 1997-05-14 2001-01-16 Motorola, Inc. Process for depositing a layer of material over a substrate
US5882498A (en) * 1997-10-16 1999-03-16 Advanced Micro Devices, Inc. Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate
US6179983B1 (en) * 1997-11-13 2001-01-30 Novellus Systems, Inc. Method and apparatus for treating surface including virtual anode
US6027631A (en) * 1997-11-13 2000-02-22 Novellus Systems, Inc. Electroplating system with shields for varying thickness profile of deposited layer
US6193859B1 (en) * 1997-11-13 2001-02-27 Novellus Systems, Inc. Electric potential shaping apparatus for holding a semiconductor wafer during electroplating
US6174796B1 (en) * 1998-01-30 2001-01-16 Fujitsu Limited Semiconductor device manufacturing method
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
US20020008036A1 (en) * 1998-02-12 2002-01-24 Hui Wang Plating apparatus and method
US6197181B1 (en) * 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
US20040031693A1 (en) * 1998-03-20 2004-02-19 Chen Linlin Apparatus and method for electrochemically depositing metal on a semiconductor workpiece
US6699373B2 (en) * 1998-07-10 2004-03-02 Semitool, Inc. Apparatus for processing the surface of a microelectronic workpiece
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
US20020032499A1 (en) * 1999-04-13 2002-03-14 Wilson Gregory J. Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece
US20040055877A1 (en) * 1999-04-13 2004-03-25 Wilson Gregory J. Workpiece processor having processing chamber with improved processing fluid flow
US6168695B1 (en) * 1999-07-12 2001-01-02 Daniel J. Woodruff Lift and rotate assembly for use in a workpiece processing station and a method of attaching the same
US6342137B1 (en) * 1999-07-12 2002-01-29 Semitool, Inc. Lift and rotate assembly for use in a workpiece processing station and a method of attaching the same
US6531046B2 (en) * 1999-12-15 2003-03-11 Shipley Company, L.L.C. Seed layer repair method
US20030038035A1 (en) * 2001-05-30 2003-02-27 Wilson Gregory J. Methods and systems for controlling current in electrochemical processing of microelectronic workpieces
US6678055B2 (en) * 2001-11-26 2004-01-13 Tevet Process Control Technologies Ltd. Method and apparatus for measuring stress in semiconductor wafers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090087800A1 (en) * 2007-09-28 2009-04-02 Fujifilm Corporation Method and apparatus for producing conductive material
US8268400B2 (en) * 2007-09-28 2012-09-18 Fujifilm Corporation Method and apparatus for producing conductive material

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