US20040164304A1 - Insulated gate planar integrated power device with co-integrated schottky diode and process - Google Patents

Insulated gate planar integrated power device with co-integrated schottky diode and process Download PDF

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US20040164304A1
US20040164304A1 US10/713,778 US71377803A US2004164304A1 US 20040164304 A1 US20040164304 A1 US 20040164304A1 US 71377803 A US71377803 A US 71377803A US 2004164304 A1 US2004164304 A1 US 2004164304A1
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aperture
drain
layer
conductivity
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Angelo Magri
Ferruccio Frisina
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STMicroelectronics SRL
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Assigned to STMICROELECTRONICS S.R.L. reassignment STMICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FRISINA, FERRUCCIO, MAGRI, ANGELO
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Priority to US11/520,210 priority Critical patent/US7560368B2/en
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode

Definitions

  • the invention relates generally to insulated gate planar integrated power devices and in particular to devices to which are associated a power diode integrated on the same chip.
  • Insulated gate devices such as MOSFETs in particular, are used in many applications as synchronous rectifiers.
  • the insulated gate device operates as a diode: it is turned on when the equivalent diode must be in conduction and is turned off when the diode must stop conducting.
  • a known approach is that of using a Schottky diode of the same voltage and of appropriate area, in parallel to the internal PN junction diode of the integrated structure of the insulated gate device (for example a power MOS transistor or briefly PMOS).
  • the Schottky diode Because of the absence of minority carriers, the Schottky diode is characterized by a fast recovery and, because of the different barrier heights, it has lower conduction voltages. In fact, for voltages lower than 0.9V the Schottky diode conducts a larger current than a PN junction diode; for higher voltages, the characteristics become similar and the PN diode finally conducts a larger current, because of the modulation of its conductivity.
  • FIG. 1 illustrates the advantage of a combined diode MPS (Merged PN Schottky) in respect to a normal junction diode.
  • a more efficient solution depicted in FIG. 4, consists in “distributing” the Schottky diode uniformly over the whole active area of the PMOS by integrating it in the elementary cells of the MOS. It has been demonstrated that by using a uniform distribution of Schottky diodes, it is possible to improve the dynamic performances (trr and softness) while using a reduced total area dedicated to the diode.
  • a Schottky diode is realized in the elementary cell of the MOSFET by a dedicated step of photolithography for realizing a Schottky diode through a certain aperture produced through a first deposited polysilicon layer, that is in the area destined to the realization of the integrated structure of an elementary cell of the insulated gate power device and on which the relative source contact will be established.
  • Schottky diodes are realized by contacting with a metal layer the monocrystalline semiconducting substrate, the doping level of which determines the voltage class.
  • the technique of forming, around the Schottky contact region in the semiconductor, a more or less dense array of juxtaposed diffuse regions (tubs) of opposite type of conductivity to that of the substrate (Lateral Merged PiN Schottky). The distance of separation among adjacent tubs is chosen so that under conditions of inverse polarization, the electric field is partially shielded by the depleted zones that form around the tubs.
  • a further aspect of the present invention is that of limiting the number of photolithographic steps in the sequence of process steps of an insulated gate integrated power device with co-integrated Schottky diode in parallel thereto.
  • the photolithographic step for defining the Schottky contact area inside the aperture of a discrete or of an elementary cell of an integrated structure of the insulated gate power device is eliminated by carrying out:
  • an embodiment of the invention provides a method for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner without requiring a dedicated masking step. This overcomes the above indicated limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages that will be mentioned in the ensuing description.
  • An implanted and diffused source region is formed in the cell area within the body region.
  • a drain region of the semiconductor substrate is coupled to the invertible channel region and the current is eventually collected through a drain contact.
  • a trench is formed, in self-alignment to spacers formed on definition edge surfaces of the aperture, in the semiconductor crystal in a portion of the area of the aperture that includes a central “window” that is defined in a shade pattern by purposely implanting with different tilt and twist angles the body dopants, for a depth extending from the crystal surface through the source region and the body region that surrounds the central zone of said window not implanted with the body dopants, reaching down into the drain semiconductor under the source diffusion in correspondence of said window.
  • a deposited metal layer contacts on at least a portion of the side walls of the trench, the source, and the body region, constituting a source contact, and, on the bottom of the trench, the drain semiconductor substrate thus establishing a Schottky contact with the drain region, electrically in parallel to the insulated gate device.
  • said trench is formed in a central zone of the area of the cell aperture and of the diffused body region, for a depth sufficient to reach into the semiconductor beyond the bottom profile of the source diffusion, that is in a region electrically coinciding with the drain region and surrounded by the diffused body region.
  • the source contact metallization fills the trench establishing an electric contact with the source region and with the body region on at least a portion of the surface of the side walls of the trench and a Schottky contact on at least a portion of the bottom surface of the trench.
  • the structure further comprises a diffused deep body region, more heavily doped than the first diffused body region that is contained therein.
  • This second or deep body region besides containing the first body region, extends for a greater depth than the first body region surround a deeper zone under the Schottky contact established on the bottom of the trench.
  • the structure further comprises a buried region having the same type of conductivity of the first body region, geometrically located in the semiconductor crystal at a certain depth under the Schottky contact established on the bottom of the trench and surrounded by a deep body region and/or by the body region.
  • FIG. 1 shows the experimental trade-off curve between the voltage Vf and the inverse current peak of a switching MPS diode, with an irradiated PN junction diode in function of the area reserved to the Schottky diode;
  • FIG. 2 depicts a solution with discrete elements combined in a single package
  • FIG. 3 depicts a monolithic solution with distinct areas for the PMOS and the Schottky diode
  • FIG. 4 depicts an integrated solution of a Schottky diode in each elementary cell of the PMOS, according to the prior art
  • FIGS. from 5 to 14 illustrate the relevant steps of a process of fabrication of an insulated gate power device and characteristics of the structure that is realized, according to a first embodiment of this invention
  • FIGS. from 15 to 21 illustrate the relevant steps of a process of fabrication and characteristics of the structure that is realized, according to an alternative embodiment of this invention
  • FIG. 22 shows leakage characteristics under inverse polarization in function of the area of the Schottky contact in the embodiments of FIGS. 5 - 14 and 15 - 21 ;
  • FIGS. from 23 to 29 illustrate the relevant steps of a process of fabrication and characteristics of the structure that is realized, according to a third alternative embodiment of this invention.
  • FIG. 30 shows the inverse leakage and the direct voltage drop performances in function of the characteristics of a shielding buried region of the Schottky contact in the embodiment of FIGS. 23 - 29 .
  • the process of this invention differs from the known processes for the realization of a structure of an insulated gate device with Schottky diode integrated in the elementary cells that compose the device, because of the way in which the elementary cell structure is realized such to include a Schottky contact between the source metal layer and a region of semiconductor crystal of substrate electrically coinciding with the drain of the integrated power device.
  • the structure of this invention may also be that of a P-channel floating gate device, by simply inverting, in a dual mode, the type of conductivity of the semiconducting crystal substrate and of the dopants used for realizing the various diffused regions.
  • ion implantation first body implant
  • a P type dopant for example boron or indium with 30° tilt and 90° twist
  • the tilt angle must be chosen such to create a shade zone by the windows opened by the anisotropic (vertical) etching in the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the hard mask formed by the polysilicon the insulating layer and eventually also of the residual thickness of the photo resist mask, and from the width of the stripes or definition lines.
  • the twist angle must be such to make the impinging ion beam orthogonal to the long side of the stripe segments.
  • the implant dose and energy will be chosen such to obtain the desired concentration and channel length;
  • ion implantation (second body implantation) of the same P type dopant but with tilt and twist angles opposite to the ones of the preceding implantation step (for example boron or indium with ⁇ 30° tilt and 90° twist or 30° tilt and ⁇ 90° twist);
  • ion implantation of a N type dopant (for example 1015 ions/cm2 of arsenic with an implant energy of about 80 keV);
  • metallization of the front side of the wafer with a material capable of establishing a good electrical contact with said exposed surfaces of the body and source diffusions and a good barrier height of the Schottky contact that is established at the bottom of the trench with the silicon of substrate, that is with the drain of the integrated structure of the insulated gate power device (suitable materials may be for example titanium or a silicide thereof);
  • ion implantation first deep body implantation
  • a P type dopant for example boron or indium with 20° tilt and 90° twist
  • the tilt angle must be chosen such to create a shade zone in the windows opened by the anisotropic (vertical) etching through the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the mask formed by the polysilicon layer, the insulating layer and the residual thickness of the photo resist mask, and from the width of the stripes or definition lines.
  • the twist angle must be such that the ionic stream be orthogonal to the long side of the stripes.
  • the dose and the implant energy must be chosen such to obtain the desired concentration;
  • ion implantation (second deep body implant) of the same P type dopant but with tilt and twist angles opposite to those of the preceding implantation step (for example boron or indium with ⁇ 20° tilt and 90° twist or 20° tilt and ⁇ 90° twist);
  • ion implantation first body implant
  • a P type dopant for example boron or indium with 40° tilt and 90° twist.
  • the tilt angle must be chosen such to create a shade zone by the windows opened by the anisotropic (vertical) etching in the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the hard mask formed by the polysilicon the insulating layer and from the width of the stripes or definition lines.
  • the twist angle must be such to make the impinging ion beam orthogonal to the long side of the stripe segments.
  • the implant dose and energy will be chosen such to obtain the desired concentration and channel length;
  • ion implantation (second body implantation) of the same P type dopant but with tilt and twist angles opposite to those of the preceding implantation step (for example boron or indium with ⁇ 40° tilt and 90° twist or 40° tilt and ⁇ 90° twist);
  • ion implantation of a N type dopant (for example 1015 ions/cm2 of arsenic with an implant energy of 80 keV);
  • an implantation (which hereinafter will be referred to as “drain engineering” or D.E.) is included in the process sequence for increasing the resistivity of the semiconductor of substrate (drain) of the device under the Schottky contact region.
  • the semiconductor substrate or drain may be in practice an expitaxial layer grown on a semiconductor crystal that may have electrical characteristics different from those of the epitaxial layer grown thereon.
  • An implanted buried region of “drain engineering” will be electrically tied to the body or, where they exists, to the deep body diffusions, such to effectively shield the Schottky contact also in a vertical direction, with the result of decisively reducing the leakage current.
  • the realized integrated structure may be defined as “Lateral & Vertical Merged PiN Schottky (LVMPS)”.
  • ion implantation Drain Engineering implant
  • a P type dopant for example boron at 200-400 keV.
  • the dose to be implanted must be such to compensate slightly the epitaxial layer and it is thus a function of the voltage class of the power device being fabricated;
  • ion implantation first body implant
  • a P type dopant for example boron or indium with 30° tilt and 90° twist.
  • the tilt angle must be chosen such to create a shade zone by the windows opened by the anisotropic (vertical) etching in the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the hard mask formed by the polysilicon the insulating layer and eventually also of the residual thickness of the photo resist mask, and from the width of the stripes or definition lines.
  • the twist angle must be such to make the impinging ion beam orthogonal to the long side of the stripe segments.
  • the implant dose and energy will be chosen such to obtain the desired concentration and channel length;
  • ion implantation (second body implant) of the same P type dopant but with tilt and twist angles opposite to those of the preceding implantation (for example boron or indium with ⁇ 30° tilt and 90° twist or 30° tilt and ⁇ 90° twist);
  • ion implantation of a N type dopant (for example 1015 ions/cm2 of arsenic with an implant energy of about 80 keV);
  • the composite basic cell structure MOS+Schottky of this invention is realized without any additional dedicated masking step.
  • the width of the stripes is thus limited only by the resolution of the photoexposition equipment and by the ability to precisely implant the dopants (to this end it is convenient to use dopants with low diffusivity such as indium and arsenic);
  • stripe layout is not mandatory, other cellular layouts may be used, eventually performing several pairs of body implantations each with appropriate tilts and twist angles in order to realize the body diffusions in each channel zone while defining a Shottky contact window there between.
  • the graph of FIG. 30 shows the leakage current and the direct voltage drop obtained on test structures for different doses of drain engineering dopant. Near the dose of 2*1012 ions/cm2 there is enough room for reducing the leakage by an order of magnitude without burdening excessively the direct voltage drop. By doubling the dose, the drain engineering diffusion creates a junction that shields the Schottky contact but reduces the direct characteristic to become practically similar to that of a PN junction diode.
  • the insulated gate planar power devices avcording to the above embodiments may be used in a variety of different types of electronic systems, such as a DC-DC converter and other types of rectifying systems.

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US8736013B2 (en) 2012-04-19 2014-05-27 Fairchild Semiconductor Corporation Schottky diode with opposite-polarity schottky diode field guard ring
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CN103700587A (zh) * 2012-09-27 2014-04-02 意法半导体股份有限公司 用于制造诸如超势垒sbr整流器之类的半导体器件的方法
CN104718627A (zh) * 2012-10-19 2015-06-17 日产自动车株式会社 半导体装置及其制造方法
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US10347501B2 (en) 2015-05-01 2019-07-09 The Regents Of The University Of California Enhanced patterning of integrated circuit layer by tilted ion implantation
WO2016179025A1 (en) * 2015-05-01 2016-11-10 The Regents Of The University Of California Enhanced patterning of integrated circuit layer by tilted ion implantation
US10937870B2 (en) 2016-05-23 2021-03-02 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using body region extensions
US10600871B2 (en) 2016-05-23 2020-03-24 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using body region extensions
US10056457B2 (en) 2016-05-23 2018-08-21 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using channel region extensions
US10096681B2 (en) 2016-05-23 2018-10-09 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells
US10388737B2 (en) 2016-05-23 2019-08-20 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) devices having an optimization layer
US9954093B2 (en) * 2016-06-29 2018-04-24 Infineon Technologies Austria Ag Method of manufacturing a super junction semiconductor device and super junction semiconductor device
CN106098752A (zh) * 2016-07-25 2016-11-09 吉林华微电子股份有限公司 一种igbt器件及其制造方法
CN107634001A (zh) * 2016-11-18 2018-01-26 成都芯源系统有限公司 一种ldmos器件的制造方法
US20200027720A1 (en) * 2017-05-19 2020-01-23 Ordos Yuansheng Optoelectronics Co., Ltd. Method for doping layer, thin film transistor and method for fabricating the same
US10886144B2 (en) * 2017-05-19 2021-01-05 Ordos Yuansheng Optoelectronics Co., Ltd. Method for doping layer, thin film transistor and method for fabricating the same
CN110212026A (zh) * 2019-05-06 2019-09-06 上海功成半导体科技有限公司 超结mos器件结构及其制备方法
US11640908B2 (en) * 2019-05-20 2023-05-02 Infineon Technologies Ag Method of implanting an implant species into a substrate at different depths
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