US20040043515A1 - Universal semiconductor housing with precrosslinked plastic embedding compounds, and method of producing the semiconductor housing - Google Patents

Universal semiconductor housing with precrosslinked plastic embedding compounds, and method of producing the semiconductor housing Download PDF

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Publication number
US20040043515A1
US20040043515A1 US10/651,856 US65185603A US2004043515A1 US 20040043515 A1 US20040043515 A1 US 20040043515A1 US 65185603 A US65185603 A US 65185603A US 2004043515 A1 US2004043515 A1 US 2004043515A1
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Prior art keywords
plastic layer
plastic
semiconductor chip
blank
layer
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Abandoned
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US10/651,856
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English (en)
Inventor
Bernd Goller
Robert-Christian Hagen
Gerald Ofner
Christian Stuempfl
Stefan Wein
Holger Worner
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Individual
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Publication of US20040043515A1 publication Critical patent/US20040043515A1/en
Priority to US11/491,746 priority Critical patent/US7517722B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the invention lies in the semiconductor processing field and relates, more specifically, to a technology for the production of universal semiconductor housings by using precross-linked plastic embedding compounds.
  • the invention relates to a method of producing a blank having a plurality of component positions for electronic components which have such plastic embedding compounds, and also to electronic components having corresponding plastic embedding compounds.
  • U.S. Pat. No. 5,990,546 discloses an electronic component with a semiconductor chip in which the semiconductor chip is enclosed in a plastic embedding compound, and contact regions of the semiconductor chip are connected electrically via a separately provided wiring plate to external contacts of the electronic component.
  • Providing a separate, complexly constructed wiring plate for an assembly of an electronic component is costly.
  • the problem arises that connecting the contact regions of the semiconductor chips to corresponding contact connecting surfaces of the separately provided wiring plate is extremely difficult, and that high reject rates occur in such a method.
  • the reliability of such electronic components is limited.
  • the blank forms a self-supporting, dimensionally stable plastic plate made of plastic embedding materials.
  • a semiconductor chip is embedded in the plastic plate.
  • Wiring structures can then be directly applied layer by layer to this self-supporting, dimensionally stable plastic plate, so that with this method the production of a separate complex wiring plate is dispensed with and the problems of connecting contact surfaces of a wiring plate to the contact regions of a semiconductor chip are overcome, since, in the method according to the invention, no wiring plate has to be fitted with semiconductor chips.
  • the method of producing a blank of this type on which wiring layers for a plurality of electronic components can finally be deposited directly and simultaneously has substantially 4 method steps.
  • a carrier plate and/or a first plastic layer of a plastic embedding compound are provided, the first plastic layer being more highly crosslinked in a lower region than in an upper region.
  • the level of crosslinking in the lower region can be so high that the lower region already forms a self-supporting, dimensionally stable plastic layer, so that the lower region of the first plastic layer already replaces the carrier plate.
  • a semiconductor chip is then fitted in the respective component position, forming a bead of plastic embedding compound which surrounds the marginal sides of the semiconductor chip.
  • a second plastic layer is then applied, which completely embeds at least the marginal sides of the semiconductor chip.
  • a self-supporting, dimensionally stable plastic plate with embedded semiconductor chips is formed.
  • the curing of the plastic layers can be accelerated by means of thermal treatment and/or by means of irradiation with high-energy light beams, such as with ultraviolet light.
  • the plastic embedding compound of the self-supporting, dimensionally stable plastic plate can have further plastic layers in addition to the two plastic layers.
  • plastic layers for example, fiber-reinforced plastic layers or those filled with glass spheres can be provided, in order to implement a self-supporting, dimensionally stable plastic plate with embedded semiconductor chips.
  • This method has the advantage that an expanded wafer in the form of a blank is formed, on which, for a plurality of components, wiring structures comprising wiring layers with contact connecting surfaces, wiring lines and external contact surfaces can be applied simultaneously in a parallel method.
  • a wiring structure is applied to the self-supporting, dimensionally stable plastic plate and is connected electrically to the contact regions of the semiconductor chip.
  • contact regions of the semiconductor chip are understood to be the contact surfaces arranged directly on the semiconductor chip and, furthermore, also flip-chip contacts which are arranged on these contact surfaces.
  • the semiconductor chip can have solder balls, which represent solder spheres soldered to the contact surfaces of the semiconductor chip.
  • flip-chip contacts can be formed as solder bumps which are produced on the contact surfaces of a semiconductor chip by a printing technique with a subsequent sintering process.
  • the flip-chip contacts on a semiconductor chip can also be formed as surface contacts, the contact surfaces of the semiconductor chip being enlarged and thickened, for example by means of a solderable material.
  • flip-chip contacts are head contacts, which have a thermocompression head and are known as “stud bumps.” Furthermore, flip-chip contacts can be represented as elevated connecting surfaces by means of the electrochemical or chemical deposition of a metal on the contact surfaces as pillar contacts.
  • the contact regions of the semiconductor chip can nevertheless be connected reliably to wiring structures on account of the method according to the invention. If the contact regions of the semiconductor chip are covered, partly or completely, by a carrier plate or by one of the plastic layers, then the contact regions can be exposed by means of a photolithographic step before an application of wiring structures.
  • a base plate is heated up to temperatures between 120 and 350° C.
  • This heated base plate can be coated with a first plastic layer of a plastic embedding compound.
  • a level of crosslinking which decreases toward a upper boundary of the first plastic layer in a vertically staggered manner is formed.
  • a lower, hotter region of the first plastic layer, which makes direct contact with the heated base plate, will be more highly crosslinked as it cools than the region toward the upper side of the first plastic layer.
  • the heatable base plate can have a metal alloy.
  • a first plastic layer of an uncrosslinked plastic embedding compound can be subjected to a temperature gradient such that, in the region of the underside of the first plastic layer, a completely crosslinked, self-supporting, dimensionally stable lower region is formed, while a level of crosslinking which decreases with the height of the plastic layer occurs above this.
  • This variant of the carrier plate has the advantage that semiconductor chips can be pressed with their passive rear side into the upper, only precrosslinked region and can be fixed in this position, the penetration depth being predefined by the completely crosslinked region.
  • the active upper side of the semiconductor chip with the contact regions is not wetted by the plastic embedding material of the first plastic layer. Instead, part of the marginal side height of the semiconductor chip is wetted by the plastic embedding compound of the first plastic layer, forming a bead around the semiconductor chip.
  • an uncross-linked plastic embedding compound can be filled with spherical particles of uniform sphere diameter.
  • spherical particles of uniform sphere diameter Particularly suitable for this purpose are glass spheres, which can be produced with extremely small diameters of the order of magnitude of a few 100 nanometers by a spraying process.
  • This method variant has the advantage that a semiconductor chip can be pressed into the first plastic layer filled with spherical particles, the penetration depth being defined by the uniform sphere diameter.
  • the semiconductor chip While, in the exemplary embodiments of the method described hitherto, the semiconductor chip is introduced with its passive rear side into the upper, only precrosslinked region of the first plastic layer, the semiconductor chip can in each case be pressed with its active upper side and its contact regions into the first plastic layer in a component position of the blank, forming a bead which surrounds the marginal sides of the semiconductor chip.
  • the level of crosslinking of the lower region of the first plastic layer has not progressed to such an extent that a completely crosslinked lower region has been formed, but rather the level of precrosslinking is still such that the contact regions can touch a carrier plate or a carrier foil made of metal. Since the passive rear side of the semiconductor chips now projects out of the first plastic layer at the component positions of the blank, these rear sides can subsequently be covered and protected by the second plastic layer.
  • the semiconductor chip is in each case initially pressed with its passive rear side into the first plastic layer at the component positions of the blank, forming a bead of plastic embedding compound which surrounds the marginal sides of the semiconductor chip, then the active upper side of the semiconductor chip with the contact regions projects out of the first plastic layer.
  • the semiconductor chips can be arranged in this first plastic layer to form a new, expanded wafer.
  • the plastic embedding compound of the first plastic layer is also designated a “bi-stage” material, since the plastic embedding compound of the first plastic layer has at least two regions with a different level of crosslinking.
  • Plastic embedding compounds of this type are partly crosslinked thermosetting plastics whose crosslinking process is frozen or interrupted. When this stage is frozen, the materials are firm and dimensionally stable but, if heat is introduced by heating to temperatures between 90 and 120° C., become partly viscous again, so that semiconductor chips can be placed.
  • the curing mechanism is once more started, so that the material can then crosslink completely.
  • the use of material systems of this type for the first plastic layer consists in its being possible for the thermosetting plastic already to be applied to a carrier without being cured completely there. If this material is brought into contact with other not yet crosslinked thermosetting plastics, then chemical-physical crosslinking over the interface between the first and second plastic layers is also possible. Thus, excellent adhesion between the two materials of the first and second plastic layer can be achieved.
  • the second plastic layer can be applied to the first plastic layer in such a way that either the entire active upper side of a semiconductor chip is kept free of the second plastic layer or that at least the contact regions of the semiconductor chip remain free of the second plastic layer.
  • the advantage Associated with the second plastic layer is the advantage that the upper side of the blank is leveled, so that a level surface is available for deposition of wiring structures on the blank.
  • the complete curing of the plastic layers can be carried out either simultaneously for a plurality of plastic layers or successively. If curing is carried out successively, then, following the fitting of the semiconductor chips into the first plastic layer, a self-supporting, dimensionally stable body already results, and can be handled simply and reliably. It can even be stored temporarily until the application of the second plastic layer.
  • the second plastic layer can then be applied by means of a transfer molding process or by means of a spin-casting process. While, for the transfer molding process, a filled epoxy resin is applied to the first plastic layer as the second plastic layer for leveling the surface of the blank, plastics based on polyimides are particularly suitable for the spin-casting process.
  • the blank In order to cure the second plastic layer, the blank can be heated to 120 to 350° C. for 2 to 30 minutes. Even if a plurality of plastic layers are subjected to common curing, it is possible to operate with this temperature and time interval. Curing can be shortened substantially if the plastic layers of the blank are irradiated with UV light for a duration of a few seconds to a few minutes.
  • the term “few” is used, in this context, in accordance with its common dictionary meaning.
  • wiring structure on the blanks can be applied to the cured, self-supporting and dimensionally stable plastic plate, which now constitutes the blank.
  • the wiring structure has contact connecting surfaces which are deposited on the contact regions of the semiconductor chips. Furthermore, the wiring structure has wiring lines which lead to positions of external contacts. The formation of such a wiring structure can be carried out by means of chemical or electrochemical deposition of a metal.
  • Electrochemical deposition of the wiring structure on the upper side of the blank with exposed contact regions can advantageously be carried out in three stages. Firstly, a closed metal layer is applied by means of sputtering or an atomization technique. This metal layer, a few nanometers thick, is used to provide a large-area electrical contact for the electrochemical deposition on the self-supporting plastic plate of the blank. A photoresist mask is then applied in a pattern of the wiring structure, leaving the sputtered layer free, in such a way that regions which are not intended to have a wiring structure are covered by photoresist. A metal alloy is then deposited electrochemically in an electrolyte bath, forming the wiring structure.
  • the photoresist coating is removed.
  • the sputtered layer is finally removed by etching the entire surface of the blank. During this etching operation, the thickness of the wiring structure is reduced only slightly.
  • An alternative method of applying the wiring structure is either to print the wiring structure on the blank by means of jet printing or to apply a wiring structure to the blank by means of a mask, as in the stencil printing process or screen printing process.
  • Further wiring layers can be applied to the plastic plate, by insulating layers with through-contacts and insulating layers with wiring lines being arranged alternately on the first wiring structure.
  • the method according to the invention thus has the advantage that joining contact surfaces of a separate wiring plate to the contact regions of the semiconductor chip in every component position is dispensed with. It is neither necessary for a wiring plate to be provided, nor is it necessary to fit such a wiring plate with electronic components. Finally, pressing the plastic embedding compound in between wiring plate and semiconductor chip, endangering the electrical connections between the contact regions of the semiconductor chip and a wiring plate, is also dispensed with.
  • the housing technology according to the invention does not achieve the necessary wiring from the contact regions of a semiconductor chip to the external contacts of an electronic component by means of a prefabricated intermediate carrier but, instead, wiring layers are applied layer by layer to a blank in a parallel process.
  • sawn semiconductor chips are pressed into a plastic embedding compound which has at least two different levels of crosslinking, the level of crosslinking in the region of the underside of the first plastic layer being higher than in the region of the first plastic layer located above.
  • the method according to the invention thus provides a reliable connection between contact connecting surfaces of a wiring structure and contact regions of a semiconductor chip for electronic components.
  • external contacts can be applied to an external wiring layer of the blank in all component positions. With this step, it is ensured that the components of the blank can already pass through a functional test via the external contacts, so that defective components already on the blank can be marked.
  • An electronic component separated out from a blank of this type has the following features.
  • the semiconductor chip is embedded in a multilayer plastic compound.
  • the semiconductor chip is surrounded on its marginal sides by a first plastic layer, up to part of its marginal side height.
  • This first plastic layer has a upper boundary to a second plastic layer located above.
  • This second plastic layer rests on regions of the marginal sides of the semiconductor chip which are not already covered by the first plastic layer.
  • the second plastic layer has an upper side which is now level and which forms an interface to at least one further component plane.
  • Provided above the second plastic layer is at least one wiring structure with through-contacts between contact regions of the semiconductor chip and external contacts of the electronic component.
  • An electronic component of this type has the advantage that the wiring structure with the through-contacts to the contact regions of the semiconductor chip rests directly on the leveled surface of the second plastic layer. As a result, the contact between wiring structure and contact regions of the semiconductor chip can be made reliably, particularly since the contact regions of the semiconductor chips of the blank are completely exposed and accessible.
  • the electronic component has the advantage that further wiring layers with interposed insulating layers can be applied to a wiring structure reliably connected in this way to the contact regions of the semiconductor chip, and thus complex wiring structures, which can have intersections and bridges, can be implemented in an extremely simple manner with an electronic component of this type.
  • a blank having a plurality of component positions for electronic components each having a semiconductor chip is provided, the blank having the following features.
  • the semiconductor chips embedded in the blank are surrounded on their marginal sides by a first plastic layer, in each case up to part of their marginal side height.
  • This first plastic layer has a upper boundary to at least a second plastic layer located above.
  • the second plastic layer rests on regions of the marginal sides of the semiconductor chips which are not already covered by the first plastic layer.
  • the second plastic layer has a level upper side, which forms an interface to at least one wiring structure.
  • external contacts of electronic components are provided, which are connected via the wiring structure to the contact regions of the semiconductor chips.
  • the first plastic layer and/or the second plastic layer are at least partly cured to form a self-supporting, substantially dimensionally stable, multilayer plastic plate.
  • a blank of this type has the advantage that the semiconductor chips are fixed in the component positions by the first plastic layer, and the second plastic layer forms a compensating layer for leveling the blank. Still further plastic layers can be arranged between the first and the second plastic layer. Furthermore, a blank of this type has the advantage that a plurality of electronic components is produced simultaneously with the blank.
  • both the electronic component and the blank have a first plastic layer which is based on a plastic embedding compound which has vertically staggered different levels of crosslinking.
  • the highest level of crosslinking is arranged in the region of a base surface of the first plastic layer. This staggering of the level of crosslinking ensures defined positioning and fixing of the semiconductor chips in the first plastic layer and/or in the blank on each component position.
  • the first plastic layer can be based on a plastic embedding compound which has a completely crosslinked region in the region of a base plate and, above this, a precrosslinked region.
  • the completely crosslinked region forms a mounting plate for the blank, on which the semiconductor chips are arranged at a defined height in the first plastic layer.
  • the first plastic layer can be filled with spherical particles, in particular of glass. These spherical particles form spacers for the semiconductor chips on account of their uniform, predefined diameter, and fix the semiconductor chips at a predefined height in the first plastic layer.
  • the second plastic layer can have a polyimide resin, which has the advantage that it can be structured by means of photolithography.
  • the component or the blank can be covered uniformly and completely by the second plastic layer of polyimide resin.
  • the contact regions of the semiconductor chip in the blank, if they are covered by the second plastic layer, can be exposed by a photolithographic step in the polyimide resin.
  • the plastic plate can be provided with an adhesive layer, on which a wiring structure is anchored securely. An adhesive layer of this type can be applied over a large area, provided that the adhesive layer is composed of insulating oxides.
  • either the active upper side of the semiconductor chip with its contact regions or the passive rear side of the semiconductor chip can be arranged in the first plastic layer.
  • the contact regions either projecting out of the upper side of the first plastic layer or, with their contact regions, penetrating the first plastic layer and being accessible from the underside of the first plastic layer.
  • the step of exposing the contact regions of the semiconductor chips can be carried out reliably and simply.
  • the result for the construction of a “wafer-level-package” or of a blank results in three possible variants for “fan-out” wiring, in which external contacts are not only arranged above the region of the semiconductor chip on the blank but are also present outside this region above the plastic plate of the blank, in the region of the plastic embedding compound.
  • the three variants for “fan-out” wiring are explained in more detail in the appended figures.
  • the semiconductor chip is embedded with its passive rear side in a two-stage or “bi-stage” material.
  • This variant has the following advantages:
  • the active upper side of the semiconductor chip does not have to be sealed off during the embedding process, and the contact regions of the semiconductor chip are kept reliably open.
  • the semiconductor chips fixed in a two-stage or “bi-stage” material of a first plastic layer are introduced into a subsequent transfer molding process in such a way that their passive rear side is embedded in the first plastic layer, and the rest of the marginal edges of the semiconductor chips are covered by plastic potting compound.
  • the first plastic layer serves merely to fix the semiconductor chips, in order that the semiconductor chips can no longer be displaced during the transfer molding process.
  • a potted carrier without additional supporting material such as a foil or a fixed carrier, can be used.
  • the carrier can be heated and cooled deliberately in the lower regions, in order to achieve a high level of crosslinking.
  • the upper region of the first plastic layer, in which the semiconductor chips are fixed, is then merely precrosslinked.
  • the carrier can be produced cost-effectively in a molding process.
  • a third variant places the semiconductor chips with their active upper sides in the two-stage or “bi-stage” material of the first plastic layer and, by using a transfer molding process, can leave the passive rear sides of the semiconductor chips free or protect them with a plastic potting compound.
  • the third variant has the following advantages:
  • the active side of the semiconductor chip does not have to be sealed off in a complicated manner during embedding in the first plastic layer.
  • the elevated contacts do not have to constitute any solderable connections, since the semiconductor chips are not fixed by the contacts but by the plastic embedding compound of the first plastic layer.
  • FIG. 1 is a schematic cross-section through a blank in the region of a component position
  • FIGS. 2 to 4 are schematic cross sections of intermediate products during the production of a blank according to a first exemplary method according to the invention, wherein:
  • FIG. 2 is a schematic cross section through a first plastic layer, which is arranged on a base plate;
  • FIG. 3 is a schematic cross section of a component position following the embedding of a semiconductor chip in the first plastic layer
  • FIG. 4 is a schematic cross section through a blank following the application of a second plastic layer to the blank
  • FIG. 5 is a schematic cross section of an electronic component of a first embodiment of the invention.
  • FIG. 6 is a schematic cross section of an electronic component of a second embodiment of the invention.
  • FIG. 7 is a schematic cross section of an electronic component of a third embodiment of the invention.
  • FIGS. 8 to 11 are schematic cross sections of intermediate products during the production of a blank according to a second exemplary method of the invention, wherein:
  • FIG. 8 is a schematic cross section through a first plastic layer on a base plate
  • FIG. 9 is a schematic cross section through the first plastic layer following the embedding of semiconductor chips in the first plastic layer at component positions of the blank;
  • FIG. 10 shows a schematic cross section through a blank following the application of a second plastic layer
  • FIG. 11 shows a schematic cross section through a blank following the application of a plurality of wiring layers on the component positions of the blank.
  • FIG. 1 there is shown a schematic cross section through a blank 1 in the region of a component position 4 .
  • the blank 1 has a self-supporting, dimensionally stable plastic plate 3 , in which a semiconductor chip 5 is embedded at the component position 4 .
  • the semiconductor chip 5 has an active upper side 15 with contact regions 16 , and a passive rear side 17 and marginal sides 18 .
  • the semiconductor chip 5 is embedded with its passive rear side 17 in a first plastic layer 7 which, before the blank 1 is cured, has regions with a different level of crosslinking in a vertically staggered manner.
  • the plastic material used for the first plastic layer 7 is a so-called “bi-stage” material or two-stage material made of a thermosetting plastic.
  • An upper region 9 of the first plastic layer 7 is crosslinked to a lesser degree before being cured than a lower region 8 .
  • the level of crosslinking, or degree of crosslinking, of the lower region 8 in this first embodiment is so high that there is already complete crosslinking before the plastic layers are cured.
  • This highly crosslinked lower region 8 forms a stable base surface 26 which, at the same time, forms the base surface for the entire plastic plate 3 of the blank 1 .
  • a bead 10 of plastic embedding compound of the first plastic layer 7 surrounds the semiconductor chip 5 in its marginal region at the sides 18 .
  • This bead 10 is formed as the semiconductor chip 5 is introduced with its passive rear side 17 into the upper region 9 of the first plastic layer 7 .
  • the bead 10 wets the marginal sides 18 in their lower regions and ensures that the semiconductor chip 5 is fixed in the first plastic layer 7 at one of the component positions 4 of the blank 1 .
  • the semiconductor chip 5 On account of the increasing degree of crosslinking of the first plastic layer 7 in the direction of the base surface 26 , the semiconductor chip 5 is not forced with its passive rear side 17 to an arbitrary depth into the first plastic layer 7 .
  • the penetration depth of the semiconductor chip 5 in the first plastic layer 7 is defined by the level of crosslinking of the lower region 8 before being cured.
  • the contact regions 16 on the active upper side 15 of the semiconductor chip 5 remain completely free of the plastic embedding compound of the first plastic layer 7 , since the semiconductor chip 5 projects with its active upper side 15 out of the first plastic layer 7 .
  • the regions of the marginal sides 18 of the semiconductor chip 5 which are not wetted by the first plastic layer 7 are covered by a second plastic layer 11 , which forms a level upper boundary 25 without wetting the active upper side 15 of the semiconductor chip 5 .
  • This second plastic layer 11 forms a leveling compensating compound and adjoins an upper boundary 13 of the first plastic layer 7 .
  • This second plastic layer 11 in this embodiment of the invention, has a thermosetting plastic which is filled with insulating particles and which is applied by a transfer molding process.
  • the active upper side 15 of the semiconductor chip 5 was pressed onto a sealing film in an injection mold, so that the entire active upper side 15 of the semiconductor chip 5 is kept free of the material of the second plastic layer 11 .
  • a wiring structure is applied reliably to the blank 1 , particularly since the contact regions 16 of the active upper side 15 of the semiconductor chip 5 are accessible for a wiring structure.
  • a wiring structure of this type is applied layer by layer to the blank 1 .
  • FIGS. 2 to 4 show schematic cross sections of intermediate products during the production of a blank according to a first exemplary embodiment of the novel method. Components with the same functions as in FIG. 1 are identified by the same designations in FIGS. 2 to 4 and not specifically explained.
  • FIG. 2 shows a schematic cross section through a first plastic layer 7 on a base plate 12 .
  • This first plastic layer 7 is carried by a base plate 12 made of a metal alloy and, in its lower region 8 , has a level of precrosslinking which is higher than in its upper region 9 .
  • the first plastic layer 7 has a filling of glass spheres which have a uniform diameter. This diameter of the glass spheres is around a few hundred nanometers, the glass spheres being produced by means of a spraying process.
  • the filling level of this first plastic layer with spherical particles is between 5 and 50% by weight.
  • This low filling level means that, when the semiconductor chip 5 , which is aligned above the first plastic layer 7 at the component position 4 , penetrates in the direction of arrow A, a defined penetration depth for the semiconductor chip 5 is ensured.
  • the spherical particles with uniform diameter in this case form spacers from the base plate 12 shown in FIG. 2. This ensures a spacing of only a few hundred nanometers between the underside 14 of the first plastic layer 7 and the passive rear side 17 of the semiconductor chip 5 as the semiconductor chip 5 penetrates in the direction of arrow A.
  • FIG. 3 shows a schematic cross section of a component position 4 after a semiconductor chip 5 has been embedded in the first plastic layer 7 .
  • the semiconductor chip 5 is introduced into the first plastic layer 7 until it is at a defined spacing from the base plate 12 , a bead 10 of slightly crosslinked material of the upper region 9 of the first plastic layer 7 being formed.
  • the upper boundary 13 of the first plastic layer 7 produced in the process is uneven and not suitable for the fitting of wiring structures.
  • the passive rear side 17 of the semiconductor chip 5 penetrates into the first plastic layer 7 , the marginal sides 18 of the semiconductor chip 5 are wetted in a lower region, so that the semiconductor chip 5 remains fixed in these component positions 4 . Displacement of the semiconductor chip 5 from the component positions 4 during subsequent method steps is prevented as a result.
  • FIG. 4 shows a schematic cross section through a blank 1 following the application of a second plastic layer 11 to the upper boundary 13 of the first plastic layer 7 .
  • the second plastic layer 11 has a polyimide resin which completely covers the active upper side 15 of the semiconductor chip 5 .
  • the polyimide resin is used simultaneously as a photoresist layer. With the aid of a photolithographic step, because of the photosensitive properties of the polyimide resin, contact regions 16 of the semiconductor chip 5 are exposed.
  • the polyimide resin forms a completely leveled upper boundary 25 .
  • a spinning process is used for the second plastic layer 11 . Further method steps for a plurality of electronic components are then carried out simultaneously on the leveled interface 25 .
  • FIG. 5 shows a schematic cross section of an electronic component 2 of a first embodiment of the invention.
  • Components with the same functions as in preceding figures are identified with the same designations and not explained specifically.
  • the blank from which this electronic component 2 of FIG. 5 has been separated is produced by a method which was explained above with reference to FIGS. 2 to 4 .
  • the metallic base plate 12 shown in FIG. 4 has been removed from the plastic plate of the blank before the blank is divided up into individual electronic components 2 .
  • windows in which the contact regions 16 of the semiconductor chip 5 are freed of the second plastic layer 11 have been opened by a photolithographic step.
  • a wiring structure 19 Arranged on the second plastic layer 11 is a wiring structure 19 which has through-contacts 22 to the contact regions 16 of the active upper side 15 of the semiconductor chip 5 .
  • the contact regions 16 are formed as surface contacts.
  • the wiring structure 19 which has been applied to the plastic layer 11 in a chemical process, has wiring lines 23 which lead from the through-contacts 22 to external contact surfaces 29 .
  • These external contact surfaces 29 are arranged outside the region of the semiconductor chip 5 on the plastic plate 3 and bear external contacts 24 in the form of solder balls.
  • Such an arrangement of the external contacts 24 is also designated a “fan-out”.
  • a solder stop resist layer 30 which surrounds the external contacts 25 , protects the wiring lines 23 of the wiring structure 19 against wetting with joining material when the external contacts 24 are joined to the external contact surfaces 29 .
  • multilayer wiring structures are provided in an example of an electronic component 2 not shown here.
  • wiring layers are applied successively, layer by layer, to the leveled second plastic layer 11 .
  • FIG. 6 shows a schematic cross section of an electronic component 2 of a second embodiment of the invention.
  • Components with the same functions as in the preceding figures are identified with the same designations and not explained specifically.
  • the second embodiment of the invention differs from the first embodiment of the invention, shown in FIG. 5, in the fact that the lower region 8 of the first plastic layer 7 is completely crosslinked, so that a carrier plate of plastic is formed.
  • a metallic base plate is not required to produce an electronic component 2 of this type, as opposed to the electronic component 2 of the first embodiment.
  • the completely crosslinked lower region 8 forms a self-supporting, dimensionally stable base layer, on which the semiconductor chip 5 is aligned and arranged.
  • the upper region 9 of the first plastic layer 7 is firstly only precrosslinked before the curing of the plastic layers 7 and 11 , so that, as the semiconductor chip 5 penetrates into the first plastic layer 7 , a bead 10 is formed around the marginal sides 18 of the semiconductor chip 5 .
  • the second plastic layer 11 is arranged as a compensating compound on the upper boundary 13 of the first plastic layer 7 .
  • This second plastic layer 11 forms a level upper boundary 25 , on which a solder stop resist layer 30 is arranged.
  • the arrangement and structure of the external contact surfaces and of the external contacts correspond to the first embodiment shown in FIG. 5.
  • FIG. 7 shows a schematic cross section of an electronic component 2 of a third embodiment of the invention.
  • Components with the same functions as in the preceding figures are identified by the same designations and not explained specifically.
  • the semiconductor chip 5 of the electronic component 2 of the third embodiment of the invention is also fixed with its passive rear side 17 in the first plastic layer 7 .
  • the third embodiment of the electronic component 2 differs from the first two embodiments, which are shown in FIGS. 5 and 6, in the fact that the contact regions 16 of the semiconductor chip 5 do not have any surface contacts. Instead, the wiring structure 19 is connected electrically to contact regions 16 of the semiconductor chip 5 , which have elevated flip-chip contacts in the form of contact balls, contact bumps, contact pillars or contact heads. In order to compensate for the height of these flip-chip contacts, an insulating layer 39 is applied to the upper boundary 25 of the second plastic layer 11 . A further insulating layer 32 with through-contacts 22 is arranged on the insulating layer 31 . Arranged on this further insulating layer 32 is a wiring structure 19 , which is connected electrically to the through-contacts 22 . The arrangement and structure of the external contact surfaces 29 and of the external contacts 24 correspond to the embodiment shown in FIGS. 5 and 6.
  • FIGS. 8 to 11 will be used to explain a second implementation example of the method, in which semiconductor chips 5 are embedded with their active upper sides 15 in the first plastic layer.
  • FIGS. 8 to 11 show schematic cross sections of intermediate products during the production of a blank 1 according to a second method example of the invention. Components with the same functions as in the preceding figures are identified with the same designations in FIGS. 8 to 11 and not explained specifically.
  • the significant aspect which distinguishes the second implementation example of the method, shown by FIGS. 8 to 11 , from the first implementation example, shown by FIGS. 2 to 4 , consists in the fact that, in the second implementation example, the semiconductor chips 5 are introduced into the first plastic layer 7 of a two-stage material at the component positions 4 with their active upper sides 15 in this material.
  • FIG. 8 shows a schematic cross section through a first plastic layer 7 on a base plate 12 .
  • the first plastic layer 7 has a lower region 8 which is more highly crosslinked than an upper region 9 .
  • the dashed line 33 identifies the transition from the more highly crosslinked lower region 8 to the less highly crosslinked upper region 9 .
  • FIG. 8 identifies the boundary between two component positions 4 , over which in each case a semiconductor chip 5 is aligned in such a way that it can be introduced with its active upper side 15 and the contact regions 16 into the first plastic layer 7 in the direction of arrow A.
  • the plastic layer 7 is solid at room temperature and reaches a partly viscous state in the more highly cross-linked lower region 8 and a state of lower viscosity in the upper region 9 when the first plastic layer 7 is heated to temperatures between 90 and 120° C. Following the heating of the first plastic layer 7 to such a temperature, the semiconductor chips 5 are introduced with their active upper sides 15 into the first plastic layer 7 in the direction of arrow A.
  • FIG. 9 shows a schematic cross section through the first plastic layer 7 after the semiconductor chips 5 have been embedded in the first plastic layer 7 at the component positions 4 of the blank.
  • a bead 10 forms in the upper region 9 of the first plastic layer 7 , surrounds each semiconductor chip 5 in its marginal regions 18 and thus fixes the semiconductor chip 5 in the component positions 4 of the blank.
  • the contact regions 16 of the semiconductor chips 5 touch the base plate 12 .
  • the first plastic layer 7 is crosslinked completely and forms a upper boundary 13 .
  • FIG. 10 shows a cross section through a blank 1 following the application of a second plastic layer 11 .
  • the second plastic layer 11 does not cover the active upper sides 15 of the semiconductor chips 5 but the passive rear sides 17 of the semiconductor chips 5 .
  • the passive rear sides 17 are therefore protected against mechanical damage.
  • the second plastic layer 11 is applied while leaving the passive rear sides 17 of the semiconductor chips 5 free.
  • the passive rear sides 17 of the semiconductor chips 5 there is the possibility of fitting heat sinks directly to the passive rear sides 17 of the semiconductor chips 5 , in order to dissipate heat losses during operation following the completion of the electronic components.
  • FIG. 11 shows a schematic cross section through a blank 1 following the application of a plurality of wiring layers 20 , 21 and 35 to the blank 1 in the component positions 4 .
  • the metallic base plate 12 shown in FIG. 10 is removed from the blank 1 . This removal of the metallic base plate is carried out by means of an etching technique. Given appropriate surface preparation of the base plate, the latter is also pulled off the plastic plate 3 of the blank 1 , exposing the contact regions 16 of the semiconductor chips 5 .
  • the surface of the base plate 12 shown in FIG. 10 has a thin coating of a few 100 nanometers, for example of polytetrafluoroethylene.
  • FIG. 11 shows, with the method according to the invention, complex wiring structures comprising a plurality of wiring layers 20 , 21 and 35 can be implemented simultaneously on the plastic plate 3 of the blank 1 for a plurality of electronic components.
  • external contacts not shown here are applied to the external wiring layer 35 .
  • the blank 1 is then divided along the dash-dotted line 34 into individual electronic components.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
US10/651,856 2002-08-29 2003-08-29 Universal semiconductor housing with precrosslinked plastic embedding compounds, and method of producing the semiconductor housing Abandoned US20040043515A1 (en)

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US20060000916A1 (en) * 2004-07-02 2006-01-05 Amstutz Aaron K System and method for encapsulation and protection of components
WO2006014196A1 (fr) * 2004-07-02 2006-02-09 Caterpillar Inc. Système et procédé d’encapsulation et protection de composants
US7210635B2 (en) 2004-07-02 2007-05-01 Caterpillar Inc System and method for encapsulation and protection of components
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US20110204513A1 (en) * 2010-02-25 2011-08-25 Thorsten Meyer Device Including an Encapsulated Semiconductor Chip and Manufacturing Method Thereof
US8421226B2 (en) 2010-02-25 2013-04-16 Infineon Technologies Ag Device including an encapsulated semiconductor chip and manufacturing method thereof
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US10943842B2 (en) 2017-08-31 2021-03-09 Micron Technology, Inc. Semiconductor device with a protection mechanism and associated systems, devices, and methods
US11756844B2 (en) 2017-08-31 2023-09-12 Micron Technology, Inc. Semiconductor device with a protection mechanism and associated systems, devices, and methods
US10615150B2 (en) * 2018-01-24 2020-04-07 Micron Technology, Inc. Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
US10741528B2 (en) 2018-01-24 2020-08-11 Micron Technology, Inc. Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods
US11114415B2 (en) 2018-01-24 2021-09-07 Micron Technology, Inc. Semiconductor device with a layered protection mechanism and associated systems, devices, and methods

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US7517722B2 (en) 2009-04-14
US20060258046A1 (en) 2006-11-16
EP1398828A2 (fr) 2004-03-17
EP1398828A3 (fr) 2010-03-03

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