US20030119305A1 - Mask layer and dual damascene interconnect structure in a semiconductor device - Google Patents

Mask layer and dual damascene interconnect structure in a semiconductor device Download PDF

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Publication number
US20030119305A1
US20030119305A1 US10/026,257 US2625701A US2003119305A1 US 20030119305 A1 US20030119305 A1 US 20030119305A1 US 2625701 A US2625701 A US 2625701A US 2003119305 A1 US2003119305 A1 US 2003119305A1
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United States
Prior art keywords
layer
mask
trench
forming
mask film
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Abandoned
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US10/026,257
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English (en)
Inventor
Robert Huang
Scott Jessen
Subramanian Karthikeyan
Joshua Li
Isaiah Oladeji
Kurt Steiner
Joseph Taylor
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Agere Systems LLC
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Agere Systems LLC
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Priority to US10/026,257 priority Critical patent/US20030119305A1/en
Assigned to AGERE SYSTEMS, INC. reassignment AGERE SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, ROBERT YS, JESSEN, SCOTT, KARTHIKEYAN, SUBRAMANIAN, OLADEJI, ISAIAH O., STEINER, KURT G., TAYLOR, JOSEPH A.
Priority to GB0226986A priority patent/GB2390741B/en
Priority to TW091133996A priority patent/TWI254375B/zh
Priority to JP2002337918A priority patent/JP4486303B2/ja
Priority to KR1020020081701A priority patent/KR20030053055A/ko
Publication of US20030119305A1 publication Critical patent/US20030119305A1/en
Priority to US10/721,126 priority patent/US7067419B2/en
Priority to JP2009161396A priority patent/JP2009224816A/ja
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

Definitions

  • the present invention relates generally to the fabrication of interconnect structures on a semiconductor device. More specifically, this invention pertains a dual damascene process used in the fabrication of interconnect structures and to interconnect structures incorporating low-k dielectric materials.
  • FIGS. 1 through 4 Several different dual damascene processes may be utilized in the fabrication of interconnect structures.
  • One such process is the full via-first (“FVF”), which is illustrated in FIGS. 1 through 4.
  • FVF full via-first
  • a structure 10 prior to etching may have an interconnect layer 11 in which there is formed a metal interconnect feature 18 .
  • a barrier layer 14 Overlaying layer 11 and feature 18 is a barrier layer 14 .
  • barrier layer 14 Over barrier layer 14 are two dielectric layers 12 and 13 separated by an intermediate etch stop layer 15 .
  • a patterned photoresist (“PR”) layer 16 is deposited over top dielectric layer 13 .
  • PR photoresist
  • a via feature is patterned in the photoresist layer 16 of a device or structure 10 using photolithography. As shown in FIG. 2, a via 17 is etched through the dielectric layers 13 and 12 , and the etch stop layer 15 , to the barrier layer 14 . The photoresist layer 16 is then stripped from the semiconductor device and replaced with a new or fresh photoresist layer (not shown). A trench feature is patterned in the fresh photoresist layer. As shown in FIG. 3, a trench 18 is etched through the dielectric layer 13 to the etch stop layer 15 . The fresh photoresist layer is then stripped. The etch stop layer 15 and the insulative barrier layer 14 , exposed in the via 17 , are then selectively etched. A thin copper barrier (not shown) together with a copper film 19 is then deposited in the trench 18 and via 17 . The semiconductor device is planarized using chemical mechanical planarization to form the interconnect structure shown in FIG. 4.
  • a fresh photoresist material is deposited on the device 10 , filling the via 17 .
  • a self-planarizing antireflection coating/photoresist, or ARC/photoresist is used to provide a planar surface for sufficient focusing of the photolithographic instrument.
  • Low-k dielectric materials Dielectric materials having lower dielectric constants are known as low-k dielectric materials and have become increasingly popular in the fabrication of interconnect structures of semiconductor devices.
  • the low-k dielectric materials typically have dielectric constants up to about 3.0.
  • low-k dielectric materials are chemically reactive with photoresist materials or have impurities that react with the photoresist materials when the latter comes into contact with the low-k dielectric materials.
  • a mask layer as used herein is a layer that includes a film, or composite films, that overlay a dielectric material in an interconnect structure, and serves as a barrier layer between a photoresist layer and a dielectric material.
  • a mask layer may also be referred to as a hard mask layer or photoresist mask, which terms may be used interchangeably in this disclosure. The mask layer protects specific regions of the dielectric materials during the etching process.
  • the hard mask layers known in the prior art typically include two layers of different property films.
  • the two mask films may include a first mask film usually consisting of SiC or Si 3 N 4 and a second mask film consisting of silicon dioxide (SiO 2 ).
  • the two hard mask films prevent the photoresist materials from coming into contact with the low-k dielectric material during via and trench photolithography and etching.
  • the first mask film, SiC or Si 3 N 4 protects the low-k dielectric films from chemical mechanical polishing. It also serves as an insulator or diffusion barrier for the metal film to be deposited in a trench and via where its function is to prevent surface current or metallic ion leaks from the conductive metal deposited in the trench.
  • the second hard mask film serves as a sacrificial layer where the trench or via is initially etched and is eliminated after the completion of all processes. It also helps protect the underlying dielectric layers when the via or trench pattern thereon is transferred to the underlying dielectric layers.
  • Dual damascene processes incorporating a mask layer are the partial-trench-first in a two layer hard mask (also referred to as the “PTF-2LM”), and the partial-via-first in two layer hard mask (also referred to as the “PVF-2LM”).
  • a PTF-2LM dual damascene process is illustrated in FIGS. 5 - 8 .
  • the semiconductor device 20 shown in FIG. 5 includes a dielectric material comprising a via dielectric layer 22 and a trench dielectric layer 21 deposited over an underlying interconnect layer 23 having a conductive line 24 .
  • An insulative barrier layer 25 is disposed between the metal layer 23 and the via dielectric layer 22 .
  • An etch stop layer 26 is disposed between the via dielectric layer 22 and the trench dielectric layer 21 .
  • a mask layer 27 having a first mask film 27 A and second mask film 27 B, overlays the dielectric material.
  • a photoreisist layer 28 has been deposited on the mask layer to pattern the trench feature.
  • a site for the trench feature is first patterned in the photoresist layer 28 , and then etched through the second mask film 27 B to the first mask film 27 A.
  • the photoresist layer 28 is then removed, and replaced with a fresh photoresist layer 28 A filling the trench 30 .
  • a via 29 feature is patterned in the fresh photoresist layer 28 A and etched through the dielectric layers 21 , and 22 and to the insulative barrier layer 25 .
  • the fresh photoresist layer 28 is then stripped.
  • the feature for the trench 30 which was patterned and etched in the mask layer 27 , is then etched through the trench dielectric layer 21 to the etch stop layer 26 . Since there is no photoresist material protection, an etch chemistry is chosen such that when the trench dielectric layer 21 is being etched, the first mask film of the mask layer is not etched. In a separate etching procedure, the etch stop layer 26 within the trench 30 and the barrier insulative layer 25 , within the via 29 , are selectively etched (not shown) so the via 29 may connect an underlying conductive line 24 to a conductive line formed in the trench 30 .
  • the via 29 connects the conductive line 24 to the line formed in the trench 30 .
  • the via and trench features must align satisfactorily.
  • the trench 30 is first aligned with the underlying metal line 24 , and then the via 29 is aligned with the trench 30 or the metal line 24 .
  • a misalignment of the trench 30 with the metal line 24 will impact the alignment or connectivity of the via 29 . If the via 29 is also misaligned with respect to the trench 30 , the error is compounded. Misaligned interconnect features can result in increase current leakage, via contact resistance, and via chain resistance which all lead to yield loss.
  • a via 39 feature is patterned in the photoresist layer 31 and then etched into the second mask film 32 B of dual mask layer 32 .
  • the photoresist layer 31 is stripped and replaced with a fresh photoresist layer 46 .
  • a trench 30 feature is then patterned in the fresh photoresist layer 46 .
  • a via 39 is first etched through the first mask film 32 A of mask layer 32 to a predetermine depth of trench dielectric 33 using an etch chemistry that is selective to the first mask film 32 A.
  • the trench 30 feature in the photoresist 46 is now etched into the second mask film 32 B of mask layer 32 .
  • the via 39 is etched through the via dielectric layer 34 to the insulative barrier layer 37 as shown in FIG. 11.
  • the trench 30 is then etched through the trench dielectric layer 33 in accordance with the feature previously patterned in the photoresist layer and etched in the second mask film 32 B of the mask layer 32 .
  • the etch stop layer 38 within the trench 30 and the barrier insulative layer 37 , within the via 39 are selectively etched.
  • the via 39 then connects an underlying conductive line 36 to a conductive line formed in the trench 30 .
  • FIG. 13 a semiconductor device is shown having a via 41 etched to predetermined depth of a mask layer 40 having a first mask film 40 A and a second mask film 40 B.
  • a photoresist layer 42 is deposited over the mask layer 40 , and a trench feature 43 is shown patterned in the photoresist layer 42 through the second mask film 40 B.
  • the trench feature 43 is misaligned with respect to the partially etched via 41 in the mask layer 40 .
  • the via 41 dimension is not fully etched in the dielectric material.
  • the dashed line in FIG. 14, represents the originally patterned dimension of the via 41 .
  • the entire dimension of the via 41 cannot be etched through the dielectric material. Accordingly, the via size has been reduced.
  • the trench 45 is then etched in the dielectric material and displaced to a side of the conductive line 44 as a result of the misalignment. The reduction in the via size which may lead to increase in via contact and chain resistances and poor device reliability and yield.
  • the present invention solves the foregoing problems with the use of a novel mask layer in the dual damascene fabrication of an interconnect structure.
  • the mask layer may be especially effective with a low-k dielectric material.
  • a low-k dielectric material or low-k dielectric layer as used in this specification, comprises those organosilicate dielectric materials and organic dielectric materials having dielectric constants up to about 3.
  • a mask layer is deposited over a dielectric material which overlays an underlying metallic layer.
  • the mask layer has four mask films including a first mask film that serves as an insulative film and/or a passivation layer (also referred to as the “passivation mask film”).
  • the mask films' composition are such that the first mask film has etch properties that are substantially identical to the etch properties of the third mask film while the second mask film has an etch properties that are substantially identical to the etch properties of the fourth mask film.
  • etch properties as used in this specification are those characteristics of a film or layer composition including the etch rate and etch selectivity for a given etch chemistry and/or etching procedure.
  • the first mask film and the third mask film comprise SiO 2 or SiC, which are known film composition for mask films. Alternatively, these mask films may also comprise Si 3 N 4 , or some other suitable compound that has an acceptable etch selectivity with respect to the dielectric material.
  • the second mask film and the fourth mask film are similarly composed of the same materials chosen to have an appropriate etch selectivity with respect to the dielectric material.
  • a via feature and trench feature are patterned and then etched in the mask layer.
  • the via feature is etched to a predetermined depth of the mask layer, or through the first three films.
  • the trench feature is also etched to a predetermined depth of the mask layer but only through the first mask film.
  • the dual damascene process may incorporate a partial via first (or “PVF”) procedure in which the via is formed in the mask layer before the trench to avoid the misalignment problems of a partial trench first (“PTF”) procedure.
  • PVF partial via first
  • the via and/or the trench are not transferred to the underlying dielectric material until both the via and the trench are first etched into the mask layer, and any photoresist material is stripped from the device. In this manner, the via can be fully transferred to the dielectric material without reducing the width of the via despite the misalignment of the trench with a trench in the underlying interconnect layer.
  • a via and trench are then etched in the dielectric material in accordance with the features patterned and etched in the mask layer.
  • the sacrificial films are removed during the steps of etching the via, trench, etch stop layer or insulative barrier, depending on the etch chemistry of the selected films or layers, or during chemical mechanical polishing when the processes are completed.
  • the via and trench are etched within the dielectric layer, and a conductive metal is deposited therein, the conductive metal is planarized using chemical mechanical planarization to complete the interconnect structure.
  • FIGS. 1 through 4 illustrate a full-via-first dual damascene process
  • FIGS. 5 through 8 illustrate a partial-trench-first with two layer hard mask (PTF-2LHM) dual damascene process
  • FIGS. 9 through 12 illustrate a partial-via-first with two layer hard mask (PVF-2LHM) dual damascene process
  • FIGS. 13 and 14 illustrate a PVF-2LHM dual damascene process in which the via size has been reduced
  • FIGS. 15 through 26 illustrate the novel mask layer and dual damascene process of the present invention.
  • FIGS. 27 through 29 illustrate the novel mask layer and dual damascene process of the present invention when a trench has been misaligned on a semiconductor device.
  • FIG. 1 A sectional view of an interconnect layer of an integrated circuit device or structure is shown in FIG. 1, and includes a low-k dielectric material including a via dielectric layer 51 and a trench dielectric layer 52 formed over an underlying interconnect layer 53 having a conductive metal 54 .
  • Via dielectric refers to the portion of a dielectric layer in which a via is formed.
  • a trench dielectric layer refers to a dielectric layer in which a trench is formed.
  • the via dielectric layer 51 is first deposited over a barrier layer 55 .
  • the via dielectric layer 51 may comprise any organosilicate or organic low-k dielectric material having a dielectric constant up to about 3.0.
  • Standard dielectric materials and such low-k dielectric materials used are CORAL manufactured by Novellus, BLACK DIAMOND manufactured by Applied Materials, or SILK manufactured by Dow Chemical Company, Inc.
  • An etch stop layer 56 is then deposited over the via dielectric layer 51 .
  • a trench dielectric layer 52 is formed over the etch stop layer 56 and comprises the same dielectric material used in the via dielectric layer 51 .
  • the via dielectric layer 51 may typically range in thickness from about 3000 to about 6000 A, and the trench dielectric layer 52 may range in thickness from about 1500 A to about 6000 A.
  • the etch stop layer 56 and the insulative barrier layer 55 have a thickness ranging up to about 500 A.
  • the insulative barrier layer 55 usually comprises silicon nitride (Si 3 N 4 ) or silicon carbide (SiC). Silicon dioxide is typically not an acceptable component for a barrier layer; however, the etch stop layer may comprise any of the three materials including SiO 2 , Si 3 N 4 or SiC.
  • a mask layer 57 is then deposited over the trench dielectric layer 52 .
  • the mask layer 57 serves as a barrier between the dielectric material and a photoresist layer 62 deposited on the mask layer 57 .
  • the mask layer 57 depicted in FIG. 15 has four mask films including a first mask film 58 , a second mask film 59 , a third mask film 60 and a fourth mask film 61 .
  • the mask films 58 through 61 range from about 200 A to 1000 A each in thickness, and are composed of a material having a sufficiently high etch selectivity with respect to the dielectric material to effectively transfer a via or trench feature patterned in the mask layer to the underlying dielectric material.
  • mask films are typically composed of Si 3 N 4 , SiO 2 or SiC.
  • the first mask film 58 should have etch properties, for a given etch chemistry and/or procedure, that are substantially identical to the etch properties of the third mask film 60 .
  • the second mask film 59 should have etch properties substantially identical to the etch properties of the fourth mask film 61 . If the first mask film 58 is composed of Si 3 N 4 , then the third mask film 60 is preferably composed of Si 3 N 4 ; and if the second mask film 59 is composed of SiO 2 , or SiC, then the fourth mask film 61 is composed of SiO 2 , or SiC. Thus, composition and the etch properties of the mask films 58 through 61 should alternate from the first mask film 58 to the fourth mask film 61 .
  • the first mask film 58 is a passivation layer.
  • the passivation layer protects the underlying dielectric layers 51 and 52 from contamination.
  • the first mask film 58 serves as an insulator.
  • the first mask film 58 remains as a component of the interconnect structure and prevents surface current leakage between conductive lines.
  • the first mask film 58 may also be referred to as a passivation mask film.
  • the dual damascene process of the present invention is depicted in the FIGS. 16 through 25.
  • the dual damascene process of the present invention generally follows the above described partial-via-first with two layer hard mask scheme, but is distinguishable in several respects as a result of the use of a four layer hard mask.
  • a via feature is first patterned in the photoresist layer 62 , and a via 63 etched in the mask layer 57 down to the first mask film 58 .
  • the photoresist layer 62 is then stripped as shown in FIG. 17.
  • a new photoresist layer 64 is formed over the mask layer 57 , filling the via 63 .
  • a trench feature is then patterned in the photoresist layer 64 .
  • a trench 65 is then etched into the mask layer 57 down to the third mask film 60 .
  • the mask layer 57 has two additional mask films, enabling a trench 65 to be first etched in the mask layer 57 , before the via 63 and the trench 65 are etched through the underlying dielectric material. As shown FIG. 19 , The photoresist layer 64 is removed before the features 63 and 65 are etched in the dielectric material. As will be explained in more detail, saving the trench 65 in the mask layer 57 avoids reduction of via size.
  • first mask film 58 remaining within the via 63 dimension is etched, and that portion of the third mask film 60 within the trench 65 dimension is also etched in a single step.
  • first mask film 58 and third mask film 60 have similar etch chemistries and etch rates, or are composed of the same compound so these portions of the mask films 56 and 60 will be removed in the same etch steps.
  • a via 63 has been etched through the mask layer 57 and the trench dielectric layer 52 to the etch stop layer 56 .
  • the sacrificial films 59 - 61 can be sequentially removed; however, the trench feature is maintained in the mask layer 57 in order to transfer the trench 65 to the underlying dielectric material.
  • the fourth mask film 61 is removed when the trench 65 is etched into the mask film 59 .
  • the second mask film 59 has etch properties identical to that of the fourth mask film 61 , a portion of the second mask film 59 within the trench 65 pattern is also removed.
  • the etch stop layer in the illustrated embodiment has etch properties similar to the etch property of the second mask film and the fourth mask film 61 . Accordingly, the etch stop layer 56 is removed when portions of the fourth mask film 61 and second mask film 69 are removed as shown in FIG. 23.
  • the etch stop layer comprises a material having an etch property similar to that of the first mask film and third mask film 60 , portions of the mask films 58 and 60 may be removed during the etching procedure for the etch stop layer.
  • first mask film 58 in the partial trench 65 is removed so that the first mask film 58 , second mask film 59 and third mask film 60 define the trench 65 .
  • the via 63 is then etched through the via dielectric layer 51 down to the barrier layer 55 , and the trench 65 is simultaneously etched through the trench dielectric layer 52 as shown in FIG. 24.
  • the barrier layer 55 is then selectively etched to expose conductive line 54 as shown in FIG. 25, and the remaining portion for third mask film 60 may be removed.
  • the only remaining mask film of the mask layer 57 is the first mask film 58 , and the second mask film 59 .
  • the first mask film 58 is the passivation layer and will be part of the device structure after processing.
  • a conductive metal 66 is deposited in the via 63 and the trench 65 .
  • a thin copper barrier layer and copper seed layer are first deposited using sputtering or chemical vapor deposition techniques (CVD), which is followed by a thick copper film deposition to fill the via 63 and trench 65 using electroplating.
  • Chemical mechanical planarization (CMP) is used to eliminate excess conductive metal outside the trench 65 , and remove remnants of the mask films 59 - 60 , so the first mask film 58 remains adjacent the conductive metal 66 .
  • CMP chemical mechanical planarization
  • the interconnect structure shown in FIG. 26 is created using a dual damascene procedure, and includes a via 63 electrically connecting the underlying conductive line 54 with a conductive line formed in the trench 65 .
  • a trench feature 69 is shown misaligned with respect to the via 68 when patterned in a photoresist layer 67 .
  • a via 68 is first patterned in a photoresist layer and etched in the mask layer 66 .
  • the photoresist layer is removed and replaced with photoresist layer 67 as shown in FIG. 27.
  • a trench feature 69 is patterned in the phototresist layer 67 ; however, the trench feature is misaligned, or displaced to a side of the via 68 .
  • a trench 75 is then etched through photoresist layer 67 and into the mask layer 66 through the fourth mask film 73 .
  • the photoresist layer 67 is removed, as shown in FIG. 29, the via 68 and trench 75 are formed in the mask layer 66 .
  • the photoresist material is removed from the via 68 , so the misalignment of the trench 75 does not result in the reduction of the size of the via 68 .
  • the trench 75 is patterned in the mask layer 66 , so the photoresist layer can be stripped from the device, before the trench and the via are etched any further.
  • the photoresist layer 67 is removed the entire width of the via 68 is exposed to the etching procedures, thus the via size cannot be reduced even if the trench has been misaligned.

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US10/026,257 2001-12-21 2001-12-21 Mask layer and dual damascene interconnect structure in a semiconductor device Abandoned US20030119305A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US10/026,257 US20030119305A1 (en) 2001-12-21 2001-12-21 Mask layer and dual damascene interconnect structure in a semiconductor device
GB0226986A GB2390741B (en) 2001-12-21 2002-11-19 A mask layer dual damascene interconnect structure in a semiconductor device
TW091133996A TWI254375B (en) 2001-12-21 2002-11-21 A mask layer and interconnect structure for dual damascene fabrication of a semiconductor device
JP2002337918A JP4486303B2 (ja) 2001-12-21 2002-11-21 半導体装置の相互接続構造においてバイアとトレンチの間に生じ得るミスアライメントに起因する影響を回避するための方法
KR1020020081701A KR20030053055A (ko) 2001-12-21 2002-12-20 반도체 장치의 상호 접속 구조체 형성 방법
US10/721,126 US7067419B2 (en) 2001-12-21 2003-11-25 Mask layer and dual damascene interconnect structure in a semiconductor device
JP2009161396A JP2009224816A (ja) 2001-12-21 2009-07-08 半導体装置のマスク層および二重ダマシーン相互接続構造

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Cited By (28)

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US20030186534A1 (en) * 2002-03-26 2003-10-02 Hidetaka Nambu Method for manufacturing semiconductor device using dual-damascene techniques
US20030219973A1 (en) * 2002-04-02 2003-11-27 Townsend Paul H. Tri-layer masking architecture for patterning dual damascene interconnects
US20040137711A1 (en) * 2002-10-30 2004-07-15 Takatoshi Deguchi Method for manufacturing semiconductor device
US6767825B1 (en) * 2003-02-03 2004-07-27 United Microelectronics Corporation Etching process for forming damascene structure of the semiconductor
US20040175932A1 (en) * 2003-03-06 2004-09-09 Samsung Electronics Co., Ltd. Method of forming a via contact structure using a dual damascene technique
US20040198037A1 (en) * 2003-03-18 2004-10-07 Fujitsu Limited Method for manufacturing semiconductor device
US20050070105A1 (en) * 2003-03-14 2005-03-31 Lam Research Corporation Small volume process chamber with hot inner surfaces
US20050090093A1 (en) * 2003-03-14 2005-04-28 Lam Research Corporation Stress free etch processing in combination with a dynamic liquid meniscus
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