US11444010B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US11444010B2
US11444010B2 US17/060,545 US202017060545A US11444010B2 US 11444010 B2 US11444010 B2 US 11444010B2 US 202017060545 A US202017060545 A US 202017060545A US 11444010 B2 US11444010 B2 US 11444010B2
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bonding material
semiconductor chip
bonding
semiconductor device
metal plate
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US17/060,545
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US20210118781A1 (en
Inventor
Kazunori Hasegawa
Yuichi Yato
Hiroyuki Nakamura
Yukihiro Sato
Hiroya SHIMOYAMA
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Renesas Electronics Corp
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Renesas Electronics Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YATO, YUICHI, NAKAMURA, HIROYUKI, SHIMOYAMA, Hiroya, HASEGAWA, KAZUNORI, SATO, YUKIHIRO
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device, and can be suitably used for, for example, a semiconductor device in which a semiconductor chip including a field effect transistor for switching is sealed.
  • An inverter circuit widely used as an example of a power supply circuit has a configuration in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series between a terminal to which a power supply voltage is supplied and a terminal to which a ground voltage is supplied.
  • a control circuit By controlling a gate voltage of the power MOSFET for high side switch and a gate voltage of the power MOSFET for low side switch by a control circuit, the power supply voltage can be converted by the inverter circuit.
  • Patent Document 1 discloses a technology relating to a semiconductor device in which a semiconductor chip including a power MOSFET for high side switch, a semiconductor chip including a power MOSFET for low side switch, and a semiconductor chip for controlling them are sealed.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2018-121035
  • a semiconductor device includes: a first semiconductor chip including a first field effect transistor for switching; a first chip mounting portion on which the first semiconductor chip is mounted via a first bonding material; a first lead electrically connected to a first pad for source of the first semiconductor chip through a first metal plate; a first metal portion formed integrally with the first lead; and a sealing body for sealing them.
  • a first back surface electrode for drain of the first semiconductor chip and the first chip mounting portion are bonded via the first bonding material, the first metal plate and the first pad for source of the first semiconductor chip are bonded via a second bonding material, and the first metal plate and the first metal portion are bonded via a third bonding material.
  • the first bonding material, the second bonding material, and the third bonding material have conductivity.
  • An elastic modulus of each of the first bonding material and second bonding material is lower than that of the third bonding material.
  • FIG. 1 is a circuit diagram showing an inverter circuit using a semiconductor device according to an embodiment
  • FIG. 2 is a top view of the semiconductor device according to the embodiment.
  • FIG. 3 is a bottom view of the semiconductor device according to the embodiment.
  • FIG. 4 is a plan transparent view of the semiconductor device according to the embodiment.
  • FIG. 5 is a plan transparent view of the semiconductor device according to the embodiment.
  • FIG. 6 is a plan transparent view of the semiconductor device according to the embodiment.
  • FIG. 7 is a cross-sectional view of the semiconductor device according to the embodiment.
  • FIG. 8 is a cross-sectional view of the semiconductor device according to the embodiment.
  • FIG. 9 is a cross-sectional view of the semiconductor device according to the embodiment.
  • FIG. 10 is a cross-sectional view of the semiconductor device according to the embodiment.
  • FIG. 11 is a plan view of the semiconductor device in a manufacturing process according to the embodiment.
  • FIG. 12 is a plan view of the semiconductor device in the manufacturing process continued from FIG. 11 ;
  • FIG. 13 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 12 ;
  • FIG. 14 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 12 ;
  • FIG. 15 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 12 ;
  • FIG. 16 is a plan view of the semiconductor device in the manufacturing process continued from FIG. 12 ;
  • FIG. 17 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 16 ;
  • FIG. 18 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 16 ;
  • FIG. 19 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 16 ;
  • FIG. 20 is a plan view of the semiconductor device in the manufacturing process continued from FIG. 16 ;
  • FIG. 21 is a cross-sectional view of the semiconductor device in the manufacturing process continued from FIG. 20 ;
  • FIG. 22 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 21 ;
  • FIG. 23 is a cross-sectional view of the semiconductor device in the manufacturing process continued from FIG. 21 ;
  • FIG. 24 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 23 ;
  • FIG. 25 is a cross-sectional view of the semiconductor device in the manufacturing process continued from FIG. 23 ;
  • FIG. 26 is a cross-sectional view of the semiconductor device in the same manufacturing process as FIG. 25 ;
  • FIG. 27 is a cross-sectional view showing a mounting example of the semiconductor device according to the embodiment.
  • FIG. 28 is a cross-sectional view showing the mounting example of the semiconductor device according to the embodiment.
  • FIG. 29 is a cross-sectional view showing the mounting example of the semiconductor device according to the embodiment.
  • FIG. 30 is a cross-sectional view showing the mounting example of the semiconductor device according to the embodiment.
  • FIG. 31 is a table in which characteristics of a low-elastic bonding material and a high-elastic bonding material are summarized for comparison.
  • FIG. 32 is a table in which the bonding materials in each of the embodiment and another embodiment are summarized.
  • the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification, details, or a supplementary explanation thereof. Also, in the embodiments described below, when mentioning the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and the number larger or smaller than the specified number is also applicable.
  • the components are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle.
  • the shape of the components, positional relation thereof, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it is conceivable that they are apparently excluded in principle. The same goes for the numerical value and the range described above.
  • hatching is omitted even in a cross-sectional view so as to make the drawings easy to see.
  • hatching is used even in a plan view so as to make the drawings easy to see.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOS Metal Oxide Semiconductor Field Effect Transistor
  • the MOSFET includes not only the MISFET (Metal Insulator Semiconductor Field Effect Transistor) using an oxide film (silicon oxide film) for a gate insulating film but also the MISFET using an insulating film other than an oxide film (silicon oxide film) for a gate insulating film.
  • FIG. 1 is a circuit diagram showing an example of an electronic device using a semiconductor device (semiconductor package) PKG according to this embodiment, and a circuit diagram in the case where an inverter circuit INV is configured by using the semiconductor device PKG is shown here.
  • a part enclosed by a dotted line denoted by CPH is formed in a semiconductor chip CPH
  • a part enclosed by a dotted line denoted by CPL is formed in a semiconductor chip CPL
  • a part enclosed by a dotted line denoted by CPC is formed in a semiconductor chip CPC
  • a part enclosed by a one-dot chain line denoted by PKG is formed in the semiconductor device PKG.
  • the semiconductor device PKG used in the inverter circuit INV shown in FIG. 1 includes two power MOSFETs 1 and 2 , a sense MOSFET 3 for sensing a current flowing in the power MOSFET 1 , a sense MOSFET 4 for sensing a current flowing in the power MOSFET 2 , and a control circuit CLC.
  • the control circuit CLC is formed in the semiconductor chip (control semiconductor chip) CPC, the power MOSFET 1 and the sense MOSFET 3 are formed in the semiconductor chip (high-side semiconductor chip, power chip) CPH, and the power MOSFET 2 and the sense MOSFET 4 are formed in the semiconductor chip (low-side semiconductor chip, power chip) CPL. Then, these three semiconductor chips CPC, CPH, and CPL are sealed as the same package, thereby forming the semiconductor device PKG.
  • the control circuit CLC includes a high-side driver circuit that controls a gate potential of the power MOSFET 1 and a low-side driver circuit that controls a gate potential of the power MOSFET 2 .
  • the control circuit CLC is a circuit configured to control the operations of the power MOSFETs 1 and 2 by controlling the respective gate potentials of the power MOSFETs 1 and 2 in accordance with the signals supplied from a control circuit CT outside the semiconductor device PKG to the control circuit CLC.
  • a gate of the power MOSFET 1 is connected to the high-side driver circuit of the control circuit CLC and a gate of the power MOSFET 2 is connected to the low-side driver circuit of the control circuit CLC.
  • a drain D 1 of the power MOSFET 1 is connected to a terminal TE 1
  • a source S 1 of the power MOSFET 1 is connected to a terminal TE 2
  • a drain D 2 of the power MOSFET 2 is connected to a terminal TE 3
  • a source S 2 of the power MOSFET 2 is connected to a terminal TE 4 .
  • the control circuit CLC is connected to a terminal TE 5
  • the terminal TE 5 is connected to the control circuit CT provided outside the semiconductor device PKG.
  • the terminals TE 1 , TE 2 , TE 3 , TE 4 , and TE 5 are all external connection terminals of the semiconductor device PKG and are formed of leads LD described later.
  • the terminal TE 1 is a terminal to which a power supply potential (VIN) is supplied and the terminal TE 4 is a terminal to which a reference potential lower than the power supply potential, for example, ground potential (GND) is supplied.
  • the terminal TE 2 and the terminal TE 3 are electrically connected outside the semiconductor device PKG. Therefore, the power MOSFET 1 and the power MOSFET 2 are connected in series between the terminal TE 1 for supplying power supply potential and the terminal TE 4 for supplying reference potential.
  • a connection point TE 6 between the source S 1 of the power MOSFET 1 and the drain D 1 of the power MOSFET 2 is provided outside the semiconductor device PKG (for example, on a wiring board on which the semiconductor device PKG is mounted), and the connection point TE 6 is connected to a load (coil CL of a motor MOT in this case).
  • a DC power supplied to the inverter circuit INV using the semiconductor device PKG is converted into an AC power by the inverter circuit INV and is then supplied to the load (coil CL of the motor MOT in this case).
  • the power MOSFET 1 corresponds to the field effect transistor for high side switch (high-potential-side switch) and the power MOSFET 2 corresponds to the field effect transistor for low side switch (low-potential-side switch).
  • Each of the power MOSFETs 1 and 2 can be regarded as a power transistor for switching.
  • the current flowing in the power MOSFET 1 is sensed by the sense MOSFET 3 and the power MOSFET 1 is controlled in accordance with the current flowing in the sense MOSFET 3 .
  • the current flowing in the power MOSFET 2 is sensed by the sense MOSFET 4 and the power MOSFET 2 is controlled in accordance with the current flowing in the sense MOSFET 4 .
  • a drain D 3 of the sense MOSFET 3 is electrically connected to the drain D 1 of the power MOSFET 1 and a gate of the sense MOSFET 3 is electrically connected to the gate of the power MOSFET 1 .
  • a source S 3 of the sense MOSFET 3 is connected to the control circuit CLC.
  • a drain D 4 of the sense MOSFET 4 is electrically connected to the drain D 2 of the power MOSFET 2 and a gate of the sense MOSFET 4 is electrically connected to the gate of the power MOSFET 2 .
  • a source S 4 of the sense MOSFET 4 is connected to the control circuit CLC.
  • FIG. 2 is a top view of the semiconductor device PKG according to this embodiment
  • FIG. 3 is a bottom view (back-side view) of the semiconductor device PKG
  • FIGS. 4 to 6 are plan transparent views of the semiconductor device PKG
  • FIGS. 7 to 10 are cross-sectional views of the semiconductor device PKG.
  • FIG. 4 shows a plan transparent view in which the semiconductor device PKG is seen from a lower-surface side through a sealing portion MR.
  • FIG. 5 shows a plan transparent view on a lower-surface side of the semiconductor device PKG in which the semiconductor device PKG is seen through (while omitting) further wires BW and metal plates MP 1 and MP 2 in FIG. 4 .
  • FIG. 4 shows a plan transparent view in which the semiconductor device PKG is seen from a lower-surface side through a sealing portion MR.
  • FIG. 5 shows a plan transparent view on a lower-surface side of the semiconductor device PKG in which the semiconductor device PKG is seen through (while omitting) further wire
  • FIG. 6 shows a plan transparent view on a lower-surface side of the semiconductor device PKG in which the semiconductor device PKG is seen through (while omitting) further the semiconductor chips CPC, CPH, and CPL in FIG. 5 .
  • the semiconductor device PKG has the same orientation.
  • the position of the outer circumference of the sealing portion MR is indicated by a dotted line.
  • the cross section of the semiconductor device PKG at the position of a line A 1 -A 1 in FIGS. 2 to 4 almost corresponds to FIG. 7
  • the cross section of the semiconductor device PKG at the position of a line A 2 -A 2 in FIGS. 2 to 4 almost corresponds to FIG.
  • a reference sign X shown in each plan view indicates a first direction (hereinafter, referred to as X direction) and a reference sign Y indicates a second direction (hereinafter, referred to as Y direction) orthogonal to the first direction X.
  • X direction a first direction
  • Y direction a second direction orthogonal to the first direction X.
  • the X direction and the Y direction are directions orthogonal to each other.
  • the semiconductor device (semiconductor package) PKG according to this embodiment shown in FIGS. 2 to 10 is a semiconductor device of the resin-sealed semiconductor package type and is a semiconductor device of the SOP (Small Outline Package) type in this case.
  • SOP Small Outline Package
  • the configuration of the semiconductor device PKG will be described below with reference to FIGS. 2 to 10 .
  • the semiconductor device PKG according to this embodiment shown in FIGS. 2 to 10 includes die pads (chip mounting portions) DPC, DPH, and DPL, the semiconductor chips CPC, CPH, and CPL mounted on the main surfaces of the die pads DPC, DPH, and DPL, the metal plates MP 1 and MP 2 , a plurality of wires (bonding wires) BW, a plurality of leads LD, and the sealing portion (sealing body) MR that seals them.
  • the sealing portion MR as a resin sealing portion is made of a resin material such as a thermosetting resin material and can contain filler or the like.
  • the sealing portion MR can be formed by using epoxy resin containing filler.
  • epoxy-based resin for example, biphenyl-based thermosetting resin to which a phenol-based curing agent, silicone rubber, filler, or others is added may be used as the material of the sealing portion MR for the purpose of reducing stress.
  • the sealing portion MR has a main surface (upper surface) MRa, a back surface (lower surface, bottom surface) MRb on a side opposite to the main surface MRa, and side surfaces MRc 1 , MRc 2 , MRc 3 , and MRc 4 intersecting the main surface MRa and the back surface MRb.
  • the outer appearance of the sealing portion MR is a thin-plate shape surrounded by the main surface MRa, the back surface MRb, and the side surfaces MRc 1 , MRc 2 , MRc 3 , and MRc 4 .
  • the side surfaces MRc 1 , MRc 2 , MRc 3 , and MRc 4 of the sealing portion MR are located on the sides opposite to each other, the side surfaces MRc 2 and the side surface MRc 4 are located on the sides opposite to each other, the side surface MRc 1 , the side surface MRc 2 , and the side surface MRc 4 intersect each other, and the side surface MRc 3 , the side surface MRc 2 , and the side surface MRc 4 intersect each other.
  • the side surfaces MRc 1 and MRc 3 are approximately parallel to the X direction
  • the side surfaces MRc 2 and MRc 4 are approximately parallel to the Y direction.
  • each of the main surface MRa and the back surface MRb is a surface parallel to both of the X direction and the Y direction.
  • the planar shape of the sealing portion MR that is, the planar shape of the main surface MRa and the back surface MRb of the sealing portion MR is, for example, a rectangular shape (oblong shape).
  • the rectangle constituting the planar shape of the sealing portion MR is a rectangle having the sides parallel to the X direction and the sides parallel to the Y direction, and the size of the sealing portion MR in the X direction is larger than that in the Y direction.
  • Each of the plurality of leads LD has a part sealed in the sealing portion MR and the other part projecting from the side surfaces of the sealing portion MR to outside.
  • the part of the lead LD located inside the sealing portion MR is referred to as an inner lead portion
  • the part of the lead LD located outside the sealing portion MR is referred to as an outer lead portion.
  • a plating layer (not shown) such as a solder plating layer may be formed on the outer lead portion of the lead LD. Consequently, it becomes easy to mount the semiconductor device PKG on the wiring board or the like (solder mounting).
  • the semiconductor device PKG has the structure in which a part of each lead LD (outer lead portion) projects from the side surface of the sealing portion MR and the structure will be described below.
  • the structure of the semiconductor device PKG is not limited to this.
  • the plurality of leads LD include the leads LD arranged on the side close to the side surface MRc 1 of the sealing portion MR and the leads LD arranged on the side close to the side surface MRc 3 of the sealing portion MR.
  • the lead LD is not arranged on the side close to the side surface MRc 2 of the sealing portion MR and the side close to the side surface MRc 4 of the sealing portion MR.
  • the plurality of leads LD arranged on the side close to the side surface MRc 1 of the sealing portion MR extend in the Y direction and are arrayed at predetermined intervals in the X direction in plan view.
  • the plurality of leads LD arranged on the side close to the side surface MRc 3 of the sealing portion MR extend in the Y direction and are arrayed at predetermined intervals in the X direction in plan view.
  • the outer lead portion of each lead LD is bent such that the lower surface near the end portion of the outer lead portion is located on substantially the same plane as the back surface MRb of the sealing portion MR.
  • the outer lead portions of the leads LD function as external connection terminals (external terminals) of the semiconductor device PKG.
  • the plurality of leads LD of the semiconductor device PKG include leads LD 1 , LD 2 , LD 3 , LD 4 , LD 5 a , LD 5 b , LD 6 , LD 7 , and LD 8 described later.
  • the die pad DPC is a chip mounting portion for mounting the semiconductor chip CPC
  • the die pad DPH is a chip mounting portion for mounting the semiconductor chip CPH
  • the die pad DPL is a chip mounting portion for mounting the semiconductor chip CPL.
  • the planar shape of each of the die pads DPC, DPH, and DPL is, for example, a rectangular shape having the sides parallel to the X direction and the sides parallel to the Y direction. In the case of FIGS. 2 to 10 , since the size of each of the semiconductor chips CPC, CPH, and CPL in the Y direction is larger than that in the X direction, the size of each of the die pads DPC, DPH, and DPL in the Y direction is larger than that in the X direction.
  • the die pad DPH, the die pad DPC, and the die pad DPL are arranged in this order in the X direction.
  • the die pad DPC is arranged between the die pad DPH and the die pad DPL.
  • the die pad DPH and the die pad DPC are adjacent to each other in the X direction but are not in contact with each other and are separated at a predetermined interval, and a part of the sealing portion MR is interposed therebetween.
  • the die pad DPC and the die pad DPL are adjacent to each other in the X direction but are not in contact with each other and are separated at a predetermined interval, and another part of the sealing portion MR is interposed therebetween.
  • the die pads DPC, DPH, and DPL and the plurality of leads LD are made of a conductive material (metal material), and are preferably made of copper (Cu) or copper alloy. Further, the die pads DPC, DPH, and DPL, the plurality of leads LD, and lead coupling portions LB 1 , LB 2 , LB 3 , and LB 4 are preferably formed of the same material (same metal material), whereby a lead frame in which the die pads DPC, DPH, and DPL and the plurality of leads LD are coupled can be easily manufactured, and it becomes easy to manufacture the semiconductor device PKG using the lead frame.
  • the die pad DPC has a main surface DPCa on which the semiconductor chip CPC is mounted and a back surface DPCb on a side opposite to the main surface DPCa.
  • the die pad DPH has a main surface DPHa on which the semiconductor chip CPH is mounted and a back surface DPHb on a side opposite to the main surface DPHa.
  • the die pad DPL has a main surface DPLa on which the semiconductor chip CPL is mounted and a back surface DPLb on a side opposite to the main surface DPLa.
  • each of the die pads DPC, DPH, and DPL is sealed by the sealing portion MR, and the back surface DPCb of the die pad DPC, the back surface DPHb of the die pad DPH, and the back surface DPLb of the die pad DPL are exposed from the main surface MRa of the sealing portion MR in this embodiment. Consequently, the heat generated during the operation of the semiconductor chips CPC, CPH, and CPL can be dissipated to the outside of the semiconductor device PKG mainly from the back surfaces of the semiconductor chips CPC, CPH, and CPL through the die pads DPC, DPH, and DPL.
  • a plating layer made of silver (Ag) or the like may be formed in the regions where the semiconductor chips CPC, CPH, and CPL are mounted, the regions to which the wires BW are connected, and the regions to which the metal plates MP 1 and MP 2 are connected. Consequently, the semiconductor chips CPC, CPH, and CPL, the metal plates MP 1 and MP 2 , and the wires BW can be connected more accurately to the die pads DPC, DPH, and DPL, the leads LD, and the lead coupling portions LB 2 and LB 4 .
  • the semiconductor chip CPH is mounted on the main surface DPHa of the die pad DPH, with the back surface being directed to the die pad DPH.
  • the semiconductor chip CPH is mounted on the main surface DPHa of the die pad DPH via a conductive bonding material (adhesive layer) BD 1 .
  • a back surface electrode (electrode, drain electrode, back surface drain electrode) BEH is formed on the back surface (entire back surface) of the semiconductor chip CPH, and the back surface electrode BEH is bonded and electrically connected to the die pad DPH via the conductive bonding material BD 1 .
  • the semiconductor chip CPL is mounted on the main surface DPLa of the die pad DPL, with the back surface being directed to the die pad DPL.
  • the semiconductor chip CPL is mounted on the main surface DPLa of the die pad DPL via a conductive bonding material (adhesive layer) BD 2 .
  • a back surface electrode (electrode, drain electrode, back surface drain electrode) BEL is formed on the back surface (entire back surface) of the semiconductor chip CPL, and the back surface electrode BEL is bonded and electrically connected to the die pad DPL via the conductive bonding material BD 2 .
  • the semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC, with the back surface being directed to the die pad DPC.
  • the semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC via a bonding material (adhesive layer) BD 3 , but the bonding material BD 3 may be conductive or insulative.
  • the planar shape of each of the semiconductor chips CPC, CPH, and CPL is, for example, a rectangular shape, more specifically, a rectangular shape having the sides parallel to the X direction and the sides parallel to the Y direction.
  • the planar size (planar area) of the die pad DPH is larger than that of the semiconductor chip CPH
  • the planar size of the die pad DPL is larger than that of the semiconductor chip CPL
  • the planar size of the die pad DPC is larger than that of the semiconductor chip CPC.
  • the semiconductor chip CPH is included in the main surface DPHa of the die pad DPH
  • the semiconductor chip CPL is included in the main surface DPLa of the die pad DPL
  • the semiconductor chip CPC is included in the main surface DPCa of the die pad DPC.
  • the semiconductor chips CPC, CPH, and CPL are sealed in the sealing portion MR and are not exposed from the sealing portion MR.
  • the back surface electrode BEH of the semiconductor chip CPH functions as both of the drain electrode of the power MOSFET 1 and the drain electrode of the sense MOSFET 3 . Therefore, the back surface electrode BEH of the semiconductor chip CPH is electrically connected to the drain (D 1 ) of the power MOSFET 1 and the drain (D 3 ) of the sense MOSFET 3 formed in the semiconductor chip CPH. Also, the back surface electrode BEL of the semiconductor chip CPL functions as both of the drain electrode of the power MOSFET 2 and the drain electrode of the sense MOSFET 4 . Therefore, the back surface electrode BEL of the semiconductor chip CPL is electrically connected to the drain (D 2 ) of the power MOSFET 2 and the drain (D 4 ) of the sense MOSFET 4 formed in the semiconductor chip CPL.
  • the bonding materials BD 1 and BD 2 are preferably made of a paste conductive bonding material such as silver paste (silver paste bonding material).
  • the paste conductive bonding material constituting each of the bonding materials BD 1 and BD 2 is already in a cured state.
  • a bonding pad PDHG for gate, bonding pads PDHS 1 and PDHS 2 for source, a bonding pad PDHA for anode of temperature detecting diode, and a bonding pad PDHC for cathode of temperature detecting diode are arranged.
  • a bonding pad PDLG for gate, bonding pads PDLS 1 and PDLS 2 for source, a bonding pad PDLA for anode of temperature detecting diode, and a bonding pad PDLC for cathode of temperature detecting diode are arranged.
  • a plurality of bonding pads PDC are arranged on a front surface (main surface on an opposite side of back surface side) of the semiconductor chip CPC.
  • the pad PDC of the semiconductor chip CPC is electrically connected to the control circuit CLC formed in the semiconductor chip CPC through an internal wiring of the semiconductor chip CPC.
  • the pad PDHG for gate of the semiconductor chip CPH is electrically connected to the gate electrode of the power MOSFET 1 and the gate electrode of the sense MOSFET 3 formed in the semiconductor chip CPH.
  • the pad PDHS 1 for source of the semiconductor chip CPH is electrically connected to the source (S 1 ) of the power MOSFET 1 formed in the semiconductor chip CPH
  • the pad PDHS 2 for source of the semiconductor chip CPH is electrically connected to the source (S 3 ) of the sense MOSFET 3 formed in the semiconductor chip CPH.
  • the planar size (area) of the pad PDHS 1 for source is larger than that of each of the other pads PDHG, PDHS 2 , PDHA, and PDHC.
  • the pad PDLG for gate of the semiconductor chip CPL is electrically connected to the gate electrode of the power MOSFET 2 and the gate electrode of the sense MOSFET 4 formed in the semiconductor chip CPL.
  • the pad PDLS 1 for source of the semiconductor chip CPL is electrically connected to the source (S 2 ) of the power MOSFET 2 formed in the semiconductor chip CPL, and the pad PDLS 2 for source of the semiconductor chip CPL is electrically connected to the source (S 4 ) of the sense MOSFET 4 formed in the semiconductor chip CPL.
  • the planar size (area) of the pad PDLS 1 for source is larger than that of each of the other pads PDLG, PDLS 2 , PDLA, and PDLC.
  • a plurality of unit transistor cells constituting the power MOSFET 1 are formed on the semiconductor substrate constituting the semiconductor chip CPH, and the power MOSFET 1 is formed by connecting the plurality of unit transistor cells in parallel.
  • a plurality of unit transistor cells constituting the power MOSFET 2 are formed on the semiconductor substrate constituting the semiconductor chip CPL, and the power MOSFET 2 is formed by connecting the plurality of unit transistor cells in parallel.
  • Each unit transistor cell is made of, for example, a trench-gate MISFET.
  • the source-drain current of the power MOSFET ( 1 , 2 ) flows in the thickness direction of the semiconductor substrate constituting the semiconductor chip.
  • the pad PDHA is electrically connected to the anode of the temperature detecting diode and the pad PDHC is electrically connected to the cathode of the temperature detecting diode.
  • the pad PDLA is electrically connected to the anode of the temperature detecting diode and the pad PDLC is electrically connected to the cathode of the temperature detecting diode. Note that the illustration of the temperature detecting diode is omitted in the circuit diagram of FIG. 1 .
  • the pads (pads PDHG, PDHS 2 , PDHA, and PDHC in this case) other than the pad PDHS 1 for source are arranged along the side facing the semiconductor chip CPC. Then, the pads PDHG, PDHS 2 , PDHA, and PDHC other than the pad PDHS 1 for source of the semiconductor chip CPH are electrically connected to the pads PDC of the semiconductor chip CPC through the wires BW, respectively. Namely, one ends of the wires BW are connected to the pads PDHG, PDHS 2 , PDHA, and PDHC and the other ends of the wires BW are connected to the pads PDC of the semiconductor chip CPC.
  • the pads (pads PDLG, PDLS 2 , PDLA, and PDLC in this case) other than the pad PDLS 1 for source are arranged along the side facing the semiconductor chip CPC. Then, the pads PDLG, PDLS 2 , PDLA, and PDLC other than the pad PDLS 1 for source of the semiconductor chip CPL are electrically connected to the pads PDC of the semiconductor chip CPC through the wires BW, respectively. Namely, one ends of the wires BW are connected to the pads PDLG, PDLS 2 , PDLA, and PDLC and the other ends of the wires BW are connected to the pads PDC of the semiconductor chip CPC.
  • the wire (bonding wire) BW is a conductive connecting member and is more specifically a conductive wire. Since the wire BW is made of metal, it can be regarded also as a metal wire (metal thin wire). A gold (Au) wire, a copper (Cu) wire, an aluminum (Al) wire, or the like can be suitably used as the wire BW.
  • the wire BW is sealed in the sealing portion MR and is not exposed from the sealing portion MR.
  • the part of each lead LD to which the wire SW is connected is the inner lead portion located inside the sealing portion MR.
  • the pad PDHS 1 for source of the semiconductor chip CPH is electrically connected to the lead coupling portion (lead wiring portion, metal portion) LB 2 through the metal plate MP 1 .
  • the metal plate MP 1 is bonded to the pad PDHS 1 for source of the semiconductor chip CPH via a conductive bonding material (adhesive layer) BD 4 and is bonded to the lead coupling portion LB 2 via a conductive bonding material (adhesive layer) BD 5 .
  • the lead coupling portion LB 2 can be regarded also as a metal portion for bonding the metal plate MP 1 via the bonding material BD 5 .
  • the pad PDLS 1 for source of the semiconductor chip CPL is electrically connected to the lead coupling portion (lead wiring portion, metal portion) LB 4 through the metal plate MP 2 .
  • the metal plate MP 2 is bonded to the pad PDLS 1 for source of the semiconductor chip CPL via a conductive bonding material (adhesive layer) BD 6 and is bonded to the lead coupling portion LB 4 via a conductive bonding material (adhesive layer) BD 7 .
  • the lead coupling portion LB 4 can be regarded also as a metal portion for bonding the metal plate MP 2 via the bonding material BD 7 .
  • the metal plate MP 1 is used instead of a wire for electrically connecting the pad PDHS 1 for source of the semiconductor chip CPH and the lead LD 2 .
  • the on resistance of the power MOSFET 1 can be reduced.
  • the metal plate MP 2 is used instead of a wire for electrically connecting the pad PDLS 1 for source of the semiconductor chip CPL and the lead LD 4 .
  • the on resistance of the power MOSFET 2 can be reduced. Consequently, the package resistance can be reduced and the conduction loss can be reduced.
  • the bonding materials BD 4 , BD 5 , BD 6 , and BD 7 are preferably made of a paste conductive bonding material such as a silver paste (silver paste bonding material).
  • a paste conductive bonding material such as a silver paste (silver paste bonding material).
  • the paste conductive bonding material constituting each of the bonding materials BD 4 , BD 5 , BD 6 , and BD 7 is already in a cured state.
  • the metal plates MP 1 and MP 2 are conductor plates made of a conductive material and are preferably formed of the same material (same metal material) as those of the die pads DPH, DPL, and DPC, the leads LD, and the lead coupling portions LB 1 , LB 2 , LB 3 , and LB 4 . Therefore, the metal plates MP 1 and MP 2 are preferably made of copper (Cu) or copper (Cu) alloy. The size (width) of each of the metal plates MP 1 and MP 2 in the X direction and the Y direction is larger than the diameter of the wire BW.
  • the heat generated in the semiconductor chips CPH and CPL is dissipated from the front surfaces of the semiconductor chips CPH and CPL through the metal plates MP 1 and MP 2 as well as the back surfaces of the semiconductor chips CPH and CPL through the die pads DPH and DPL, and it is thus possible to improve the heat dissipation from the semiconductor chips CPH and CPL.
  • the pads PDC that are not connected to the pads of the semiconductor chip CPH and the pads of the semiconductor chip CPL are electrically connected to the leads LD 5 a and LD 5 b of the plurality of leads LD of the semiconductor device PKG.
  • one ends of the wires BW are connected to the pads PDC of the semiconductor chip CPC that are not connected to the pads of the semiconductor chip CPH and the pads of the semiconductor chip CPL, and the other ends of the wires BW are connected to the inner lead portions of the leads LD 5 a or the inner lead portions of the leads LD 5 b .
  • Each of the leads LD 5 a and LD 5 b can function as a signal transmission path between the semiconductor chip CPC in the semiconductor device PKG and the control circuit CT outside the semiconductor device PKG.
  • the leads LD 5 a are arranged on the side close to the side surface MRc 1 of the sealing portion MR, and the leads LD 5 b are arranged on the side close to the side surface MRc 3 of the sealing portion MR.
  • Each of the leads LD 5 a and LD 5 b is not connected to any of the die pads DPC, DPH, and DPL, the leads LD 1 , LD 2 , LD 3 , and LD 4 , and the lead coupling portions LB 1 , LB 2 , LB 3 , and LB 4 via conductors, and are isolated leads.
  • the lead coupling portion LB 2 is adjacent to the die pad DPG in the Y direction and extends along the side surface MRc 3 in the X direction in the sealing portion MR, but is separated from the die pad DPH.
  • the lead coupling portion LB 4 is adjacent to the die pad DPL in the Y direction and extends along the side surface MRc 1 in the X direction in the sealing portion MR, but is separated from the die pad DPL.
  • the lead coupling portions LB 2 and LB 4 are sealed in the sealing portion MR and are not exposed from the sealing portion MR.
  • the leads LD 2 of the plurality of leads LD of the semiconductor device PKG are collectively connected (coupled) to the lead coupling portion LB 2 .
  • the lead coupling portion LB 2 and the leads LD 2 are integrally formed.
  • the plurality of leads LD 2 are adjacent to each other in the X direction, and the inner lead portions of the plurality of leads LD 2 are coupled by the lead coupling portion LB 2 extending in the X direction in the sealing portion MR.
  • the plurality of leads LD 2 and the lead coupling portion LB 2 are electrically connected to the pad PDHS 1 of the semiconductor chip CPH through the metal plate MP 1 and the like and thus electrically connected to the source (S 1 ) of the power MOSFET 1 formed in the semiconductor chip CPH, and correspond to the terminal TE 2 described above.
  • the leads LD 4 of the plurality of leads LD of the semiconductor device PKG are collectively connected (coupled) to the lead coupling portion LB 4 .
  • the lead coupling portion LB 4 and the leads LD 4 are integrally formed.
  • the plurality of leads LD 4 are adjacent to each other in the X direction, and the inner lead portions of the plurality of leads LD 4 are coupled by the lead coupling portion LB 4 extending in the X direction in the sealing portion MR.
  • the plurality of leads LD 4 and the lead coupling portion LB 4 are electrically connected to the pad PDLS 1 of the semiconductor chip CPL through the metal plate MP 2 and the like and thus electrically connected to the source (S 2 ) of the power MOSFET 2 formed in the semiconductor chip CPL, and correspond to the terminal TE 4 described above.
  • the volume can be increased as compared with the case where the plurality of leads LD 2 are divided, so that the wiring resistance can be reduced and the conduction loss of the power MOSFET 1 can be reduced.
  • the plurality of leads LD 4 and the lead coupling portion LB 4 are collectively connected to the lead coupling portion LB 2 .
  • the leads LD 1 are integrally formed with the die pad DPH. Therefore, the plurality of leads LD 1 are electrically connected to the back surface electrode BEH of the semiconductor chip CPH through the die pad DPH and the conductive bonding material BD 1 , and correspond to the terminal TE 1 described above.
  • the leads LD 3 are integrally formed with the die pad DPL. Therefore, the plurality of leads LD 3 are electrically connected to the back surface electrode BEL of the semiconductor chip CPL through the die pad DPL and the conductive bonding material BD 2 , and correspond to the terminal TE 3 described above.
  • the plurality of leads LD 2 and the plurality of leads LD 4 of the semiconductor device PKG are not electrically connected.
  • the plurality of leads LD 2 and the plurality of leads LD 4 of the semiconductor device PKG are electrically connected through the wiring or the like of the wiring board by mounting the semiconductor device PKG on the wiring board or the like.
  • the plurality of leads LD 1 are arranged on the side close to the side surface MRc 1 of the sealing portion MR so as to be adjacent to the die pad DPH in the Y direction, and the plurality of leads LD 3 are arranged on the side close to the side surface MRc 3 of the sealing portion MR so as to be adjacent to the die pad DPL in the Y direction.
  • the plurality of leads LD 1 are adjacent to each other in the X direction, and the inner lead portions of the plurality of leads LD 1 are coupled by the lead coupling portion LB 1 extending in the X direction in the sealing portion MR.
  • the lead coupling portion LB 1 is integrally connected to the die pad DPH via a coupling portion LB 1 a extending in the Y direction.
  • the plurality of leads LD 3 are adjacent to each other in the X direction, and the inner lead portions of the plurality of leads LD 3 are coupled by the lead coupling portion LB 3 extending in the X direction in the sealing portion MR.
  • the lead coupling portion LB 3 is integrally connected to the die pad DPL via a coupling portion LB 3 a extending in the Y direction.
  • the plurality of leads LD 8 are integrally coupled to the die pad DPC. These leads LD 8 are used to support the die pad DPC to a frame body of the lead frame when manufacturing the semiconductor device PKG.
  • the lead LD 6 is integrally coupled to the die pad DPH. This lead LD 6 is used to support the die pad DPH to the frame body of the lead frame when manufacturing the semiconductor device PKG.
  • the lead LD 7 is integrally coupled to the die pad DPL. This lead LD 7 is used to support the die pad DPL to the frame body of the lead frame when manufacturing the semiconductor device PKG.
  • suspension leads TL integrally coupled to the die pad DPH are arranged on the side close to the side surface MRc 2 of the sealing portion MR, and suspension leads TL integrally coupled to the die pad DPL are arranged on the side close to the side surface MRc 4 of the sealing portion MR.
  • These suspension leads TL are used to support the die pads DPH and DPL to the frame body of the lead frame when manufacturing the semiconductor device PKG. The suspension leads TL are not exposed from the side surfaces of the sealing portion MR.
  • FIGS. 11 to 26 are plan views and cross-sectional views in the manufacturing process of the semiconductor device PKG according to this embodiment.
  • FIGS. 11, 12, 16 , and 20 are plan views and FIGS. 13 to 15, 17 to 19, and 21 to 26 are cross-sectional views.
  • FIGS. 13, 17, 21, 23, and 25 correspond to the cross-sectional views at the cross-sectional position corresponding to FIG. 7
  • FIGS. 14 and 18 correspond to the cross-sectional views at the cross-sectional position corresponding to FIG. 8
  • FIGS. 15, 19, 22, 24, and 26 correspond to the cross-sectional views at the cross-sectional position corresponding to FIG. 9 .
  • a lead frame LF is prepared and the semiconductor chips CPC, CPH, and CPL are prepared.
  • the order of preparing the lead frame LF and the semiconductor chips CPC, CPH, and CPL is not particularly limited, and they may be prepared simultaneously.
  • the lead frame LF integrally includes the frame body (not shown), the die pads DPC, DPH, and DPL, the plurality of leads LD, the lead coupling portions LB 1 , LB 2 , LB 3 , and LB 4 , and the suspension leads TL.
  • One ends of the respective leads LD are coupled to the frame body.
  • the die pad DPC is coupled to the frame body by the leads LD 8
  • the die pad DPH is coupled to the frame body by the leads LD 1 and LD 6 and the suspension leads TL
  • the die pad DPL is coupled to the frame body by the leads LD 3 and LD 7 and the suspension leads TL.
  • the lead frame LF is preferably made of a metal material mainly made of copper (Cu) and is specifically made of copper (Cu) or copper (Cu) alloy.
  • FIG. 11 shows the region of the lead frame LF from which one semiconductor device PKG is manufactured.
  • the die bonding process of the semiconductor chips CPH, CPL, and CPC is performed. Namely, the semiconductor chip CPH is mounted (arranged) on the main surface DPHa of the die pad DPH of the lead frame LF via the bonding material BD 1 a , the semiconductor chip CPL is mounted (arranged) on the main surface DPLa of the die pad DPL of the lead frame LF via the bonding material BD 2 a , and the semiconductor chip CPC is mounted (arranged) on the main surface DPCa of the die pad DPC of the lead frame LF via the bonding material BD 3 a .
  • the bonding material BD 1 a is applied (supplied) onto the main surface DPHa of the die pad DPH
  • the bonding material BD 2 a is applied (supplied) onto the main surface DPLa of the die pad DPL
  • the bonding material BD 3 a is applied (supplied) onto the main surface DPCa of the die pad DPC
  • the semiconductor chips CPH, CPL, and CPC may be mounted on the main surfaces DPHa, DPLa, and DPCa of the die pads DPH, DPL, and DPC, respectively.
  • each of the bonding materials BD 1 a , BD 2 a , and BD 3 a is the paste bonding material (adhesive material) and is preferably silver paste, but is not cured yet.
  • the process of arranging the metal plates MP 1 and MP 2 is performed. Specifically, first, the bonding material BD 5 a is applied (supplied) onto the lead coupling portion LB 2 , the bonding material BD 7 a is applied (supplied) onto the lead coupling portion LB 4 , the bonding material BD 4 a is applied (supplied) onto the pad PDHS 1 for source of the semiconductor chip CPH, and the bonding material BD 6 a is applied (supplied) onto the pad PDLS 1 for source of the semiconductor chip CPL. Then, as shown in FIGS.
  • the metal plate MP 1 is arranged (mounted) on the semiconductor chip CPH and the lead coupling portion LB 2 , and the metal plate MP 2 is arranged on the semiconductor chip CPL and the lead coupling portion LB 4 .
  • the metal plate MP 1 is arranged such that a part of the metal plate MP 1 is arranged on the pad PDHS 1 for source of the semiconductor chip CPH via the bonding material BD 4 a and another part of the metal plate MP 1 is arranged on the lead coupling portion LB 2 via the bonding material BD 5 a .
  • the metal plate MP 2 is arranged such that a part of the metal plate MP 2 is arranged on the pad PDLS 1 for source of the semiconductor chip CPL via the bonding material BD 6 a and another part of the metal plate MP 2 is arranged on the lead coupling portion LB 4 via the bonding material BD 7 a .
  • Each of the bonding materials BD 4 a , BD 5 a , BD 6 a , and BD 7 a is the paste bonding material (adhesive material) and is preferably silver paste, but is not cured yet.
  • the process of curing the bonding materials BD 1 a , BD 2 a , BD 3 a , BD 4 a , BD 5 a , BD 6 a , and BD 7 a (heat treatment) is performed. Consequently, the bonding material (adhesive layer) BD 1 made of the cured bonding material BD 1 a , the bonding material (adhesive layer) BD 2 made of the cured bonding material BD 2 a , and the bonding material (adhesive layer) BD 3 made of the cured bonding material BD 3 a are formed.
  • the semiconductor chip CPH is bonded and fixed to the die pad DPH by the bonding material BD 1
  • the semiconductor chip CPL is bonded and fixed to the die pad DPL by the bonding material BD 2
  • the semiconductor chip CPC is bonded and fixed to the die pad DPC by the bonding material BD 3 .
  • the metal plate MP 1 is bonded and fixed to the pad PDHS 1 for source of the semiconductor chip CPH by the bonding material BD 4 and is bonded and fixed to the lead coupling portion LB 2 by the bonding material BD 5
  • the metal plate MP 2 is bonded and fixed to the pad PDLS 1 for source of the semiconductor chip CPL by the bonding material BD 6 and is bonded and fixed to the lead coupling portion LB 4 by the bonding material BD 7 .
  • the wire bonding process is performed. Specifically, the plurality of pads (PDHG, PDHS 2 , PDHA, PDHC) of the semiconductor chip CPH and the plurality of pads (PDC) of the semiconductor chip CPC are electrically connected through the wires BW, the plurality of pads (PDLG, PDLS 2 , PDLA, PDLC) of the semiconductor chip CPL and the plurality of pads (PDC) of the semiconductor chip CPC are electrically connected through the wires BW, and the plurality of pads (PDC) of the semiconductor chip CPC and the plurality of leads (LD 5 a , LD 5 b ) of the lead frame LF are electrically connected through the wires BW.
  • the plurality of pads (PDHG, PDHS 2 , PDHA, PDHC) of the semiconductor chip CPH and the plurality of pads (PDC) of the semiconductor chip CPC are electrically connected through the wires BW
  • wires BW It is also possible to use multiple types of wires made of different materials as the wires BW.
  • the plurality of pads (PDC) of the semiconductor chip CPC and the plurality of leads (LD 5 a , LD 5 b ) of the lead frame LF are electrically connected through the wires SW made of copper (Cu).
  • the plurality of pads (PDHG, PDHS 2 , PDHA, PDHC) of the semiconductor chip CPH and the plurality of pads (PDC) of the semiconductor chip CPC are electrically connected through the wires BW made of gold (Au), and the plurality of pads (PDLG, PDLS 2 , PDLA, PDLC) of the semiconductor chip CPL and the plurality of pads (PDC) of the semiconductor chip CPC are electrically connected through the wires BW made of gold (Au).
  • the molding process (process of forming sealing portion MR) is performed. Specifically, first, as shown in FIGS. 21 and 22 , the lead frame LF is sandwiched by a molding die (lower molding die) KG 1 and a molding die (upper molding die) KG 2 .
  • the lead frame LF is sandwiched by the molding die KG 1 and the molding die KG 2 such that the die pads DPH, DPL, and DPC, the semiconductor chips CPH, CPL, and CPC, the metal plates MP 1 and MP 2 , the wires BW, the inner lead portions of the leads LD, and the lead coupling portions LB 1 , LB 2 , LB 3 , and LB 4 are arranged in a cavity CAV between the molding dies KG 1 and KG 2 .
  • Each of the back surfaces DPCb, DPHb, and DPLb of the die pads DPH, DPL, and DPC is in contact with the upper surface of the molding die KG 1 .
  • the outer lead portions of the leads LD are located outside the cavity CAV and sandwiched between the molding die KG 1 and the molding die KG 2 .
  • a resin material MR 1 for forming the sealing portion MR is injected (introduced) into the cavity CAV between the molding dies KG 1 and KG 2 .
  • the resin material MR 1 to be injected is made of, for example, a thermosetting resin material, and can contain filler or the like.
  • the process of curing the resin material MR 1 injected into the cavity CAV heat treatment
  • the sealing portion MR made of the cured resin material MR 1 is formed.
  • the molding die KG 1 and the molding die KG 2 are separated, and the lead frame LF is taken out together with the sealing portion MR as shown in FIG. 25 and FIG. 26 .
  • the sealing portion MR in which the semiconductor chips CPC, CPH, and CPL, the die pads DPC, DPH, and DPL, the plurality of wires BW, the metal plates MP 1 and MP 2 , the lead coupling portions LB 1 , LB 2 , LB 3 , and LB 4 , and the inner lead portions of the plurality of leads LD are sealed is formed.
  • the sealing portion MR is formed in the molding process such that the back surfaces DPCb, DPHb, and DPLb of the die pads DPC, DPH, and DPL are exposed from the main surface MRa of the sealing portion MR.
  • the processes up to this molding process are performed in the state where the main surfaces DPCa, DPHa, and DPLa of the die pads DPC, DPH, and DPL are directed upward. Therefore, at the stage where the sealing portion MR is formed by performing the molding process, the back surface MRb of the sealing portion MR is directed upward.
  • the semiconductor device PKG is mounted on the wiring board or the like, the semiconductor device PKG is mounted on the wiring board such that the back surface MRb of the sealing portion MR faces the wiring board.
  • a plating layer (not shown) is formed on each of the outer lead portions of the leads LD exposed from the sealing portion MR as needed. Thereafter, the top and bottom (front and back) of the lead frame LF are inverted together with the sealing portion MR, and then the leads LD are cut at predetermined positions outside the sealing portion MR and separated from the frame body of the lead frame LF.
  • the semiconductor device PKG shown in FIGS. 2 to 10 is manufactured.
  • FIGS. 27 to 30 are cross-sectional views showing the state where the semiconductor device PKG is mounted on a wiring board PB 1 .
  • FIG. 27 corresponds to the cross-sectional view at the cross-sectional position corresponding to FIG. 7
  • FIG. 28 corresponds to the cross-sectional view at the cross-sectional position corresponding to FIG. 8
  • FIG. 29 corresponds to the cross-sectional view at the cross-sectional position corresponding to FIG. 9
  • FIG. 30 corresponds to the cross-sectional view at the cross-sectional position corresponding to FIG. 10 .
  • the semiconductor device PKG is mounted on a main surface PB 1 a of the wiring board PB 1 , with the back surface MRb of the sealing portion MR being directed to the main surface (upper surface) PB 1 a of the wiring board PB 1 .
  • the plurality of leads LD of each semiconductor device PKG are bonded and fixed to a plurality of terminals (electrodes) TM formed on the main surface PB 1 a of the wiring board PB 1 via conductive bonding materials SD such as solder.
  • the plurality of leads LD of each semiconductor device PKG are electrically connected to the plurality of terminals TM formed on the main surface PB 1 a of the wiring board PB 1 via the conductive bonding materials SD.
  • the bonding material SD is preferably made of solder.
  • a heat sink (chassis) HS is arranged (mounted) via an insulating adhesive material BD 11 on the main surface MRa of the sealing portion MR of the semiconductor device PKG mounted on the wiring board PB 1 .
  • insulating adhesive material BD 11 for example, a heat conductive grease having an insulating property can be used.
  • heat sink HS for example, a fin type heat sink can be used.
  • the back surfaces DPCb, DPHb, and DPLb of the die pads DPC, DPH, and DPL are exposed from the main surface MRa of the sealing portion MR, and the back surfaces DPCb, DPHb, and DPLb of the die pads DPC, DPH, and DPL are bonded to the head sink HS via the insulating bonding material BD 11 . Consequently, the heat generated in the semiconductor chips CPC, CPH, and CPL in the semiconductor device PKG can be dissipated to the heat sink HS through the die pads DPC, DPH, and DPL and the adhesive material BD 11 (heat conductive grease).
  • the heat sink HS with a large heat capacity can be attached to the semiconductor device PKG while preventing the die pads DPC, DPH, and DPL of the semiconductor device PKG from being electrically connected to each other through the adhesive material BD 11 and the heat sink HS.
  • the main feature of this embodiment lies in the proper setting of an elastic modulus of the bonding materials (adhesive layers) BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 in the semiconductor device PKG.
  • the elastic modulus of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is lower than that of each of the bonding materials BD 5 and BD 7 .
  • the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 have a low elastic modulus
  • the bonding materials BD 5 and BD 7 have a high elastic modulus.
  • the low-elastic bonding material is used as the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6
  • the high-elastic bonding material is used as the bonding materials BD 5 and BD 7 .
  • the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 have conductivity, while the bonding material BD 3 may be conductive or insulative depending on cases.
  • the bonding material BD 3 (BD 3 a ) is made of the same material as that of the bonding materials BD 1 and BD 2 (BD 1 a , BD 2 a ). Consequently, the manufacturing process of the semiconductor device PKG (more specifically, die bonding process) can be simplified, and the manufacturing cost of the semiconductor device PKG can be reduced.
  • the bonding material BD 3 (BD 3 a ) is made of the same material as that of the bonding materials BD 1 and BD 2 (BD 1 a , BD 2 a ), the bonding material BD 3 also has conductivity.
  • FIG. 31 is a table in which characteristics of a low-elastic bonding material and a high-elastic bonding material are summarized for comparison, and shows the case where both of the low-elastic bonding material and the high-elastic bonding material are made of silver paste.
  • the low-elastic bonding material has a lower elastic modulus than that of the high-elastic bonding material. Also, as can be seen from the table of FIG. 31 , the low-elastic bonding material has a lower silver (Ag) content than that of the high-elastic bonding material. This is because when the ratio of silver (Ag) in the bonding material is lowered, the ratio of the resin component in the bonding material is increased and the elastic modulus is decreased accordingly.
  • the low-elastic bonding material has a lower thermal conductivity and a higher volume resistivity (electric resistivity) than those of the high-elastic bonding material. This is because when the silver (Ag) content is low, the thermal conductivity is reduced and the volume resistivity (electric resistivity) is increased, so that the low-elastic bonding material having a lower silver (Ag) content as compared with the high-elastic bonding material having a higher silver (Ag) content has a low thermal conductivity and a high volume resistivity.
  • the high-elastic bonding material is applied to the bonding materials BD 5 and BD 7
  • the low-elastic bonding material is applied to the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 .
  • Each of the bonding materials BD 1 , BD 2 , and BD 3 is the bonding material for bonding the semiconductor chip (CPH, CPL, CPC) to the die pad (DPH, DPL, DPC).
  • the semiconductor chips CPH and CPL are both semiconductor chips in which a field effect transistor (power transistor) for switching is formed, a large amount of heat is generated during operation. Therefore, the semiconductor chips CPH and CPL can be heat sources.
  • the thermal expansion coefficient of the die pad (DPH, DPL, DPC) and the thermal expansion coefficient of the semiconductor chip (CPH, CPL, CPC) are different from each other.
  • the bonding materials BD 1 and BD 2 , and the die pads DPH and DPL are increased due to the heat generation during the operation of the semiconductor chips CPH and CPL, the strong stress is generated in the bonding materials BD 1 and BD 2 interposed between the die pads DPH and DPL and the semiconductor chips CPH and CPL due to the difference in thermal expansion coefficient between the die pads DPH and DPL and the semiconductor chips CPH and CPL.
  • This stress may lead to the occurrence of cracks in the bonding materials BD 1 and BD 2 . Since the occurrence of cracks in the bonding materials BD 1 and BD 2 interposed between the die pads DPH and DPL and the semiconductor chips CPH and CPL may cause the reduction in reliability of the semiconductor device PKG, it is desirable to prevent it.
  • the elastic modulus of the bonding materials BD 1 and BD 2 is reduced, and it is thus preferable that the low-elastic bonding material is applied as the bonding materials BD 1 and BD 2 .
  • the elastic modulus of the bonding materials BD 1 and BD 2 is reduced, the cracks are less likely to occur in the bonding materials BD 1 and BD 2 even if the temperatures of the semiconductor chips CPH and CPL, the bonding materials BD 1 and BD 2 , and the die pads DPH and DPL are increased due to the heat generation of the semiconductor chips CPH and CPL and the stress due to the difference in thermal expansion coefficient between the die pads DPH and DPL and the semiconductor chips CPH and CPL is generated in the bonding materials BD 1 and BD 2 .
  • the cracks caused by the stress generated in the bonding materials BD 1 and BD 2 due to the heat generation in the semiconductor chips CPH and CPL are less likely to occur in the bonding materials BD 1 and BD 2 in the case where the elastic modulus of the bonding materials BD 1 and BD 2 is low.
  • the stress (strain) to be generated in the bonding materials BD 1 and BD 2 due to the difference in thermal expansion coefficient between the die pads DPH and DPL and the semiconductor chips CPH and CPL when the semiconductor chips CPH and CPL generate heat can be suppressed, so that the occurrence of cracks in the bonding materials BD 1 and BD 2 can be suppressed. Since the occurrence of cracks in the bonding materials BD 1 and BD 2 can be suppressed, the reliability of the semiconductor device PKG can be improved.
  • the connection resistance between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH and the connection resistance between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL increase, resulting in the increase in the on resistance (resistance at conduction) of the power MOSFETs 1 and 2 .
  • the ratio (sense ratio) between the current flowing in the sense MOSFETs 3 and 4 and the current flowing in the power MOSFETs 1 and 2 varies, so that the sensing accuracy of the current of the power MOSFETs 1 and 2 by the sense MOSFETs 3 and 4 is decreased. Since the elastic modulus of the bonding materials BD 1 and BD 2 is reduced in this embodiment, the occurrence of cracks in the bonding materials BD 1 and BD 2 can be suppressed, and it is thus possible to prevent such a problem.
  • the amount of heat generated in the semiconductor chip CPC during operation is smaller as compared with those of the semiconductor chips CPH and CPL. Therefore, there is low risk of the occurrence of cracks in the bonding material BD 3 even when the elastic modulus of the bonding material BD 3 is not reduced.
  • any of the low-elastic bonding material and the high-elastic bonding material may be applied to the bonding material BD 3 .
  • the bonding material BD 3 may be conductive or insulative.
  • the same material as that of the bonding materials BD 1 and BD 2 (BD 1 a , BD 2 a ) is used to form the bonding material BD 3 (BD 3 a ), and it is thus preferable that the low-elastic bonding material is applied to the bonding material BD 3 similarly to the bonding materials BD 1 and BD 2 .
  • the manufacturing process of the semiconductor device PKG (more specifically, die bonding process) can be simplified, and the manufacturing cost of the semiconductor device PKG can be reduced.
  • the bonding materials BD 4 and BD 6 are the bonding materials for bonding the metal plates MP 1 and MP 2 to the pads PDHS 1 and PDLS 1 of the semiconductor chips CPH and CPL. As described above, the amount of heat generated in the semiconductor chips CPH and CPL is large, and the semiconductor chips CPH and CPL can be heat sources. Also, since the metal plates MP 1 and MP 2 and the semiconductor chips CPH and CPL are made of different materials, the thermal expansion coefficient of the metal plates MP 1 and MP 2 and the thermal expansion coefficient of the semiconductor chips CPH and CPL are different from each other.
  • the elastic modulus of the bonding materials BD 4 and BD 6 is reduced, and it is thus preferable that the low-elastic bonding material is applied as the bonding materials BD 4 and BD 6 .
  • the elastic modulus of the bonding materials BD 4 and BD 6 is reduced, the cracks are less likely to occur in the bonding materials BD 4 and BD 6 even if the temperatures of the semiconductor chips CPH and CPL, the bonding materials BD 4 and BD 6 , and the metal plates MP 1 and MP 2 are increased due to the heat generation of the semiconductor chips CPH and CPL and the stress due to the difference in thermal expansion coefficient between the metal plates MP 1 and MP 2 and the semiconductor chips CPH and CPL is generated in the bonding materials BD 4 and BD 6 .
  • the cracks caused by the stress generated in the bonding materials BD 4 and BD 6 due to the heat generation in the semiconductor chips CPH and CPL are less likely to occur in the bonding materials BD 4 and BD 6 in the case where the elastic modulus of the bonding materials BD 4 and BD 6 is low.
  • the stress (strain) to be generated in the bonding materials BD 4 and BD 6 due to the difference in thermal expansion coefficient between the metal plates MP 1 and MP 2 and the semiconductor chips CPH and CPL when the semiconductor chips CPH and CPL generate heat can be suppressed, so that the occurrence of cracks in the bonding materials BD 4 and BD 6 can be suppressed. Since the occurrence of cracks in the bonding materials BD 4 and BD 6 can be suppressed, the reliability of the semiconductor device PKG can be improved.
  • the connection resistance between the pad PDHS 1 of the semiconductor chip CPH and the metal plate MP 1 and the connection resistance between the pad PDSL 1 of the semiconductor chip CPL and the metal plate MP 2 increase, resulting in the increase in the on resistance (resistance at conduction) of the power MOSFETs 1 and 2 . Since the elastic modulus of the bonding materials BD 4 and BD 6 is reduced in this embodiment, the occurrence of cracks in the bonding materials BD 4 and BD 6 can be suppressed, and it is thus possible to prevent such a problem.
  • the bonding materials BD 5 and BD 7 are the bonding materials for bonding the metal plates MP 1 and MP 2 to the lead coupling portions LB 2 and LB 4 . As described above, the amount of heat generated in the semiconductor chips CPH and CPL is large, and the semiconductor chips CPH and CPL can be heat sources.
  • the metal plates MP 1 and MP 2 are bonded to the pads PDHS 1 and PDLS 1 of the semiconductor chips CPH and CPL via the bonding materials BD 4 and BD 6 , the heat generated in the semiconductor chips CPH and CPL is transmitted to the metal plates MP 1 and MP 2 through the bonding materials BD 4 and BD 6 and is further transmitted to the lead coupling portions LB 2 and LB 4 through the bonding materials BD 5 and BD 7 .
  • the metal plates MP 1 and MP 2 and the lead coupling portions LB 2 and LB 4 are made of the same material (same metal material).
  • the metal plates MP 1 and MP 2 and the lead coupling portions LB 2 and LB 4 are preferably made of copper or copper alloy.
  • the thermal expansion coefficient of the metal plates MP 1 and MP 2 and the thermal expansion coefficient of the lead coupling portions LB 2 and LB 4 are substantially equal to each other. Accordingly, even when the heat generated in the semiconductor chips CPH and CPL is transmitted to the metal plates MP 1 and MP 2 and the lead coupling portions LB 2 and LB 4 and the temperatures of the metal plates MP 1 and MP 2 , the bonding materials BD 5 and BD 7 , and the lead coupling portions LB 2 and LB 4 increase, the stress generated in the bonding materials BD 5 and BD 7 interposed between the metal plates MP 1 and MP 2 and the lead coupling portions LB 4 and LB 4 does not increase so much.
  • the bonding material with the same elastic modulus is used for all of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 unlike this embodiment, the risk of the occurrence of cracks in the bonding materials BD 5 and BD 7 due to the heat generated in the semiconductor chips CPH and CPL is quite smaller than the risk of the occurrence of cracks in the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 due to the heat generated in the semiconductor chips CPH and CPL.
  • the bonding area (planar area of bonding material BD 5 ) between the metal plate MP 1 and the lead coupling portion LB 2 is smaller than the bonding area (planar area of bonding material BD 1 ) between the semiconductor chip CPH and the die pad DPH and the bonding area (planar area of bonding material BD 2 ) between the semiconductor chip CPL and the die pad DPL.
  • the bonding area (planar area of bonding material BD 5 ) between the metal plate MP 1 and the lead coupling portion LB 2 is smaller than the bonding area (planar area of bonding material BD 4 ) between the metal plate MP 1 and the pad PDHS 1 of the semiconductor chip CPH and the bonding area (planar area of bonding material BD 6 ) between the metal plate MP 2 and the pad PDLS 1 of the semiconductor chip CPL.
  • the bonding area (planar area of bonding material BD 7 ) between the metal plate MP 2 and the lead coupling portion LB 4 is smaller than the bonding area (planar area of bonding material BD 1 ) between the semiconductor chip CPH and the die pad DPH and the bonding area (planar area of bonding material BD 2 ) between the semiconductor chip CPL and the die pad DPL.
  • the bonding area (planar area of bonding material BD 7 ) between the metal plate MP 2 and the lead coupling portion LB 4 is smaller than the bonding area (planar area of bonding material BD 4 ) between the metal plate MP 1 and the pad PDHS 1 of the semiconductor chip CPH and the bonding area (planar area of bonding material BD 6 ) between the metal plate MP 2 and the pad PDLS 1 of the semiconductor chip CPL.
  • the planar size (planar area) of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is relatively large, the planar size (planar area) of each of the bonding materials BD 5 and BD 7 is relatively small when compared.
  • the electric resistivity (volume resistivity) of the bonding materials BD 5 and BD 7 with the small planar size (planar area) is low, the connection resistance between the metal plate MP 1 and the lead coupling portion LB 2 via the bonding material BD 5 and the connection resistance between the metal plate MP 2 and the lead coupling portion LB 4 via the bonding material BD 7 increase, and this is undesirable.
  • the bonding materials BD 5 and BD 7 with the planar size (planar area) smaller than those of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 , it is preferable to reduce the electric resistivity (volume resistivity) and thus to use the high-elastic bonding material.
  • the high-elastic bonding material has a high silver content and thus has low electric resistivity (volume resistivity)
  • the electric resistivity (volume resistivity) of the bonding materials BD 5 and BD 7 can be reduced by using the high-elastic bonding material for the bonding materials BD 5 and BD 7 .
  • the planar size (planar area) of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is relatively large, and thus the resistance (conduction resistance) of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 can be suppressed.
  • the low-elastic bonding material for the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 in order to reduce the risk of the occurrence of cracks in the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 due to the heat generated in the semiconductor chips CPH and CPL.
  • the high-elastic bonding material for the bonding materials BD 5 and BD 7 in order to suppress the connection resistance between the metal plate MP 1 and the lead coupling portion LB 2 via the bonding material BD 5 and the connection resistance between the metal plate MP 2 and the lead coupling portion LB 4 via the bonding material BD 7 .
  • the lead frame LF is sandwiched between the molding die KG 1 and the molding die KG 2 in the molding process (process of forming sealing portion MR), and the outer lead portion of each lead LD is sandwiched between the molding die KG 1 and the molding die KG 2 at this time.
  • the lead coupling portion LB 2 is integrally formed with the lead LD 2 and the lead coupling portion LB 4 is integrally formed with the lead LD 4 , and the outer lead portions of the leads LD 2 and LD 4 are also sandwiched between the molding die KG 1 and the molding die KG 2 (see FIG. 21 and FIG. 22 ).
  • the stress is generated in the bonding material BD 5 that bonds the lead coupling portion LB 2 and the metal plate MP 1 because the position of the lead LD 2 is slightly moved when the outer lead portion of the lead LD 2 is sandwiched between the molding die KG 1 and the molding die KG 2 .
  • the stress is generated in the bonding material BD 7 that bonds the lead coupling portion LB 4 and the metal plate MP 2 .
  • the molding die KG 1 and the molding die KG 2 are heated to a predetermined temperature, for example, 160 to 190° C., more preferably, about 170 to 180° C.
  • the heating temperature of the molding die KG 1 and the molding die KG 2 is higher than the temperature reached when the temperatures of the semiconductor chips CPH and CPL increase due to the heat generated in the semiconductor chips CPH and CPL during the operation of the semiconductor device PKG (reached temperature of semiconductor chips CPH and CPL). Therefore, when the lead frame LF is sandwiched between the molding die KG 1 and the molding die KG 2 , the stress is generated in the bonding materials BD 5 and BD 7 , and the bonding materials BD 5 and BD 7 are heated.
  • Both of the high-elastic bonding material and the low-elastic bonding material tend to soften and weaken in strength at high temperature, but the high-elastic bonding material has lower degree of reduction in strength at high temperature than the low-elastic bonding material, and thus the high-elastic bonding material has higher strength at high temperature than the low-elastic bonding material.
  • the high-elastic bonding material has a higher silver (Ag) content and a lower ratio of a resin component than the low-elastic bonding material, and the degree of reduction in strength at high temperature is smaller in the high-elastic bonding material having a low ratio of a resin component than in the low-elastic bonding material having a high ratio of a resin component.
  • the high-elastic bonding material as the bonding materials BD 5 and BD 7 , and it is thus possible to increase the strength of the bonding materials BD 5 and BD 7 at high temperature. Consequently, even if the stress is generated in the bonding material BD 5 that bonds the lead coupling portion LB 2 and the metal plate MP 1 and the bonding material BD 7 that bonds the lead coupling portion LB 4 and the metal plate MP 2 when the lead frame LF is sandwiched between the molding die KG 1 and the molding die KG 2 in the molding process, the occurrence of the problem (for example, breakage of bonding materials BD 5 and BD 7 ) due to the stress can be suppressed or prevented. Therefore, the manufacturing yield of the semiconductor device PKG can be improved, and the manufacturing cost of the semiconductor device PKG can be reduced. Also, the reliability of the semiconductor device PKG can be improved.
  • the stress generated in the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is relatively small in comparison with the stress generated in the bonding materials BD 5 and BD 7 when the lead frame LF is sandwiched between the molding die KG 1 and the molding die KG 2 in the molding process.
  • the stress generated by sandwiching the outer lead portions of the leads LD of the lead frame LF between the molding die KG 1 and the molding die KG 2 in the molding process is relatively small in the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 . Accordingly, it is not necessary to apply the high-elastic bonding material to the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 in consideration of the stress generated by sandwiching the outer lead portions of the leads LD of the lead frame LF between the molding die KG 1 and the molding die KG 2 in the molding process.
  • the temperatures of the die pads DPH, DPL, and DPC, the semiconductor chips CPH, CPL, and CPC, the metal plates MP 1 and MP 2 , and the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 increase.
  • the low-elastic bonding material is used for the bonding materials BD 1 , BD 2 , and BD 3 , it is possible to suppress the generation of the stress due to the difference in thermal expansion coefficient between the die pads DPH, DPL, and DPC and the semiconductor chips CPH, CPL, and CPC in the bonding materials BD 1 , BD 2 , and BD 3 in the molding process.
  • the low-elastic bonding material is used for the bonding materials BD 4 and BD 6 , it is possible to suppress the generation of the stress due to the difference in thermal expansion coefficient between the semiconductor chips CPH and CPL and the metal plates MP 1 and MP 2 in the bonding materials BD 4 and BD 6 in the molding process. Consequently, it is possible to suppress or prevent the occurrence of the problem (for example, breakage) in the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 in the molding process.
  • the lead coupling portion LB 2 is separated from the molding dies KG 1 and KG 2 and is in the floating state, the position thereof is not stable. Therefore, the stress generated by sandwiching the outer lead portions of the leads LD of the lead frame LF between the molding die KG 1 and the molding die KG 2 in the molding process is relatively large in the bonding materials BD 5 and BD 7 in comparison with the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 . Therefore, it is desirable to increase the strength at high temperature in the bonding materials BD 5 and BD 7 , and the high-elastic bonding material is preferably used to achieve it.
  • the metal plates MP 1 and MP 2 and the lead coupling portions LB 2 and LB 4 are made of the same material, the stress due to the difference in thermal expansion coefficient between the metal plates MP 1 and MP 2 and the lead coupling portions LB 2 and LB 4 is scarcely generated in the bonding materials BD 5 and BD 7 in the molding process.
  • the elastic modulus is properly set for the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 in the semiconductor device PKG.
  • the low-elastic bonding material is applied to the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 and the elastic modulus of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is low.
  • the high-elastic bonding material is applied to the bonding materials BD 5 and BD 7 and the elastic modulus of each of the bonding materials BD 5 and BD 7 is high.
  • the elastic modulus of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is made lower than that of each of the bonding materials BD 5 and BD 7 .
  • the elastic modulus of each of the bonding materials BD 5 and BD 7 is made higher than that of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 .
  • the same (common) bonding material is used for the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 .
  • the same (common) bonding material is used as the bonding materials BD 1 a , BD 2 a , BD 3 a , BD 4 a , and BD 6 a described above. Consequently, the manufacturing process of the semiconductor device PKG can be simply performed and the manufacturing cost of the semiconductor device can be reduced.
  • the elastic modulus of the bonding material BD 1 , the elastic modulus of the bonding material BD 2 , the elastic modulus of the bonding material BD 3 , the elastic modulus of the bonding material BD 4 , and the elastic modulus of the bonding material BD 6 are almost equal to one another.
  • the same (common) bonding material is used for the bonding materials BD 5 and BD 7 .
  • the same (common) bonding material is used as the bonding materials BD 5 a and BD 7 a described above. Consequently, the manufacturing process of the semiconductor device PKG can be simply performed and the manufacturing cost of the semiconductor device can be reduced. Note that, when the same bonding material is used for the bonding materials BD 5 and BD 7 , the elastic modulus of the bonding material BD 5 and the elastic modulus of the bonding material BD 7 are almost equal to each other.
  • the elastic modulus (elastic modulus at 25° C.) of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is about 1 to 3 GPa (gigapascal).
  • the elastic modulus (elastic modulus at 25° C.) of each of the bonding materials BD 5 and BD 7 is about 10 to 20 GPa. Consequently, the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 can be optimized, and the effect described above can be accurately obtained.
  • the main feature of this embodiment is to make the elastic modulus of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 lower than that of each of the bonding materials BD 5 and BD 7 , and this can be expressed in another way as follows.
  • the silver paste (silver paste bonding material) is used as the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 , and the silver (Ag) content of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 5 is made lower than the silver (Ag) content of each of the bonding materials BD 5 and BD 7 .
  • the silver (Ag) content of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is about 82 to 88 weight % (wt %). Also, it is more preferable that the silver (Ag) content of each of the bonding materials BD 5 and BD 7 is about 90 to 96 weight %. Consequently, the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 can be optimized, and the above-described effect can be obtained accurately.
  • the same (common) material is used for all of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 unlike this embodiment.
  • all of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 are formed to have a low elastic modulus or all of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 are formed to have a high elastic modulus.
  • the inventors of this application have studied about the problems that occur depending on the difference in elastic modulus for each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 , and as a result, the configuration in which the elastic modulus of each of the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6 is made lower than that of each of the bonding materials BD 5 and BD 7 like this embodiment is adopted.
  • the semiconductor chips CPH, CPL, and CPC are sealed and packaged together has been described in this embodiment.
  • the semiconductor chips CPH, CPL, and CPC may be separately sealed and packaged.
  • the cross-sectional structure of the semiconductor device (semiconductor package) including the semiconductor chip CPH is the same as that shown in FIG. 7 , and this semiconductor device includes the semiconductor chip CPH, the die pad DPH, the metal plate MP 1 , the plurality of leads LD (including the leads LD 1 , LD 2 , and LD 6 ), the lead coupling portions LB 1 and LB 2 , the bonding materials BD 1 , BD 4 , and BD 5 , and the sealing portion MR that seals them.
  • the pads PDHA, PDHC, PDHG, and PDHS 2 of the semiconductor chip CPH are electrically connected to the leads LD through the wires BW.
  • the elastic modulus of each of the bonding materials BD 1 and BD 4 is lower than that of the bonding material BD 5 in the semiconductor device including the semiconductor chip CPH, and from another viewpoint, the silver (Ag) content of each of the bonding materials BD 1 and BD 4 is lower than that of the bonding material BD 5 .
  • the semiconductor device including the semiconductor chip CPH does not include the semiconductor chips CPL and CPC, the die pads DPL and DPC, the metal plate MP 2 , the leads LD 3 , LD 4 , LD 5 a , LD 5 b , LD 7 , and LD 8 , the lead coupling portions LB 3 and LB 4 , and the bonding materials BD 2 , BD 3 , BD 6 , and BD 7 .
  • FIG. 32 is a table in which the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , BD 5 , BD 6 , and BD 7 in each of the first embodiment and the second embodiment are summarized.
  • the low-elastic bonding material is applied to the bonding materials BD 1 , BD 2 , BD 3 , BD 4 , and BD 6
  • the high-elastic bonding material is applied to the bonding materials BD 5 and BD 7 as described above.
  • the low-elastic bonding material is applied to the bonding materials BD 1 , BD 2 , and BD 3
  • the high-elastic bonding material is applied to the bonding materials BD 4 , BD 5 , BD 6 , and BD 7
  • the elastic modulus of each of the bonding materials BD 1 , BD 2 , and BD 3 is lower than that of each of the bonding materials BD 4 , BD 5 , BD 6 , and BD 7 .
  • the silver (Ag) content of each of the bonding materials BD 1 , BD 2 , and BD 3 is lower than that of each of the bonding materials BD 4 , BD 5 , BDE, and BD 7 . Since the second embodiment is substantially the same as the first embodiment other than that, the repetitive description thereof will be omitted here.
  • the low-elastic bonding material is applied to the bonding materials BD 1 , BD 2 , and BD 3 that bond the semiconductor chips CPH, CPL, and CPC to the die pads DPH, DPL, and DPC like the first embodiment described above.
  • the reason why the low-elastic bonding material is applied to the bonding materials BD 1 , BD 2 , and BD 3 in the second embodiment is the same as that in the first embodiment.
  • the stress (strain) to be generated in the bonding materials BD 1 and BD 2 due to the difference in thermal expansion coefficient between the die pads DPH and DPL and the semiconductor chips CPH and CPL when the semiconductor chips CPH and CPL generate heat can be suppressed by reducing the elastic modulus of the bonding materials BD 1 and BD 2 , and the occurrence of cracks in the bonding materials BD 1 and BD 2 can be suppressed like the first embodiment. Since the occurrence of cracks in the bonding materials BD 1 and BD 2 can be suppressed, the reliability of the semiconductor device PKG can be improved.
  • the low-elastic bonding material is preferably applied not only to the bonding materials BD 1 and BD 2 but also to the bonding material BD 3 like the first embodiment described above. Consequently, the bonding material BD 3 (BD 3 a ) can be formed of the same bonding material as that of the bonding materials BD 1 and BD 2 (BD 1 a , BD 2 a ), so that the manufacturing process of the semiconductor device PKG (more specifically, die bonding process) can be simplified and the manufacturing cost of the semiconductor device PKG can be reduced.
  • the bonding area (corresponding to the planar area of the bonding material BD 1 ) between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH is substantially the same as the area of the semiconductor chip CPH and is relatively large.
  • the bonding area (corresponding to the planar area of the bonding material BD 2 ) between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL is substantially the same as the area of the semiconductor chip CPL and is relatively large.
  • the large bonding area between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH functions to reduce the connection resistance between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH via the bonding material BD 1 .
  • the large bonding area between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL functions to reduce the connection resistance between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL via the bonding material BD 2 . Therefore, even when the low-elastic bonding material is used as the bonding material BD 1 , the connection resistance between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH via the bonding material BD 1 can be easily suppressed, and even when the low-elastic bonding material is used as the bonding material BD 2 , the connection resistance between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL via the bonding material BD 2 can be easily suppressed.
  • the bonding materials BD 4 and BD 6 are bonding materials for bonding the metal plates MP 1 and MP 2 to the pads PDHS 1 and PDLS 1 of the semiconductor chips CPH and CPL.
  • the bonding area (corresponding to the planar area of the bonding material BD 4 ) between the metal plate MP 1 and the pad PDHS 1 of the semiconductor chip CPH is smaller than the bonding area (corresponding to the planar area of the bonding material BD 1 ) between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH.
  • the bonding area (corresponding to the planar area of the bonding material BD 6 ) between the metal plate MP 2 and the pad PDLS 1 of the semiconductor chip CPL is smaller than the bonding area (corresponding to the planar area of the bonding material BD 2 ) between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL.
  • the planar size (planar area) of each of the bonding materials BD 4 and BD 6 is smaller than the planar size (planar area) of each of the bonding materials BD 1 and BD 2 .
  • connection resistance between the metal plate MP 1 and the pad PDHS 1 of the semiconductor chip CPH via the bonding material BD 4 tends to be larger than the connection resistance between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH via the bonding material BD 1 .
  • connection resistance between the metal plate MP 2 and the pad PDLS 1 of the semiconductor chip CPL via the bonding material BD 6 tends to be larger than the connection resistance between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL via the bonding material BD 2 .
  • the high-elastic bonding material is applied to the bonding materials BD 4 and BD 6 with an emphasis on the reduction of the connection resistance between the metal plate MP 1 and the pad PDHS 1 of the semiconductor chip CPH via the bonding material BD 4 and the connection resistance between the metal plate MP 2 and the pad PDLS 1 of the semiconductor chip CPL via the bonding material BD 6 .
  • the high-elastic bonding material has a high silver content and thus has low electric resistivity (volume resistivity), and the electric resistivity (volume resistivity) of the bonding materials BD 4 and BD 6 can be reduced by using the high-elastic bonding material as the bonding materials BD 4 and BD 6 .
  • connection resistance between the metal plate MP 1 and the pad PDHS 1 of the semiconductor chip CPH via the bonding material BD 4 and the connection resistance between the metal plate MP 2 and the pad PDLS 1 of the semiconductor chip CPL via the bonding material BD 6 can be suppressed.
  • the on resistance (resistance at conduction) of the semiconductor chip CPH (power MOSFET 1 ) and the on resistance (resistance at conduction) of the semiconductor chip CPL (power MOSFET 2 ) can be further reduced.
  • the high-elastic bonding material is applied to the bonding materials BD 5 and BD 7 like the first embodiment described above, and the reason for that is the seine as that of the first embodiment. Therefore, the repetitive description about the bonding materials BD 5 and BD 7 will be omitted here.
  • the first embodiment described above (bonding materials BD 1 , BD 2 , BD 4 , and BD 5 are low-elastic bonding materials) is advantageous.
  • the second embodiment (bonding materials BD 1 and BD 2 are low-elastic bonding materials and bonding materials BD 4 and BD 6 are high-elastic bonding materials) is advantageous.
  • the high-elastic bonding material is applied to the bonding materials BD 4 , BD 5 , BD 6 , and BD 7 for bonding the metal plates MP 1 and MP 2 , and thus the same (common) bonding material can be used for the bonding materials BD 4 , BD 5 , BD 6 , and BD 7 for bonding the metal plates MP 1 and MP 2 . Consequently, the manufacturing process of the semiconductor device PKG can be simply performed and the manufacturing cost of the semiconductor device can be reduced.
  • the elastic modulus of the bonding material BD 4 is almost equal to one another.

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CN112768414A (zh) 2021-05-07
JP2021068783A (ja) 2021-04-30
TW202129866A (zh) 2021-08-01
EP3813106A1 (en) 2021-04-28
JP7266508B2 (ja) 2023-04-28
US20210118781A1 (en) 2021-04-22

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