US10951008B2 - Creating arbitrary patterns on a 2-d uniform grid VCSEL array - Google Patents
Creating arbitrary patterns on a 2-d uniform grid VCSEL array Download PDFInfo
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- US10951008B2 US10951008B2 US16/867,594 US202016867594A US10951008B2 US 10951008 B2 US10951008 B2 US 10951008B2 US 202016867594 A US202016867594 A US 202016867594A US 10951008 B2 US10951008 B2 US 10951008B2
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- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
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- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
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- H01S5/00—Semiconductor lasers
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- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2054—Methods of obtaining the confinement
- H01S5/2059—Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion
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Definitions
- the present invention relates generally to optoelectronic devices, and particularly to devices configurable to emit patterned illumination.
- 3D imagers enable the remote measurement of distance (and often intensity) of each point on a target scene—so-called target scene depth—by illuminating the target scene with one or more optical beams and analyzing the reflected optical signal.
- an optoelectronic device comprises a semiconductor die on which a monolithic array of vertical-cavity surface-emitting laser (VCSEL) diodes is formed in a two-dimensional pattern that is not a regular lattice.
- VCSEL vertical-cavity surface-emitting laser
- regular lattice means a two-dimensional pattern in which the spacing between adjacent elements in the pattern (for example, between adjacent emitters in a VCSEL array) is constant and is synonymous with a periodic lattice.
- the pattern can be uncorrelated, in the sense that the auto-correlation of the positions of the laser diodes as a function of transverse shift is insignificant for any shift larger than the diode size. Random, pseudo-random, and quasi-periodic patterns are examples of such uncorrelated patterns.
- Embodiments of the present invention that are described hereinbelow provide improved methods for fabricating patterned light sources and light sources that can be produced by such methods.
- an optoelectronic device including a semiconductor substrate and an array of optoelectronic cells, which are formed on the semiconductor substrate.
- the cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell.
- DBR distributed Bragg-reflector
- the array includes a first set of the optoelectronic cells that are configured to emit laser radiation in response to the excitation current and a second set of the optoelectronic cells, interleaved with the first set, in which at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
- the array is a regular array, while the first set of the optoelectronic cells are arranged in an uncorrelated pattern within the array.
- the second set of the optoelectronic cells include implanted ions in the upper DBR stack, which increase an electrical resistance of the upper DBR stack by an amount sufficient to reduce the excitation current injected into the quantum well structure to below a threshold required for emitting laser radiation.
- the electrodes of the second set of the optoelectronic cells are configured so as not to inject the excitation current into the quantum well structure.
- the optoelectronic cells include an isolation layer between the epitaxial layers and the electrodes, and a part of the isolation layer is etched away in the first set of the optoelectronic cells and is not etched in the second set of the optoelectronic cells, so that the excitation current is not injected into the quantum well structure of the second set of the optoelectronic cells.
- the device includes conductors configured to feed electrical current to the optoelectronic cells, and an isolation layer, which isolates the electrodes of the second set of the optoelectronic cells from the conductors, so that the electrical current is not fed to the electrodes of the second set of the optoelectronic cells.
- the device includes an isolation layer formed between the lower and upper DBR stacks, wherein the isolation layer is etched out of an area of the quantum well structure in the first set of the optoelectronic cells and is not etched out of the second set of the optoelectronic cells.
- a method for manufacturing an optoelectronic device includes depositing first epitaxial layers on a semiconductor substrate to define a lower distributed Bragg-reflector (DBR) stack. Second epitaxial layers are deposited over the first epitaxial layers to define a quantum well structure. Third epitaxial layers are deposited over the second epitaxial layers to define an upper DBR stack. The epitaxial layers are etched to define an array of optoelectronic cells.
- DBR distributed Bragg-reflector
- Electrodes are deposited over the third epitaxial layers electrodes and are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell so as to cause a first set of the optoelectronic cells to emit laser radiation in response to the excitation current.
- At least one element, selected from among the epitaxial layers and the electrodes, of a second set the optoelectronic cells, which is interleaved with the first set, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.
- FIG. 1 is a schematic top view of an optoelectronic device comprising a semiconductor die on which a monolithic array of VCSELs has been formed in a two-dimensional pattern, in accordance with an embodiment of the present invention
- FIGS. 2 a - b are schematic sectional views of an enabled VCSEL and a disabled VCSEL, in accordance with an embodiment of the present invention
- FIGS. 3 a - b are schematic sectional views of an enabled VCSEL and a disabled VCSEL, in accordance with another embodiment of the present invention.
- FIGS. 4 a - b are schematic sectional views of areas of enabled and disabled VCSELs, in accordance with yet another embodiment of the present invention.
- FIGS. 5 a - b are schematic sectional views of areas of enabled and disabled VCSELs, in accordance with a further embodiment of the present invention.
- FIGS. 6 a - b are schematic sectional views of areas of enabled and disabled VCSELs, in accordance with still another embodiment of the present invention.
- FIGS. 7 a - b are schematic sectional views of an enabled VCSEL and a disabled VCSEL, in accordance with an alternative embodiment of the present invention.
- Light sources emitting multiple beams are used, inter alia, in 3-D (three-dimensional) mapping applications based on optical triangulation.
- a light source that projects a random or pseudo-random pattern on the target to be mapped.
- a desirable emitter for such a light source is a VCSEL (vertical-cavity surface-emitting laser) array, due to low power consumption, high reliability, and good beam quality.
- a random or pseudo-random pattern of emitters in a VCSEL array can be generated by a corresponding photolithographic mask. The non-periodic distribution of the emitters, however, may lead to reduced control over the photoresist pattern CD (critical dimensions), as well as poor etch uniformity due to uneven etch load effects.
- the embodiments of the present invention address the above limitations by fabricating a VCSEL array on a uniform grid, and disabling individual emitters.
- the disabled emitters can be interleaved with the enabled (operating) emitters in substantially any desired pattern, for example in a pseudo-random or otherwise uncorrelated pattern.
- the disclosed embodiments selectively disable emitters using modifications in the VCSEL fabrication process, for example by modifying the epitaxial layers or the electrodes of the VCSELs. As the design is based on a uniform grid, it can be manufactured reliably using standard photolithographic methods.
- FIG. 1 is a schematic top view of an optoelectronic device comprising a semiconductor die 10 on which a monolithic array of enabled optoelectronic cells 12 , such as VCSELs, has been formed in an uncorrelated two-dimensional pattern, in accordance with an embodiment of the present invention.
- the array is formed on the semiconductor substrate by the same sort of photolithographic methods as are used to produce VCSEL arrays that are known in the art, with suitable thin film layer structures forming the VCSELs, and conductors providing electric power and ground connections from contact pads 14 to VCSELs 12 in the array.
- the sort of uncorrelated pattern of enabled VCSELs 12 is produced using substantially the same processes as are used in fabricating a regular array (i.e., an array in the form of a regular lattice) of VCSEL-like cells. In contrast to a conventional regular array, however, only VCSELs 12 are selectively enabled, while disabling the remaining VCSEL-like cells. These disabled cells are referred to herein as “dummy cells 16 ,” since they are nearly identical in structure to VCSELs 12 but are incapable of laser emission due to thin film layer properties that are configured in the manufacturing process. In the following, the terms “disabling” and “disabled” are used synonymously with “not enabling” and “not enabled”, respectively.
- FIGS. 2-7 are schematic sectional views of enabled and disabled VCSELs. Each figure compares an enabled VCSEL (that can be used as the basis for enabled VCSELs 12 ), in a figure labeled by “a”, to a disabled VCSEL (as a possible basis for dummy cells 16 ), in a figure labeled by “b”. As the enabled and disabled VCSELs share most of the same elements, a detailed description of an enabled VCSEL is given with reference to FIG. 2 a , below.
- FIGS. 2 a - b are schematic sectional views of an enabled VCSEL 17 and a disabled VCSEL 18 , in accordance with an embodiment of the present invention.
- Enabled VCSEL 17 in FIG. 2 a is formed on a semiconductor substrate 19 .
- Epitaxial semiconductor layers of a VCSEL (a lower n-type distributed Bragg-reflector [n-DBR]stack 20 , a quantum well structure 22 , and an upper p-DBR stack 24 ) are deposited over an area of semiconductor substrate 19 .
- a confinement layer 36 typically Al-oxide, is formed and patterned.
- an isolation layer 28 is deposited and patterned, and one or more p-electrodes 30 and n-electrodes 32 are deposited and patterned.
- Isolation trenches 34 are etched to define the array of VCSELs and to isolate neighboring VCSELs. Additionally, an isolation implant 38 , such as a proton implant, may be deposited adjacent to p-DBR stack 24 and quantum well structure 22 for increased isolation between neighboring VCSELs.
- an isolation implant 38 such as a proton implant
- Disabled VCSEL 18 in FIG. 2 b differs from enabled VCSEL 17 in that in the disabled VCSEL, isolation implant 38 extends into p-DBR stack 24 and possibly into quantum well structure 22 . Due to the lattice damage caused by the ion implantation, the resistance of the implanted layers increases from the non-implanted state, lowering the excitation current injected into quantum well structure 22 to below the threshold required for emitting laser radiation. As a result, the VCSEL is disabled and will not emit laser radiation.
- Disabling of VCSEL 18 is achieved in the fabrication process by a modification of the photomask responsible for defining the lateral distribution of the deposition of isolation implant 38 so as to permit implantation ions to reach p-DBR stack 24 and possibly quantum well structure 22 .
- FIGS. 3 a - b are schematic sectional views of an enabled VCSEL 39 and a disabled VCSEL 40 , in accordance with another embodiment of the present invention.
- Enabled VCSEL 39 is substantially similar to enabled VCSEL 17 of FIG. 2 a , except that the present embodiment does not necessarily comprise isolation implant 38 for isolating neighboring VCSELs.
- Disabling VCSEL 40 is accomplished by preventing the injection of excitation current into p-DBR stack 24 and quantum well structure 22 .
- FIGS. 4-6 show the differences between enabled VCSEL 39 and disabled VCSEL 40 in three alternative embodiments of the present invention. These figures refer to FIGS. 3 a - b , and show an area 44 (marked by a dotted line) for enabled VCSEL 39 and an area 46 (marked by a dotted line) for disabled VCSEL 40 .
- FIGS. 4 a - b are schematic sectional views of areas 44 and 46 of enabled and disabled VCSELs 39 and 40 of FIGS. 3 a - b , respectively, in accordance with an embodiment of the present invention.
- an electrical contact between p-electrode 30 and p-DBR stack 24 is produced by etching a via in a location 41 in isolation layer 28 prior to deposition of the metal layer (M 1 ) that serves as the p-electrode, thus enabling the flow of excitation current from the p-electrode to the p-DBR stack and further to quantum well structure 22 .
- no via is etched, as is shown by contiguous isolation layer 28 in a location 42 , thus preventing the flow of excitation current from p-electrode 30 into p-DBR stack 24 and further to quantum well structure 22 .
- Disabling of VCSEL 40 is achieved in the fabrication process by a modification of the photomask responsible for delineating the etch of isolation layer 28 so as not to etch a via in location 42 .
- FIGS. 5 a - b are schematic sectional views of areas 44 and 46 of enabled and disabled VCSELs 39 and 40 of FIGS. 3 a - b , respectively, in accordance with another embodiment of the present invention.
- a via is etched in isolation layer 28 in locations 62 and 64 , respectively.
- a second isolation layer 60 is deposited over isolation layer 28 , and a via is etched in enabled VCSEL 39 in location 62 , whereas no via is etched in disabled VCSEL 40 in location 64 .
- p-electrode 30 is deposited over second isolation layer 60 , and the via etched in location 62 enables electrical contact between the p-electrode and p-DBR stack 24 , thus enabling the flow of excitation current from the p-electrode to the p-DBR stack and further to quantum well structure 22 .
- Disabling of VCSEL 40 is achieved in the fabrication process by a modification of the photomask responsible for delineating the etch of isolation layer 60 so as to prevent the etching of a via in location 64 .
- FIGS. 6 a - b are schematic sectional views of areas 44 and 46 of enabled and disabled VCSELs 39 and 40 of FIGS. 3 a - b , respectively, in accordance with yet another embodiment of the present invention.
- an electrical contact between p-electrode 30 and p-DBR stack is generated by etching a via in a location 41 in isolation layer 28 , similarly to enabled VCSEL of FIG. 4 a .
- a second isolation layer 66 is deposited over p-electrode (as opposed to depositing over isolation layer 28 , as in FIGS. 5 a - b ).
- a via is etched in second isolation layer 66 in a location 72 , but no via is etched in a location 74 .
- a conducting layer 76 is deposited on second isolation layer 66 for feeding electrical current to the array of optoelectronic cells.
- conducting layer 76 is in electrical contact with p-electrode 30 , and thereby with p-DBR stack 24 , enabling the flow of excitation current from the second metal layer to the p-DBR stack and further to quantum well structure 22 .
- contiguous second isolation layer 66 in location 74 p-electrode 30 of disabled VCSEL 40 is isolated from conducting layer 76 , thus preventing feeding of electrical current to the p-electrode.
- Disabling of VCSEL 40 is achieved in the fabrication process by a modification of the photomask responsible for delineating the etch of isolation layer 60 so as to prevent the etching of a via in location 74 .
- FIGS. 7 a - b are schematic sectional views of an enabled VCSEL 80 and a disabled VCSEL 82 , in accordance with an embodiment of the present invention.
- Enabled VCSEL 80 is substantially similar to enabled VCSEL 39 of FIG. 3 a .
- Disabled VCSEL 82 differs from enabled VCSEL 80 in that confinement layer 36 is not etched in location 84 , preventing the growth of quantum well structure 22 .
- Disabling of VCSEL 80 is achieved in the fabrication process by a modification of the photomask so as to prevent the etch of confinement layer 36 in location 84 .
Abstract
Description
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- an improved dry etch uniformity is achieved by minimizing so-called etch loading effects;
- a tighter control of photoresist CD is achieved due to the periodical structure of the uniform grid; and
- a more uniform temperature distribution of
die 10 can be achieved, leading to a better optical power uniformity, by filling the trenches between cells with a resin, such as polyimide.
Claims (16)
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CN Application # 201810914530.5 office action dated Jun. 1, 2020. |
CN Application # 201811355978 Office Action dated Dec. 3, 2020. |
CN Application # 201811355978A Office Action dated Apr. 27, 2020. |
KR Application # 10-2020-0046213 Office Action dated Jul. 7, 2020. |
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TWI683348B (en) | 2020-01-21 |
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JP6931419B2 (en) | 2021-09-01 |
KR102288103B1 (en) | 2021-08-12 |
TW201913741A (en) | 2019-04-01 |
TWI720744B (en) | 2021-03-01 |
JP7210663B2 (en) | 2023-01-23 |
CN109428261A (en) | 2019-03-05 |
KR102351103B1 (en) | 2022-01-14 |
EP3656028A1 (en) | 2020-05-27 |
CN109428261B (en) | 2021-01-01 |
JP2020532131A (en) | 2020-11-05 |
EP3656028B1 (en) | 2022-05-04 |
KR20200030100A (en) | 2020-03-19 |
EP4047762A1 (en) | 2022-08-24 |
US20190089128A1 (en) | 2019-03-21 |
TW202015105A (en) | 2020-04-16 |
JP2021182640A (en) | 2021-11-25 |
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