DE202018004017U1 - Generating arbitrary patterns on a uniform 2-D grid VCSEL array - Google Patents

Abstract

An optoelectronic device comprising: a semiconductor substrate; andan array of optoelectronic cells formed on the semiconductor substrate and comprising: first epitaxial layers defining a bottom distributed Bragg reflector (DBR) stack; second epitaxial layers formed over the bottom DBR stack defining a quantum well structure third epitaxial layers formed over the quantum well structure defining an upper DBR stack; andelectrodes formed over the top DBR stack configurable to inject an excitation current into the quantum well structure of each optoelectronic cell, the array comprising a first set of the optoelectronic cells configured to, in response to the excitation current To emit laser radiation, and a second set of the optoelectronic cells interleaved with the first set, in which at least one element of the optoelectronic cells selected among the epitaxial layers and the electrodes is configured such that the optoelectronic cells in the second set do not emit the laser radiation.

Description

Cross-reference to a related application

This application claims the benefit of US Provisional Patent Application 62 / 552,406 filed on Aug. 31, 2017, the disclosure of which is incorporated herein by reference.

Field of the invention

The present invention relates generally to optoelectronic devices, and more particularly to devices that are configurable to emit patterned illumination.

background

Existing and emerging consumer applications have created an increasing need for real-time three-dimensional (3D) imagers. These imaging devices, also commonly known as depth sensors or depth images, allow remote measurement of a distance (and often intensity) from any point of a target scene - so-called target scene depth - by illuminating the target scene with one or more optical beams and analyzing the reflected ones optical signals.

Various methods for generating light sources based on arrays of multiple light emitting elements of optical radiation on a monolithic semiconductor substrate are known in the art.

The United States Patent Application Publication 2014/0211215 , the disclosure of which is incorporated herein by reference, describes an optical device including a beam source configured to generate an optical beam having a pattern imposed thereon. In one embodiment, an optoelectronic device includes a semiconductor die on which a monolithic array of Vertical Cavity Surface Emitting Laser (VCSEL) diodes is formed in a two-dimensional pattern that is not a regular grid. The term "regular grid" means a two-dimensional pattern in which the spacing between adjacent elements in the pattern (eg, between adjacent emitters in a VCSEL array) is constant, and is synonymous with a periodic grid. The pattern may be uncorrelated, in the sense that the autocorrelation of the positions of the laser diodes is insignificant as a function of a transverse displacement for any displacement greater than the diode size. Random, pseudorandom and quasi-periodic patterns are examples of such uncorrelated patterns.

Summary

Embodiments of the present invention, which are described below, provide improved apparatus for fabricating patterned light sources and light sources that can be produced by such apparatus.

Therefore, there is provided for this purpose an optoelectronic device in accordance with an embodiment of the invention including a semiconductor substrate and an array of optoelectronic cells formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack defining a quantum well structure; third epitaxial layers formed over the quantumwall structures forming an upper DBR stack; and electrodes formed over the upper DBR stack that are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell.

The arrangement includes a first set of optoelectronic cells configured to emit laser radiation in response to the excitation current and a second set of optoelectronic cells interleaved with the first set, in which at least one of the optoelectronic cell elements, selected among the epitaxial layers and the electrodes is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

In a disclosed embodiment, the array is a regular array while the first set of opto-electronic cells are arranged in an uncorrelated pattern within the array.

In one embodiment, the second set of optoelectronic cells includes implanted ions in the upper DBR stack that increase an electrical resistance of the upper DBR stack by a sufficient amount to reduce the excitation current injected into the quantum well structure below a threshold, which is required for emitting laser radiation.

In other embodiments, the electrodes of the second set of optoelectronic cells are configured so as not to inject the excitation current into the quantum well structure. In such an embodiment, the optoelectronic cells include an insulating layer between the epitaxial layers and the electrodes, and a portion of the Insulation layer is etched in the first set of optoelectronic cells and is not etched in the second set of optoelectronic cells, so that the excitation current is not injected into the quantum well structure of the second set of optoelectronic cells. In another embodiment, the device includes conductors configured to supply current to the optoelectronic cells and an isolation layer that isolates the electrodes of the second set of optoelectronic cells from the conductors such that the electrical current does not reach the electrodes of the optoelectronic cells second set of optoelectronic cells is fed.

Additionally or alternatively, the device includes an insulating layer formed between the lower and upper DBR stacks, wherein the insulating layer is etched out of a portion of the quantumwall structure in the first set of optoelectronic cells and is not etched out of the second set of optoelectronic cells.

In accordance with one embodiment of the invention, an apparatus for manufacturing an optoelectronic device is also provided. The apparatus for manufacturing an optoelectronic device is configured to deposit first epitaxial layers on a semiconductor substrate to define a bottom distributed Bragg reflector (DBR) stack. Second epitaxial layers are deposited over the first epitaxial layers to define a quantum well structure. Third epitaxial layers are deposited over the second epitaxial layers to define an upper DBR stack. The epitaxial layers are etched to define an array of optoelectronic cells. Electrodes are deposited over the third epitaxial layers and are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell such that a first set of optoelectronic cells are caused to emit laser radiation in response to the excitation current. At least one element selected among the epitaxial layers and the electrodes of the second set of optoelectronic cells interleaved with the first set is configured such that the optoelectronic cells in the second set do not emit the laser radiation.

The present invention will be better understood by the following detailed description of embodiments thereof taken in conjunction with the drawings, in which:

list of figures

• 1 FIG. 12 is a schematic plan view of an optoelectronic device including a semiconductor chip on which a monolithic array of VCSELs has been formed in a two-dimensional pattern, in accordance with an embodiment of the present invention; FIG.
• 2a to b are schematic cross-sectional views of an activated VCSEL and a deactivated VCSEL in accordance with an embodiment of the present invention;
• 3a to b are schematic cross-sectional views of an activated VCSEL and a deactivated VCSEL in accordance with an embodiment of the present invention;
• 4a to b are schematic cross-sectional views of portions of activated and deactivated VCSELs in accordance with still another embodiment of the present invention;
• 5a to b are schematic cross-sectional views of portions of activated and deactivated VCSELs in accordance with another embodiment of the present invention;
• 6a to b are schematic cross-sectional views of portions of activated and deactivated VCSELs in accordance with still another embodiment of the present invention; and
• 7a to b are schematic cross-sectional views of an activated VCSEL and a deactivated VCSEL in accordance with an alternative embodiment of the present invention.

Detailed description of embodiments

Overview

Light sources that emit multiple beams are used inter alia in 3D (three-dimensional) imaging applications based on optical triangulation. As in the above US Patent Application Publication 2014/0211215 It is advantageous to use a light source that projects a random or pseudo-random pattern onto a target that is to be imaged. A desirable emitter for such a light source is a Vertical Cavity Surface Emitting Laser (VCSEL) array because of low power consumption, high reliability, and good beam quality. A random or a Pseudo-random patterns of emitters in a VCSEL array can be generated by a corresponding photolithographic mask. However, the non-periodic distribution of the emitters can result in reduced control over the critical dimensions (CD) of the photoresist pattern as well as poor etch uniformity due to unequal etch loading effects.

The embodiments of the present invention described herein address the above limitations by establishing a VCSEL array on a uniform grid and by deactivating individual emitters. The deactivated emitters may be nested with the activated (powered) emitters in substantially any desired pattern, e.g. in a pseudo-random pattern or otherwise uncorrelated pattern. The disclosed embodiments selectively deactivate emitters using modifications in the VCSEL fabrication process, e.g. by modifying the epitaxial layers or the electrodes of the VCSELs. Since the design is based on a uniform grid, it can be reliably manufactured using standard photolithography techniques.

Description of the system

1 FIG. 12 is a schematic plan view of an opto-electronic device including a semiconductor chip. FIG 10 includes on which a monolithic array of activated optoelectronic cells 12 , such as VCSELs, has been formed in an uncorrelated two-dimensional pattern in accordance with an embodiment of the present invention. The array is formed on the semiconductor substrate by the same type of photolithographic techniques used in the prior art to produce VCSEL arrays, with suitable thin film layer structures forming the VCSELs, and conductors comprising electrical current and ground connections of contact surfaces 14 to VCSELs 12 in the arrangement.

The type of uncorrelated patterns of activated VCSELs 12 is produced using substantially the same processes as are produced to produce a uniform array (ie, a uniform grid array) of VCSEL-like cells. Unlike conventional uniform arrangements, VCSELs 12 however, optionally activated while deactivating the remaining VCSEL-like cells. These deactivated cells are referred to herein as "dummy cells 16" because they are nearly identical in structure to the VCSELs 12 but are incapable of laser emission due to thin film layer properties configured in the manufacturing process. In the following, the terms "deactivate" or "deactivated" are used synonymously with "not activated" or "not activated".

• • Eine verbesserte Trockenätzgleichförmigkeit wird durch ein Minimieren von sogenannten Ätzladungseffekten erreicht;
• • eine genauere Kontrolle der Photoresistenz-CD wird aufgrund der periodischen Struktur des gleichförmigen Gitters erreicht; und
• • eine gleichförmigere Temperaturverteilung des Chips 10 kann erreicht werden, was zu einer besseren optischen Leistungsgleichförmigkeit führt, indem die Gräben zwischen Zellen mit einem Kunstharz, wie beispielsweise Polyimid gefüllt werden.

The ability to create an array of powered emitters in substantially any desired pattern, eg, in a pseudorandom or otherwise uncorrelated pattern based on a regular array of cells, has several advantages:

• Improved dry etch uniformity is achieved by minimizing so-called etch charge effects;
• • closer control of the photoresist CD is achieved due to the periodic structure of the uniform grating; and
• • a more uniform temperature distribution of the chip 10 can be achieved, resulting in better optical performance uniformity by filling the trenches between cells with a synthetic resin such as polyimide.

The 2 to 7 FIG. 12 are schematic cross-sectional views of activated and deactivated VCSELs. FIG. Each figure compares an activated VCSEL (which serves as the basis for activated VCSELs 12 can be used) in a figure marked "a" with a disabled VCSEL (ie, a possible basis for dummy cells) in a figure marked by "b". Since the activated and deactivated VCSELs share most of the elements, a detailed description of an activated VCSEL will be referred to 2a provided below. 2a to b are schematic cross-sectional views of an activated VCSEL 17 and a disabled VCSEL 18 in accordance with an embodiment of the present invention.

The activated VCSEL 17 in the 2a is on a semiconductor substrate 19 educated. The epitaxial semiconductor layers of a VCSEL (lower n-type distributed Bragg reflector [n-DBR] stack 20, a quantum well structure 22 and a top p-DBR stack 24) are over a region of the semiconductor substrate 19 deposited. Between the n-DBR stack 20 and the p-DBR stack 24 is a refinement layer 36 , typically alumina, formed and patterned. After depositing the p-DBR stack 24, an insulating layer is formed 28 deposited and patterned, and one or more p-type electrodes 30 and n-type electrodes 32 are deposited and patterned. The isolation trenches 34 are etched to define the array of VCSELs to isolate adjacent VCSELs. In addition, an isolation implant 38 , such as a proton implant, adjacent to the p-DBR stack 24 and the quantum wall structure 22 deposited for increased isolation between adjacent VCSELs.

The disabled VCSEL 18 in the 2 B is different from the activated VCSEL 17 in that an isolation implant 38 into the p-DBR stack 24 and possibly into the quantumwall structure 22 extends. Due to the lattice damage caused by the ion implantation, the resistance of the implanted layers to the non-implanted state increases, thereby increasing the excitation current into the quantum well structure 22 is reduced below the threshold required to emit laser radiation. As a result, the VCSEL is deactivated and it will not emit laser radiation. Disabling the VCSEL 18 is achieved in the manufacturing process by a modification of the photomask used to define the lateral distribution of the deposition of the isolation implant 38 is responsible for allowing implantation ions, the p-DBR stack 24, and possibly the quantum well structure 22 to reach.

The 3a to b are schematic cross-sectional views of an activated VCSEL 39 and a disabled VCSEL 40 in accordance with another embodiment of the present invention. The activated VCSEL 39 is essentially similar to the activated VCSEL 17 from 2a except that the present embodiment is not necessarily an isolation implant 38 for isolating adjacent VCSELs. Disabling the VCSEL 40 is achieved by injecting an excitation current into the p-DBR stack 40 and the quantum well structure 22 is prevented. The differences between the activated VCSEL 39 and the disabled VCSEL 40 in three alternative embodiments of the present invention are in the 4 to 6 shown. These figures relate to the 3a to b and show an area 44 (marked by a dotted line) for the activated VCSEL 39 and an area 46 (marked by a dotted line) for the deactivated VCSEL 40 ,

The 4a to b are schematic cross-sectional views of areas 44 and 46 of the activated and deactivated VCSELs 39 and 40 of the 3a to b in accordance with an embodiment of the present invention.

In the activated VCSEL 39 becomes an electrical contact between the P electrode 30 and the p-DBR stack 24 is produced by a via in one place 41 in the insulation layer 28 before the deposition of the metal layer (M1) serving as the p-electrode, whereby the flow of excitation current from the p-electrode to the p-DBR stack and further to the quantum well structure 22 is possible. In the disabled VCSEL 40 no via is etched as it is by the continuous insulation layer 28 in one place 42 whereby the flow of excitation current from the p-electrode 30 into the p-DBR stack 24 and further to the quantum well structure 22 is prevented.

Disabling the VCSEL 40 is achieved in the manufacturing process by a modification of the photomask used for the representation of the etching of the insulating layer 28 is responsible to the place 42 no via-etching.

The 5a to b are schematic cross-sectional views of the regions 44 and 46 the activated and deactivated VCSELs 39 and 40 of the 3a to 3b in accordance with another embodiment of the present invention.

In both the activated VCSEL 39 as well as the disabled VCSEL 40 is a via in the insulation layer 28 in the places 62 respectively. 64 etched. A second insulation layer 60 is above the insulation layer 28 deposited and in the place 62 is a via in the activated VCSEL 39 etched, whereas in the place 64 no via in the disabled VCSEL 40 etched. The p-electrode 30 is over the second insulating layer 60 deposited and the Via, the place 62 is etched, allows electrical contact between the p-electrode and the p-DBR stack 24, whereby the flow of excitation current from the p-electrode to the p-DBR stack and further to the quantum well structure 22 is possible. Between the p-electrode 30 and the p-DBR stack 24 of the deactivated VCSEL 40 however, no electrical contact is established due to the contiguous second insulation layer 60 locally 64 whereby the flow of excitation current from the p-electrode into the p-DBR stack and further to the quantum well structure 22 is prevented.

A deactivation of the VCSEL 40 is achieved in the manufacturing process by a modification of the photomask, which is for a representation of the etching of the insulating layer 60 is responsible for etching a via in place 64 to prevent.

The 6a to b are schematic cross-sectional views of the regions 44 and 46 the activated and deactivated VCSEL 39 and 40 of the 3a to 3b in accordance with yet another embodiment of the present invention.

In both the activated VCSEL 39 as well as the disabled VCSEL 40 is an electrical contact between the p-electrode 30 and the p-DBR stack 24 by etching a via in place 41 in the insulation layer 28 generated, similar to the activated VCSEL of 4a , A second insulation layer 66 is deposited over the p-electrode 30 (in FIG Contrary to deposition over the insulation layer 28 as in the 5a till B). A via is in one place 72 in the second insulation layer 66 etched, but in one place 74 no via is etched. A conductive layer 76 is on a second insulation layer 66 deposited to feed an electric current to the array of optoelectronic cells. Due to the Via, the local 72 etched is the conductive layer 76 with the pp electrode 30 in electrical contact and thereby with the p-DBR stack 24, whereby the flow of excitation current from the second metal layer to the p-DBR stack and further to the quantum well structure 22 is possible. Due to the coherent second insulation layer 66 locally 74 is the p-electrode 30 of the disabled VCSEL 40 however, from the conductive layer 76 isolated, thereby preventing a supply of electric current to the p-electrode.

Disabling the VCSEL 40 is achieved in the manufacturing process by a modification of the photomask used for representing the etching of the insulating layer 60 is responsible for etching a via in place 74 to prevent.

The 7a to b are schematic cross-sectional views of an activated VCSEL 80 and a disabled VCSEL 82 in accordance with an embodiment of the present invention. The activated VCSEL 80 is substantially similar to the activated VCSEL 39 of the 3a , The disabled VCSEL 82 differs from the activated VCSEL 80 in that the refinement layer 36 locally 84 not etched, causing the growth of a quantum wall structure 22 is prevented.

Disabling the VCSEL 80 is achieved in the manufacturing process by a modification of the photomask to the etching of a refining layer 36 locally 84 to prevent.

It will be understood that the embodiments described above are given by way of example and that the present invention is not limited to what has been particularly shown and described above. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described above, as well as variations and modifications thereof, which will become apparent to those skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 62552406 [0001]
• US 2014/0211215 [0005, 0015]

Claims (14)

Optoelectronic device comprising: a semiconductor substrate; and an arrangement of optoelectronic cells formed on the semiconductor substrate and comprising: first epitaxial layers defining a lower distributed Bragg reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack defining a quantum well structure; third epitaxial layers formed over the quantum well structure defining an upper DBR stack; and Electrodes formed over the top DBR stack configurable to inject an excitation current into the quantum well structure of each optoelectronic cell, wherein the array comprises a first set of the optoelectronic cells configured to emit laser radiation in response to the excitation current, and a second set of the optoelectronic cells interleaved with the first set, in which at least one element of the optoelectronic Cells selected among the epitaxial layers and the electrodes are configured such that the optoelectronic cells in the second set do not emit the laser radiation. Optoelectronic device according to Claim 1 wherein the array is a uniform array while the first set of opto-electronic cells are arranged in an uncorrelated pattern within the array. Optoelectronic device according to Claim 1 wherein the second set of optoelectronic cells comprises implanted ions in the upper DBR stack which increase an electrical resistance of the upper DBR stack by a sufficient amount to reduce the excitation current injected into the quantum well structure below a threshold, which is required for emitting laser radiation. Optoelectronic device according to Claim 1 wherein the electrodes of the second set of the optoelectronic cells are configured so as not to inject the excitation current into the quantum well structure. Optoelectronic device according to Claim 4 wherein the optoelectronic cells comprise an insulating layer between the epitaxial layers and the electrodes and wherein a portion of the insulating layer is etched away in the first set of optoelectronic cells and not etched in the second set of the optoelectronic cells such that the excitation current does not enter the quantum well structure of the optoelectronic cell second set of optoelectronic cells is injected. Optoelectronic device according to Claim 4 and a conductor configured to supply an electric current to the optoelectronic cells, and an insulating layer isolating the electrodes of the second set of the optoelectronic cells from the conductors so that the electric current is not supplied to the electrodes of the second set of electrodes optoelectronic cells is fed. Optoelectronic device according to Claim 1 and an insulating layer formed between the upper and lower DBR stacks, wherein the insulating layer is etched out of a portion of the quantum well structure in the first set of optoelectronic cells and is not etched out of the second set of optoelectronic cells. Device for producing an optoelectronic device, wherein the device for producing the optoelectronic device is configured to: Depositing first epitaxial layers on a semiconductor substrate to define a bottom, distributed Bragg reflector (DBR) stack; Depositing second epitaxial layers over the first epitaxial layers to define a quantum well structure; Depositing third epitaxial layers over the second epitaxial layers to define an upper DBR stack; Etching the epitaxial layers to define an array of optoelectronic cells; Depositing electrodes over the third epitaxial layers that are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell to cause a first set of the optoelectronic cells to emit laser radiation in response to the excitation current; and Configuring at least one element selected among the epitaxial layers and the electrodes from a second set of the optoelectronic cells interleaved with the first set so that the optoelectronic cells in the second set do not emit the laser radiation. Device for producing an optoelectronic device according to Claim 8 wherein the array is a uniform array while the first set of opto-electronic cells are arranged in an uncorrelated pattern within the array. Device for producing an optoelectronic device according to Claim 8 , where the Configuring the at least one element comprises implanting ions in the upper DBR stack, which increases the electrical resistance of the upper DBR stack by a sufficient amount to reduce the excitation current injected into the quantum well structure below a threshold value to emit laser radiation is required. Device for producing an optoelectronic device according to Claim 8 wherein configuring the at least one element comprises configuring the electrodes of the second set so as not to inject the excitation current into the quantum well structure. Device for producing an optoelectronic device according to Claim 11 wherein configuring the electrodes comprises forming an insulating layer between the epitaxial layers and the electrodes, and etching away a portion of the insulating layer in the first set of optoelectronic cells while not etching the insulating layer in the second set of the optoelectronic cells, such that Excitation current is not injected into the quantum well structure of the second set of optoelectronic cells. Device for producing an optoelectronic device according to Claim 11 wherein configuring the electrodes comprises configuring conductors to supply an electrical current to the array of optoelectronic cells, and depositing and patterning an insulating layer to isolate the electrodes of the second set of the optoelectronic cells from the conductors, such that the electric current is not fed to the electrodes of the second set of optoelectronic cells. Device for producing an optoelectronic device according to Claim 8 wherein configuring the at least one element comprises depositing an insulating layer between the lower and upper DBR stacks, and etching out the insulating layer from a portion of the quantum well structure in the first set of the optoelectronic cells while the insulating layer is not from the second set of the optoelectronic cells optoelectronic cells is etched out.

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