US10636718B2 - Inorganic packaging module having a chip encapsulated therein - Google Patents

Inorganic packaging module having a chip encapsulated therein Download PDF

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US10636718B2
US10636718B2 US16/137,868 US201816137868A US10636718B2 US 10636718 B2 US10636718 B2 US 10636718B2 US 201816137868 A US201816137868 A US 201816137868A US 10636718 B2 US10636718 B2 US 10636718B2
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frame
substrate
layer
packaging module
cover
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US20190088567A1 (en
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Sheng Hsiang Chang
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Chang Chang Sheng Hsiang
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Chang Sheng Hsiang Chang
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the preferred embodiment(s) as well as examples listed in the description is related to a packaging module and, more particularly to an inorganic packaging module having a chip encapsulated thereon.
  • PPA Polyphthalamide
  • EMC Epoxy Molding Compound
  • the packaging module involves ultraviolet light
  • the material used either it is the PPA or the EMC
  • the material used will become crispy and fragile. It is because when the conventional packaging module is exposed under ultraviolet light for a long period of time, there will be a fundamental change to the nature of the material, which leads to the consequence that the packaging module has cracks everywhere and is no longer air-tight and water-proof.
  • a general packaging module includes a substrate, a lead-frame, i.e., dam and a cover.
  • the PPA or EMC often is adopted for making the lead-frame and there are numerous choices or the substrate depending on the application and purpose of making the packaging module.
  • the substrate may be made of an organic material, for example, plastic, i.e., PCB or an inorganic material, for example, ceramic.
  • an organic connection agent e.g., frit
  • frit is used to securely connect the substrate and the lead-frame. Again, the same frit is applied to bond the lead-frame and the cover.
  • the organic material when the organic material is exposed in an environment full of ultraviolet light, the organic material becomes hard and crispy, which leads to the easy separation between the substrate and the lead-frame or between the lead-frame and the cover. After a long period of time exposing under ultraviolet light, the bonding or connection between the substrate and the lead-frame or between the lead-frame and the cover fails and the electronic element packaged inside the packaging module will then be damaged by moist in the air.
  • ultraviolet light is required in, such as, medical industry or disinfection application to water or air
  • around 60% ⁇ 70% of light efficiency becomes heat during transformation.
  • only 10% of the efficiency is transformed into the required light and the remainder of the ultraviolet light is transformed into heat.
  • light tubes capable of emitting ultraviolet light have been largely employed to fulfill the needs in, such as, the medical industry or disinfection application to air or water.
  • LEDs light emitting diodes
  • LTCC low temperature co-fired ceramic
  • LTCC high temperature co-fired ceramic
  • the lead-frame or the cover currently adopted are no longer suitable to be compatible for such a high output LEDs, besides there are also the potential problems created by the hardening and crisp of the frit used to combine the substrate and the lead-frame and the lead-frame and the cover.
  • flip chip and wire bond Processing a flip chip is similar to conventional IC fabrication, with a few additional steps. Near the end of the manufacturing process, the attachment pads are metalized to make them more receptive to solder. This typically consists of several treatments. A small dot of solder is then deposited on each metalized pad. The chips are then cut out of the wafer as normal.
  • the chip is inverted to bring the solder dots down onto connectors on the underlying electronics or circuit board.
  • the solder is then re-melted to produce an electrical connection, typically using a Thermosonic bonding or alternatively reflow solder process. This also leaves a small space between the chip's circuitry and the underlying mounting.
  • an electrically-insulating adhesive is then “underfilled” to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system.
  • the underfill distributes the thermal expansion mismatch between the chip and the board, preventing stress concentration in the solder joints which would lead to premature failure.
  • Flip chips have several disadvantages.
  • the lack of a carrier means they are not suitable for easy replacement, or manual installation. They also require very flat mounting surfaces, which is not always easy to arrange, or sometimes difficult to maintain as the boards heat and cool.
  • the short connections are very stiff, so the thermal expansion of the chip must be matched to the supporting board or the connections may crack.
  • the underfill material acts as an intermediate between the difference in CTE of the chip and board.
  • wire bonding Another common methodology used to mount the chip onto the substrate is wire bonding.
  • the bonding parameters play a critical role in bond formation and bond quality. Parameters such bond force, ultrasonic energy, temperature, and loop geometry, to name a few, can have a significant effect on bond quality.
  • wire bonding techniques thermalsonic bonding, ultrasonic bonding, thermocompression bonding
  • types of wire bonds ball bonding, wedge bonding
  • Certain materials and wire diameters are more practical for fine pitch or complex layouts.
  • the bond pad also plays an important role as the metallization and barrier layer(s) stacked-up will impact the bond formation.
  • Typical failure modes that result from poor bond quality and manufacturing defects include: fracture at the ball bond neck, heel cracking (wedge bonds), pad liftoff, pad peel, over-compression, and improper intermetallic formation.
  • a combination of wire bond pull/shear testing, nondestructive testing, and destructive physical analysis (DPA) maybe used to screen manufacturing and quality issues.
  • wire bond manufacturing tends to focus on bond quality, it often does not account for wear-out mechanisms related to wire bond reliability. In this case, an understanding of the application and use environment can help prevent reliability issues. Common examples of environments that lead to wire bond failures include elevated temperatures, elevated temperature and humidity, and temperature cycling.
  • IMC intermetallics
  • thermo-mechanical stress is generated in the wire bond as a result of coefficient of thermal expansion (CTE) mismatch between the epoxy molding compound (EMC), the leadframe, the die, the die adhesive, and the wire bond.
  • CTE coefficient of thermal expansion
  • EMC epoxy molding compound
  • the leadframe the die
  • the die adhesive the die adhesive
  • the wire bond This leads to low cycle fatigue due to shear or tensile stresses in the wire bond.
  • Various fatigue models have been used to predict the fatigue life of wire bonds under such conditions.
  • a packaging module having a chip encapsulated therein.
  • Using a complete inorganic packaging material to encapsulate the chip allows the manufacturing process to be irrelevant to the difficulties so generated by using organic packaging material, such as epoxy resin, e.g., frit or other organic compound.
  • the primary objective of the preferred embodiment of the present invention is to provide a packaging module having a substrate, a chip securely mounted on and electrically connected to the substrate, a frame securely mounted on top of the substrate to enclose the chip inside a space defined by the substrate and the frame, a first Ni layer and a first Au layer formed between the substrate and the frame to securely connect the frame to the substrate and a cover firmly mounted on top of the frame to sealingly encapsulate the chip inside the space.
  • Another objective of the preferred embodiment of the present invention is that a second Ni layer and a second Au layer are formed between the frame and the cover to firmly mount the cover on the frame.
  • the frame is made of a metallic material which is selected from the group containing of Al, Cu, alloy of Al, alloy of Cu, alloy of Au and alloy of Fe—Co—Ni.
  • the substrate further has a first titanium layer and a patterned copper layer sequentially formed and sandwiched between the substrate and the frame, the patterned copper layer is formed on two opposite sides of the substrate and electrically connected to one another.
  • the frame is made of a nonmetallic material selected from the group consisting of AlN, Al2O3, SiN and SiC.
  • the frame further has a second titanium layer and a second patterned copper layer sequentially formed on two opposite sides of the frame to correspond to and connect to the first Ni layer, the first Au layer, the first Titanium layer and the patterned copper layer.
  • the cover is transparent and made of quartz.
  • Another objective of the preferred embodiment of the present invention is that a third titanium layer and a third Au layer formed between the cover and the frame to sealingly encapsulate the chip inside the space.
  • Another objective of the preferred embodiment of the present invention is that an Au—Sn alloy pad sandwiched between the frame and the substrate.
  • Another objective of the preferred embodiment of the present invention is that a second Au—Sn alloy pad sandwiched between the frame and the cover.
  • FIG. 1 is a cross sectional view showing the structure of the substrate of the preferred embodiment of the invention.
  • FIG. 2 is still a cross sectional view showing that multiple islands are formed on at least one side of the substrate
  • FIG. 3 is a schematic cross sectional view showing that a chip is electrically connected to a pair of islands
  • FIG. 4 is a schematic cross sectional view showing that a frame is provide on top of the substrate to surround the chip.
  • FIG. 5 is a schematic view showing that a cover is mounted on top of the frame to encapsulate the chip.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
  • the following description describes different preferred embodiments of how the packaging module of the invention is formed and what kind of material(s) is adopted to make the packaging module of the preferred embodiment free from the damages caused by moist in the air.
  • the preferred embodiment of the present invention provides an inorganic packaging module having at least a chip encapsulated inside the packaging module.
  • the packaging module includes a substrate carrying thereon a chip, a frame integrally formed on top of the substrate and surrounding the chip and a transparent cover on top of the frame to enclose the chip inside the packaging module.
  • the cover is made of quartz. It is to be noted that the cover is securely connected to the frame using inorganic metal as a connection agent.
  • connection between the substrate and the frame and between the frame and the cover are both using inorganic metal as a connection agent and because the metal is selected from the same group, the coefficient of thermal expansion (CTE) at the interface between the substrate and the frame as well as the interface between the frame and the cover is well compatible during expansion due to heat and contraction resulting from cold.
  • the finished surface mount device (SMD) has excellent heat conduction and great effect preventing moist from seeping into the packaging module to damage the chip inside the packaging module.
  • each element in this embodiment has numerous processing methods and each method is able to fully achieve the desired purpose of the invention, the following description will be describing different kinds of the substrate and of the frame and then a description about the combination between the substrate and the frame is provided. Later on, a description about the cover and the combination between the cover and the frame is offered.
  • a substrate 10 made of, such as, ceramic is provided.
  • At least a through hole 11 having a trapezoidal shape is defined through the substrate 10 and filled with a conductive material, such as, copper (Cu).
  • the through hole 11 defined by, preferably, laser, and having the trapezoidal shape is because when laser is employed, as depth goes deeper into the substrate 10 , energy of the laser decreases, which leads to the result that the size of the initial stage forming the opening in the substrate 10 is larger than that of the final stage just before the through hole is completed.
  • a titanium (Ti) layer 12 having a thickness range between 0.01 ⁇ m ⁇ 10 ⁇ m is formed on all faces of the substrate 10 and including side faces surrounding the through hole 11 .
  • a layer of titanium preferably via sputtering.
  • a patterned copper layer 14 of thickness between 0.01 ⁇ m ⁇ 700 ⁇ m is formed on top and bottom of the titanium layer 12 and the through hole 11 is filled with copper as well to form a copper bar 16 to electrically connect to the top copper layer and the bottom patterned copper layer 14 .
  • a nickel (Ni) layer 20 having a thickness ranging from 0 ⁇ m ⁇ 10 ⁇ m is formed via, for example, plating, on the patterned copper layer 14 .
  • the nickel layer 20 is optionally formed on top of the patterned copper layer 14 and which is why the thickness of the nickel layer 20 starts from 0 ⁇ m.
  • An Au layer 22 is then formed on top of the nickel layer 20 for connection via, for example, plating and has a thickness ranging from 0.05 ⁇ m ⁇ 20 ⁇ m. Therefore, it is to be noted that from the central core of the structure shown in FIG.
  • a substrate 10 is provided and then a titanium layer 12 is formed.
  • a patterned copper layer 14 together with a copper bar 16 formed inside the through hole of the substrate to electrically connect to the patterned copper layer 14 is formed.
  • a nickel (Ni) layer 20 and an Au layer 22 are sequentially formed.
  • the nickel-Au layers may also be replaced with Ni—Ag or compound of nickel-Palladium (pd)-Au.
  • Application of a proper mask and the related well known process multiple islands 30 are formed on the substrate 10 .
  • Each of the islands 30 contains the Ti layer 12 , the copper layer 14 , the Ni layer 20 and the Au layer 22 .
  • the islands 30 are formed on two opposite sides of the substrate 10 .
  • the islands 30 on one side of the substrate 10 are for connection with a chip (not shown) and the islands 30 on the other side of the substrate 10 are for connection with other electronic devices, such as, a printed circuit board (PCB).
  • PCB printed circuit board
  • FIGS. 3 and 4 another embodiment to fulfill the desired purpose or effect of the present invention is shown in FIGS. 3 and 4 .
  • a chip 80 of any kind, is provided on top of the islands 30 and a pad 81 made of, preferably, alloy of Au—Sn is sandwiched between the islands 30 and the chip 80 .
  • the pad 81 functions to securely connect the chip 80 to the substrate 10 via, of course, the islands 30 .
  • the use of the pad 81 ensures electrical connection between the chip 81 and the islands 30 .
  • a frame 40 as shown in FIG. 4 , having two openings in communication with one another is provided on top of the substrate 10 to surround the chip 80 .
  • the frame 40 may be made of such as AlN, Al 2 I 3 , SiN 4 or SiC and has a titanium layer formed on two opposite sides of the frame 40 and having a thickness between 0.01 ⁇ m ⁇ 10 ⁇ m to function as a bonding medium between copper and ceramic.
  • a copper layer having a thickness between 0.01 ⁇ m ⁇ 700 ⁇ m is formed on a side face of each of the titanium layer.
  • a Ni layer is formed on only one side face of the copper layer and has a thickness between 0 ⁇ m ⁇ 10 ⁇ m.
  • the forming of the Ni layer can be neglected or removed depending on design choice for the product and an Au layer having a thickness between 0.05 ⁇ m ⁇ 20 ⁇ m is formed on a side face of the Ni layer. It is appreciated from the earlier discussion that the Ti layer, Copper layer, Ni layer and Au layer together form the island 30 . As such, no respective reference numeral is provided on the corresponding drawing as they are previously described and shown in the earlier drawings.
  • a modified Non-Organic Ceramic Heterogeneity (NCH) technology i.e., Gold-Gold interconnection (GGI) is employed to make use of metal diffusion effect and reach the final result of producing an eutectic compound in the interfaces between the substrate 10 and the frame 40 , which results in that the frame 40 and the substrate 10 are firmly connected to each other in a water and air tight manner.
  • NCH Non-Organic Ceramic Heterogeneity
  • GGI Gold-Gold interconnection
  • the fame 40 may be made of a kind of metal, such as aluminum or copper, an alloy of, such as, aluminum alloy, copper alloy or Fe—Co—Ni alloy.
  • the frame 40 has an island 30 formed on its top side and bottom side. That is, a complete structure of a Ti layer, a copper layer, a Ni layer and an Au layer is formed on two opposite sides of the frame 40 and especially the bottom island 30 of the frame 40 corresponds and connects to one of the islands 30 of the substrate 10 .
  • the formation of island 30 on the top and bottom sides thereof may not be necessary. That is, the Ti layer and the Copper layer may be omitted from the manufacture process and the Ni layer and the Au layer are left when the frame 40 is made of a kind of metal listed above.
  • a Nickel (Ni) layer 20 having a thickness ranging from 0.1 ⁇ m ⁇ 3 ⁇ m is formed on two opposite sides of the frame 40 .
  • an Au layer 22 having a thickness of 0.05 ⁇ m ⁇ 20 ⁇ m is formed on two opposite sides of the Ni layer 20 to function as a bonding or connection agent.
  • the addition of the Ni layer is to prevent the later-added Au layer from reaction with the material of the frame 40 .
  • an Au—Sn alloy pad may be optionally added to the Au layer 22 .
  • the frame 40 is made of a non-metal material selected from the group consisting of, such as, AlN, Al 2 O 3 , Si 3 N 4 or SiC, the outermost layer formed thereon is the Au layer 22 and the Au—Sn alloy pad and the outermost layer of each island 30 formed on the substrate 10 is also Au layer and the Au—Sn alloy pad, the GGI interconnection is ready and under properly selected parameters for temperature and pressure, the frame 40 and the substrate 10 are sealingly connected to one another.
  • the frame 40 is made of a metal selected from the group consisting of, such as, aluminum, copper, aluminum alloy, copper alloy or Fe—Co—Ni alloy, as shown in FIG. 4 , the outermost layer is the Au layer and the outermost layer of each island 30 on the substrate 10 is also the Au layer, the GGI interconnection is ready and under the properly selected parameters for temperature and pressure, the frame 30 and the substrate 10 are sealingly connected to one another.
  • a cover 50 preferably transparent, made of quartz is provided on top of the frame 40 to enclose the chip 80 in the space defined by the substrate 10 and the frame 40 . Still, in order to securely connect the cover 50 to the frame 40 and to enclose the chip 80 without being influenced by the moisture in the air, a Ti layer 51 , an Au layer 52 and an Au—Sn alloy pad 53 are formed on a side face of the cover 50 to correspond and connect to the island 30 when the frame 40 is made of a non-metal material and to the Ni—Au layer and the Au—Sn alloy pad when the frame 40 is made of a metal as previously described.
  • an Au—Sn alloy pad 53 ′ may be added on top of the islands 30 and sandwiched between the islands 30 and the frame 40 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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TW106132332 2017-09-21
TW106132332A 2017-09-21
TW106132332A TWI651872B (zh) 2017-09-21 2017-09-21 一種紫外線發光二極體晶片封裝結構

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