US10497623B2 - Method of manufacturing a semiconductor package including a shield layer - Google Patents

Method of manufacturing a semiconductor package including a shield layer Download PDF

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US10497623B2
US10497623B2 US15/958,847 US201815958847A US10497623B2 US 10497623 B2 US10497623 B2 US 10497623B2 US 201815958847 A US201815958847 A US 201815958847A US 10497623 B2 US10497623 B2 US 10497623B2
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semiconductor package
shield layer
sealant
semiconductor
package
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US20180308756A1 (en
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Youngsuk Kim
Byeongdeck Jang
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Disco Corp
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Disco Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a method of manufacturing a semiconductor package which has a shielding function.
  • a semiconductor package for use in a portable communication apparatus such as a mobile phone is required to restrain leakage of electromagnetic noises to the exterior, for preventing bad influences on communication characteristics. Therefore, it is necessary for the semiconductor package to have a shielding function.
  • a semiconductor package having a shielding function there has been known one in which a semiconductor chip mounted on an interposer substrate is sealed with a sealant, and a shield layer is formed along an outer surface of the sealant layer. While the shield layer may be composed of a sheet metal shield, the considerable thickness of the sheet metal in this case hampers reductions in size and thickness of the apparatus.
  • the shield layer is deposited (builds up) between the adjacent packages. Then, at the time of picking up the semiconductor package, large burs may be generated due to, for example, tearing-up of the shield layer between the packages, or division between the packages may not be achieved successfully. In such a case, it is necessary to separately remove the burs from the semiconductor package by a processing tool or the like. The deburring work needs a lot of time, and there may exist burs which cannot be completely removed from the semiconductor package even by use of a processing tool.
  • a method of manufacturing a semiconductor package obtained by dividing a semiconductor package substrate having a plurality of semiconductor chips which are mounted in a plurality of regions on a wiring board partitioned by a plurality of intersecting division lines and which are sealed with a sealant, the semiconductor package substrate being divided along the division lines.
  • the method includes: an adhering step of adhering a wiring board side of the semiconductor package substrate onto a support member having an adhesive layer; a groove forming step of cutting in from a sealant side to at least an intermediate position in the sealant along the division lines by a processing tool, to form grooves having a first width at least at an upper surface of the sealant, after the adhering step is conducted; a dividing step of cutting in from the sealant side to an intermediate position in the support member along the grooves by use of a cutting blade having a second width smaller than the first width, to divide the semiconductor package substrate such that the adjacent semiconductor packages are spaced by a predetermined interval X mm from each other, after the groove forming step is conducted; a shield layer forming step of forming a shield layer on side surfaces of the semiconductor packages and an upper surface of the sealant from a conductive material supplied from above the sealant, after the dividing step is conducted; and a picking-up step of picking up the semiconductor package formed with the shield layer, after the shield layer forming step
  • the first width and the second width are so set that an inclination or a step is generated in each side surface in such a manner that outer shape size of the semiconductor package becomes larger than that at an upper surface of the sealant of each of the divided semiconductor packages on route from the upper surface toward the lower surface of the sealant, and where the side surface length from a lower end of the inclination or step of the semiconductor package to a groove bottom of the cut into the support member is Y mm, then the first width, the second width, the side surface length Y mm, and shield layer forming conditions are so set as to obtain such an aspect ratio Y/X that at the time of formation of the shield layer, the shield layer is formed on the side surfaces but the amount of the shield layer formed on the groove, bottom between the semiconductor packages is reduced.
  • a method of manufacturing a semiconductor package obtained by dividing a semiconductor package substrate having a plurality of semiconductor chips which are mounted in a plurality of regions on a wiring board partitioned by a plurality of intersecting division lines and which are sealed with a sealant, the semiconductor package substrate being divided along the division lines.
  • the method includes: a dividing step of dividing the semiconductor package substrate along the division lines, and forming each side surface of each semiconductor package with an inclination or step such that outer shape size of the semiconductor package becomes larger than that at an upper surface of the sealant of the semiconductor package on route from the upper surface toward a lower surface of the sealant; a semiconductor package aligning step of aligning the divided individual semiconductor packages in such a manner that the adjacent semiconductor packages are spaced by a predetermined interval X mm from each other, and holding a wiring board side of the aligned semiconductor packages on a holding jig or adhering the wiring board side onto a support member; a shield layer forming step of forming a shield layer on side surfaces of the semiconductor packages and an upper surface of the sealant from a conductive material supplied from above the sealant; and a picking-up step of picking up the semiconductor package formed with the shield layer, after the shield layer forming step is conducted.
  • side surface length from a lower end of the inclination or step of the semiconductor package to the holding jig or the support member is Y mm
  • the inclination or step, the side surface length Y mm, the predetermined interval X mm, and the shield layer forming conditions are so set as to obtain such an aspect ratio Y/X that at the time of formation of the shield layer, the shield layer is formed on the side surfaces but the amount of the shield layer formed on a bottom surface between the semiconductor packages is reduced.
  • the side surface of the semiconductor package is formed with the inclination or step such that the outer shape size of the semiconductor package becomes larger than that at the upper surface of the sealant on route from the upper surface toward the lower surface of the sealant of the semiconductor package after the dividing.
  • the side surface is divided into an upper portion and a lower portion.
  • the shield layer on the side surface of the semiconductor package and the shield layer on the groove bottom are separated from each other more easily, so that generation of burs upon picking-up of the semiconductor package can be restrained. Therefore, the need for a deburring work is eliminated, and, accordingly, processing quality and processing time can be improved.
  • the semiconductor packages are placed in regions formed by partitioning a holding surface of the holding jig or the support member by grooves provided in a grid pattern, and are aligned such that the adjacent semiconductor packages are spaced by the predetermined interval X mm from each other, and the groove width of the grooves is larger than the predetermined interval X mm between the semiconductor packages.
  • the shield layer is less liable to be formed on the groove bottom, and generation of burs upon picking-up of the semiconductor package can be restrained.
  • FIG. 1 is a sectional schematic view of a semiconductor package according to the present embodiment
  • FIGS. 2A and 2B are schematic sectional views depicting a method of manufacturing a semiconductor package according to a comparative example
  • FIGS. 3A to 3D are schematic sectional views depicting a method of manufacturing a semiconductor package according to a first embodiment
  • FIGS. 4A to 4D are schematic sectional views depicting the method of manufacturing a semiconductor package according to the first embodiment
  • FIGS. 5A to 5C are schematic sectional views depicting a method of manufacturing a semiconductor package according to a second embodiment
  • FIGS. 6A to 6D are schematic sectional views depicting the method of manufacturing a semiconductor package according to the second embodiment
  • FIGS. 7A to 7E are schematic sectional views depicting an example of variation of side surface shape of the semiconductor package
  • FIG. 8 is a schematic sectional view of a specimen
  • FIGS. 9A to 9D are diagrams: depicting the relation between step coverage and aspect ratio of the specimen.
  • FIGS. 10A and 10B are schematic sectional views depicting modifications of the semiconductor package
  • FIGS. 11A to 11C are schematic sectional views depicting a modification of formation of a groove in a semiconductor package substrate
  • FIG. 12 is a schematic sectional view depicting a modification of the semiconductor package.
  • FIG. 13 is a sectional view depicting a modification of a catting blade.
  • FIG. 1 is a sectional schematic view of a semiconductor package according to the present embodiment.
  • FIGS. 2A and 2B are figures for explaining a method of manufacturing a semiconductor package according to a comparative example. Note that the following embodiment is merely illustrative, and other step may be provided between the steps, and the order of the steps may be changed, as required.
  • a semiconductor package 10 is any packaged semiconductor apparatus that requires shielding in view of so-called electro-magnetic interference (EMI), and is configured such that leakage of electromagnetic noises to the surroundings is restrained by a shield layer 16 provided at an outer surface thereof.
  • EMI electro-magnetic interference
  • semiconductor chips 12 mounted on an upper surface of a wiring board (interposer substrate) 11 are each sealed by a resin layer (sealant) 13 , and bumps 14 are disposed on a lower surface of the wiring board 11 .
  • the wiring board 11 is formed with electrodes to foe connected to the semiconductor chips 12 , and various wirings inclusive of a ground line 17 .
  • the semiconductor chip 12 is formed by individualizing a semiconductor wafer on the basis of each device on a semiconductor substrate, and is mounted at a predetermined position on the wiring board 11 .
  • an inclined surface 25 such as to expand outward in going downward from a package upper surface 22 is formed, and a shield layer 16 is formed on the inclined surface 25 from above by a sputtering method or the like.
  • the inclined surfaces 25 of the package side surfaces 23 intersect obliquely the forming direction of the shield layer 16 , so that it is easy to form the shield layer 16 on the inclined surface 25 .
  • a semiconductor package 100 according to a comparative example is formed by a method in which a semiconductor package substrate 105 with semiconductor chips 102 on a wiring board 101 being sealed by a resin layer 103 is fully cut by use of a cutting blade 111 .
  • the semiconductor packages 100 after division are aligned on a tape 106 , and a shield layer 107 (see FIG. 2B ) is formed thereon from above by sputtering or the like.
  • package side surfaces 109 are orthogonal to a package upper surface 108 , the shield layer 107 with an appropriate thickness cannot be formed unless a sufficient package interval is secured. For this reason, there has been a problem, that the time required for forming the shield layer 107 is prolonged, and materials cost and equipment cost are raised.
  • the shield layer 107 deposited also in a thick form on a groove bottom 110 between the packages is peeled from the tape 106 together with the semiconductor package 100 .
  • the picking-up of the semiconductor package 100 may tear up the shield layer 107 between the packages, leaving a bur 112 at the lower side of a package side surface 109 , or the shield layer 107 may not be cut between the packages.
  • the yield of the semiconductor package 100 may be lowered, or a deburring work may be further needed and a lot of time may be required therefor.
  • the thickness of the shield layer is greatly affected by the aspect ratio between the packages.
  • the side surface is inclined or the package interval is enlarged to thereby form a shield layer in an appropriate thickness, and, at the lower side of the package side surface, the package interval is reduced (the aspect ratio is raised) to thereby reduce the thickness of the shield layer.
  • FIGS. 3A to 4D are figures for explaining the method of manufacturing a semiconductor package according to the first embodiment.
  • FIG. 3A depicts an example of a mounting step
  • FIG. 3B depicts an example of a substrate producing step
  • FIG. 3C depicts an example of an adhering step
  • FIG. 3D depicts an example of a groove forming step.
  • FIG. 4A depicts an example of a dividing step
  • FIGS. 4B and 4C depict an example of a shield layer forming step
  • FIG. 4D depicts an example of a picking-up step.
  • a mounting step is first conducted.
  • a plurality of semiconductor chips 12 are mounted in a plurality of regions partitioned in a grid pattern by intersecting division lines on a surface of a wiring board 11 .
  • the wiring board 11 is formed therein with wirings such as a ground line 17 , and bumps 14 are disposed on a lower surface of the wiring board 11 .
  • one end of a wire 19 is connected to an electrode on the upper surface of the semiconductor chip 12
  • the other end of the wire 19 is connected to an electrode 18 on the surface of the wiring board 11 .
  • the wire bonding is not limitative, and flip chip bonding may be performed in which electrodes on the lower surface of the semiconductor chip 12 are directly connected to electrodes on the surface of the wiring board 11 .
  • a substrate producing step is performed after the mounting step is conducted.
  • a sealant 24 is supplied to a front surface side of the wiring board 11 having the plurality of semiconductor chips 12 mounted thereon, and the semiconductor chips 12 are each sealed with the sealant 24 , whereby a semiconductor package substrate 15 (see FIG. 3C ) is produced.
  • the lower surface of the wiring board 11 with the semiconductor chips 12 mounted thereon is held by a holding jig (not depicted), and a mold 32 is disposed so as to cover the upper surface of the wiring board 11 .
  • An upper wall of the mold 32 has an injection port 33 opened therein, and a supply nozzle 34 for supplying the sealant 24 is positioned on the upper side of the injection port 33 .
  • the sealant 24 is supplied onto the upper surface of the wiring board 11 from the supply nozzle 34 through the injection port 33 , to seal the semiconductor chips 12 .
  • the sealant 24 is cured by heating or drying, whereby the semiconductor package substrate 15 having a resin layer 13 (see FIG. 3C ) formed on the upper surface of the wiring board 11 is produced.
  • the sealant 24 one that has a curing property is used; for example, the sealant 24 can be selected from among epoxy resins, silicone resins, urethane resins, unsaturated polyester resins, acrylic urethane resins, poly inside resins and the like.
  • the sealant 24 is not limited to a liquid one, and a sheet-shaped or powdery resin can also be used. In this way, the plurality of semiconductor chips 12 on the wiring board 11 are sealed all together.
  • the front surface of the semiconductor package substrate 15 may be planarized by grinding, after the substrate producing step.
  • the resin layer 13 covering the semiconductor chips 12 can be adjusted to a desired thickness. In this way, a planarizing step may be performed after the substrate producing step.
  • the mounting step and the substrate producing step may be omitted.
  • an adhering step is performed after the substrate producing step is conducted.
  • an adhesive tape 35 is adhered such as to close a central opening of a ring frame (not depicted) as a support member having an adhesive layer, and the wiring board 11 side of the semiconductor package substrate 15 is adhered onto the adhesive tape 35 .
  • the bumps 14 of the semiconductor package substrate 15 come into the adhesive layer of the adhesive tape 35 , whereby the semiconductor package substrate 15 is favorably supported by the ring frame through the adhesive tape 35 .
  • a ring frame which is circular in top plan view may be used, or a ring frame which is tetragonal in top plan view may be used.
  • a groove forming step is performed after the adhering step is conducted.
  • the wiring board 11 side of the semiconductor package substrate 15 is held by a chuck table (not depicted) through the adhesive tape 35 .
  • a V blade 28 (processing tool) having a tip formed in a V shape is made to cut into the wiring board 11 (semiconductor package substrate 15 ) from the resin layer (sealant) 13 side to an intermediate position of the thickness of the wiring board 11 (semiconductor package substrate 15 ), whereby a V groove 29 is formed along each region corresponding to the division line.
  • the V blade 28 is formed by binding diamond abrasive grains or the like with a binder into a disk shape with a V-shaped tip, and is mounted to a tip of a spindle (not depicted).
  • the V blade 28 is aligned to the division line on the outside of the semiconductor package substrate 15 , and is lowered to a depth corresponding to an intermediate position of the thickness of the wiring board 11 on the outside of the semiconductor package substrate 15 . Then, the semiconductor package substrate 15 is put into cutting feeding in a horizontal direction in relation to the V blade 28 , whereby the semiconductor package substrate 15 is half cut along the division line, and the V groove 29 having a first width t 1 is formed at least at the upper surface of the resin layer 13 . This half cutting is repeated, whereby a plurality of V grooves 29 are formed in the upper surface of the semiconductor package substrate 15 along the division lines.
  • the tip of the V blade 28 is formed in a V shape in the present embodiment, this configuration is not limitative.
  • the tip of the V blade 28 need only be in such a shape that the V groove 29 can be thereby formed in the semiconductor package substrate 15 .
  • the tip of a cutting blade 99 may be formed in a V shape with a flat tip. Therefore, the V shape of the tip of the cutting blade is not limited to a perfect V shape in which the cutting blade is pointed to the tip thereof, but includes a shape in which the tip of the cutting blade is in a substantially V shape with a flat tip.
  • the V-shaped surface of the tip of the V blade may not necessarily be inclined rectilinearly, but may be somewhat rounded.
  • a dividing step is performed after the groove forming step is conducted.
  • a cutting blade 36 having a second width t 2 smaller than the first width t 1 is used; the cutting blade 36 is made to cut in from the resin layer 13 side to an intermediate position of the thickness of the adhesive tape 35 along the V grooves 29 , whereby the semiconductor package substrate 15 is divided into individual semiconductor packages 10 .
  • the cutting blade 36 is formed by binding diamond abrasive grains or the like with a binder into a disk shape with a rectangle-shaped tip, and is mounted to a tip of a spindle (not depicted). With the tip of the cutting blade 36 being rectangular in shape, a vertical rectangular groove 37 is formed from the groove bottom of the V groove 29 toward the adhesive tape 35 .
  • the cutting blade 36 is aligned to the division line on the outside of the semiconductor package substrate 15 , and the cutting blade 36 is lowered to a depth corresponding to an intermediate position of the thickness of the adhesive tape 35 , on the outside of the semiconductor package substrate 15 .
  • the semiconductor package substrate 15 is put into cutting feeding in a horizontal direction in relation to the cutting blade 36 , whereby the semiconductor package substrate 15 is fully cut along the division line, and the adjacent semiconductor packages 10 are divided from each other in the manner of being spaced from each other by a predetermined interval of X mm.
  • the full cutting is repeated, whereby the semiconductor package substrate 15 is individualized along the division lines.
  • the package side surface 23 is formed with the inclined surface 25 such that the outer shape size of package becomes larger than that at the package upper surface (sealant upper surface) 22 on route from, the package upper surface 22 toward a lower surface.
  • the package interval is wider on the inclined surface 25 side and is narrower on the side of a vertical surface 26 . While the details will be described later, with the package interval narrowed at the lower side (the vertical surface 26 side) of the package side surface 23 , the aspect ratio is raised, and it is ensured that the shield layer 16 (see FIG. 4B ) is less liable to be deposited (to build up) on a groove bottom 38 between the packages.
  • a shield layer forming step is performed after the dividing step is conducted.
  • the shield layer 16 is formed on the package upper surface 22 and the package side surfaces 23 from a conductive material supplied from above the resin layer 13 .
  • each semiconductor package 10 is held by a holding jig (not depicted) through the adhesive tape 35 .
  • a film of the conductive material is formed on the semiconductor packages 10 from above by sputtering or the like, whereby the shield layer 16 having a desired thickness is formed on the package upper surfaces 22 and the package side surfaces 23 .
  • the inclined surface 25 of the package side surface 23 is inclined in such a manner as to expand outward in going downward from the package upper surface 22 , and the inclined surface 25 intersects obliquely the forming direction (vertical direction) of the shield layer 16 . Therefore, when the shield layer 16 is formed on the semiconductor package 10 , the shield, layer 16 is formed in a thickness large enough to display a sufficient shielding effect, not only on the package upper surface 22 but also on the inclined surfaces 25 . Although the shield layer 16 is formed also on the vertical surfaces 26 of the package side surfaces 23 and on the groove bottom 38 between the packages, the thickness of the shield layer 16 there is controlled according to the aspect ratio between the packages (the aspect ratio of the rectangular groove 37 ).
  • the aspect ratio between the packages is represented by Y/X, where Y (mm) is the depth from the lower end of the inclined surface 25 to the groove bottom 38 of the cut into the adhesive tape 35 (the length of the side surface), and X (mm) is the opposing spacing between the vertical surfaces 26 .
  • the first width t 1 , the second width t 2 (see FIG. 4A ), the depth Y mm, and the shield layer forming conditions are so set as to obtain such an aspect ratio that at the time of formation of the shield layer, the shield layer 16 is formed on the package side surfaces 23 but the thickness of the shield layer 16 formed on the groove bottom 38 between the packages is reduced. Note that for each of these conditions, experimentally, empirically or theoretically obtained values are set.
  • the inclined surfaces 25 of the package side surfaces 23 and the upper side of the vertical surfaces 26 are less liable to be influenced by the aspect ratio, whereas the lower side of the vertical surfaces 26 of the package side surfaces 23 and the groove bottom 38 between the packages are more liable to be influenced by the aspect ratio. Therefore, the shield layer 16 can be formed in an appropriate thickness, irrespectively of the aspect ratio, on the inclined surfaces 25 and at the upper side of the vertical surfaces 26 . On the other hand, at the lower side of the vertical surfaces 26 and on the groove bottom 38 , the thickness of the shield layer 16 is varied, according to the aspect ratio between the packages.
  • the thickness of the shield layer 16 at the lower side of the vertical surfaces 26 and on the groove bottom 38 will be small, whereas when the aspect ratio is low, the thickness of the shield layer 16 at the lower side of the vertical surfaces 26 and on the groove bottom 38 will be large.
  • the control of the aspect ratio is carried out mainly by varying the depth Y mm from the lower end of the inclined surface 25 to the groove bottom 38 , since the opposing spacing X mm between the vertical surfaces 26 is dependent on the line width of the division line.
  • the aspect ratio set to be high on the vertical surface 26 side it is ensured that the shield layer 16 is formed in an appropriate thickness on the inclined surfaces 25 and at the upper side of the vertical surfaces 26 where the influence of the aspect ratio is slight, whereas the shield layer 16 is formed in a thin form at the lower side of the vertical surfaces 26 and on the groove bottom 38 where the influence of the aspect ratio is heavy. Therefore, leakage of electromagnetic noise is restrained by the shield layer 16 on the upper side in the semiconductor package 10 , whereas the shield layer 16 is thinned and generation of burs is restrained on the lower side in the semiconductor package 10 .
  • the ground line 17 of the wiring board 11 is exposed to the exterior at the lower side of the inclined surfaces 25 of the package side surfaces 23 . Since the shield layer 16 is formed in an appropriate thickness at the lower side of the inclined surfaces 25 and the shield layer 16 is connected to the ground line 17 there, electromagnetic noises generated in the semiconductor package 10 are released out of the semiconductor package 10 through the ground line 17 . Note that although the shield layer 16 is thinned at the lower side of the vertical surfaces 26 of the package side surfaces 23 , the electromagnetic noises have been cut by the multiplicity of wirings in the wiring board 11 . Therefore, leakage of electromagnetic noises to electronic parts in the surroundings of the semiconductor package 10 is prevented as a whole.
  • the shield layer 16 is a multilayer film having a thickness of several micrometers or more formed from at least one metal selected from among copper, titanium, nickel, gold and the like, and is formed by, for example, a sputtering method, an ion plating method, a spray coating method, a CVD method, an ink jet method, or a screen printing method.
  • the shield layer 16 may be formed by vacuum lamination in which a metallic film having the above-mentioned multilayer film is adhered to the package upper surface 22 and the package side surfaces 23 in a vacuum atmosphere. In this way, a semiconductor package 10 in which the package upper surface 22 and the package side surfaces 23 are covered with the shield layer 16 is manufactured.
  • a picking-up step is performed after the shield layer forming step is conducted.
  • the semiconductor package 10 formed with the shield layer 16 is picked up by a picker (not depicted) or the like.
  • deposition (build-up) of the shield layer 16 at the lower side of the vertical surfaces 26 of the package side surfaces 23 or on the groove bottom 38 between the packages is restrained, by the control of the aspect ratio between the packages. Therefore, at the time of picking up the semiconductor package 10 , the shield layer 16 is not peeled off from the groove bottom 38 of the adhesive tape 35 , and burs are not liable to be generated at package lower portions.
  • FIGS. 5A to 6D a method of manufacturing a semiconductor package according to a second embodiment will be described below.
  • the second embodiment differs from the first embodiment in that a shield layer is formed in a state in which semiconductor packages are aligned on a protective tape. Therefore, the same points of configuration as those in the method of manufacturing the semiconductor package according to the first embodiment will be described in a simplified manner.
  • FIGS. 5A to 6D are figures for explaining the method of manufacturing a semiconductor package according to the second embodiment.
  • FIG. 5A depicts an example of a mounting step
  • FIG. 5B depicts an example of a substrate producing step
  • FIG. 5C depicts an example of a dividing step
  • FIG. 6A depicts an example of a semiconductor package aligning step
  • FIGS. 6B and 6C depict an example of a shield layer forming step
  • FIG. 6D depicts an example of a picking-up step.
  • a mounting step is first performed.
  • a plurality of semiconductor chips 12 are mounted in a plurality of regions partitioned by division lines on a wiring board 11 .
  • the wiring board 11 is formed therein with wirings such as a ground line 17 , and bumps 14 are disposed on a lower surface of the wiring board 11 .
  • one end of a wire 19 is connected to an electrode on an upper surface of the semiconductor chip 12
  • the other end of the wire 19 is connected to an electrode 18 on the surface of the wiring board 11 .
  • the wire bonding is not restrictive, and flip chip bonding may be conducted in which electrodes on the lower surface of the semiconductor chip 12 are directly connected to electrodes on the surface of the wiring board 11 .
  • a substrate producing step is performed after the mounting step is conducted.
  • a sealant 24 is supplied onto the wiring board 11 on a holding jig (not depicted) from a supply nozzle 34 through an injection port 33 of a mold 32 , and the plurality of semiconductor chips 12 on the wiring board 11 are sealed with the sealant 24 .
  • the sealant 24 is cured by .heating or drying, whereby a semiconductor package substrate 15 in which a resin layer 13 (see FIG. 5C ) is formed on an upper surface of the wiring board 11 is produced.
  • a planarizing step of planarizing the resin layer 13 by grinding may be performed after the substrate producing step.
  • the mounting step and the substrate producing step may be omitted.
  • a dividing step is performed after the substrate producing step is conducted.
  • the resin layer 13 side is half cut by a V blade 28 , whereby V grooves 29 are formed along division lines.
  • the wiring board 11 is fully cut by a cutting blade 36 , whereby the semiconductor package substrate 15 is divided along the division lines into individual semiconductor packages 10 . In this way, the semiconductor package substrate 15 is individualized by step cutting conducted using the V blade 28 and the cutting blade 36 .
  • the semiconductor package substrate 15 is formed with the V grooves 29 , and with narrow-width rectangular grooves 37 at groove bottoms of the V grooves 29 . Therefore, package side surfaces 23 are formed with inclined surfaces 25 such that the outer shape size of package becomes larger than that at the package upper surface 22 on route from the package upper surface 22 toward the lower surface. In regard of the package side surfaces 23 , the package interval is greater on the inclined surface 25 side, and is smaller on the vertical surface 26 side. Therefore, in a semiconductor package aligning step conducted at a later stage, the semiconductor packages 10 can be aligned in such a manner that the package interval is reduced on the lower side in the semiconductor packages 10 .
  • the semiconductor package aligning step is performed after the dividing step is conducted.
  • the divided semiconductor packages 10 are aligned on a protective tape 41 serving as a support member.
  • a holding surface of the protective tape 41 is formed with shallow grooves (grooves) 42 in a grid pattern, and the holding surface is partitioned by the shallow grooves 42 into a plurality of regions.
  • the semiconductor package 10 is placed in each of the regions, whereby the semiconductor packages 10 are aligned in a state in which the adjacent semiconductor packages 10 are spaced from each other by a predetermined interval of X mm.
  • the vertical surfaces 26 of the semiconductor package 10 protrude into the inside of the shallow groove 42 .
  • the semiconductor packages 10 may be held on a holding jig, instead of the protective tape 41 .
  • a shield layer forming step is performed after the semiconductor package aligning step.
  • a shield layer 16 is formed on the package upper surfaces 22 and the package side surfaces 23 from a conductive material supplied from above the resin layer 13 .
  • the shield layer 16 is formed in a desired thickness not only on the package upper surfaces 22 but also on the inclined surfaces 25 .
  • the shied layer 16 is formed also on the vertical surfaces 26 of the package side surfaces 23 and on the groove bottoms 43 of the shallow grooves 42 of the protective tape 41 , the thickness of the shield layer 16 there is controlled according to the aspect ratio between the packages on the package lower side.
  • the aspect ratio between the packages is represented by Y/X, where Y (mm) is the depth from the lower end of the inclined surface 25 to the groove bottom 43 of the shallow groove 42 of the protective tape 41 (the length of the side surface), and X (mm) is the opposing spacing between the vertical surfaces 26 .
  • the inclination of the inclined surface 25 , the depth Y mm, the predetermined interval X mm, and the shield layer forming conditions are so set as to obtain such an aspect ratio that at the time of formation of the shield layer, the shield layer 16 is formed on the package side surfaces 23 but the thickness of the shield layer 16 formed on the groove bottom 43 between the packages is reduced. Note that for each of these conditions, experimentally, empirically or theoretically obtained values are set.
  • the control of the aspect ratio is carried out mainly by varying the opposing spacing X mm between the vertical surfaces 26 and the depth Y mm of the shallow grooves 42 of the protective tape 41 in aligning on the protective tape 41 .
  • the aspect ratio set to be high on the vertical surface 26 side it is ensured that the shield layer 16 is formed in an appropriate thickness on the inclined surfaces 25 and on the upper side of the vertical surfaces 26 where the influence of the aspect ratio is slight, whereas the shield layer 16 is formed in a thin form at the lower side of the vertical surfaces 26 and on the groove bottoms 43 where the influence of the aspect ratio is heavy.
  • the shield layer 16 since the vertical surfaces 26 of the semiconductor package 10 protrude into the inside of the shallow groove 42 , the shield layer 16 is separated between the vertical surface 26 and the shallow groove 42 . Therefore, generation of burs upon picking-up of the semiconductor package 10 is restrained.
  • the ground line 17 of the wiring board 11 is exposed to the exterior at the lower side of the inclined surfaces 25 of the package side surfaces 23 . Since the shield layer 16 is formed in an appropriate thickness at the lower side of the inclined surfaces 25 and the shield layer 16 is connected to the ground line 17 , electromagnetic noises generated in the semiconductor package 10 are released out of the semiconductor package 10 through the ground line 17 . Note that the shield layer 16 is thinned at the lower side of the vertical surfaces 26 of the semiconductor package 10 , the electromagnetic noises are cut by the multiplicity of wirings in the wiring board 11 . Therefore, leakage of electromagnetic noises to electronic parts in the surroundings of the semiconductor package 10 is prevented as a whole.
  • the shield layer 16 is a multilayer film having a thickness of several micrometers or more formed from at least one metal selected from among copper, titanium, nickel, gold and the like, and is formed by, for example, a sputtering method, an ion plating method, a spray coating method, a CVD method, an ink jet method, or a screen printing method.
  • the shield layer 16 may be formed by vacuum lamination in which a metallic film having the above-mentioned multilayer film is adhered to the package upper surface 22 and the package side surfaces 23 in a vacuum atmosphere. In this way, a semiconductor package 10 in which the package upper surface 22 and the package side surfaces 23 are covered with the shield layer 16 is manufactured.
  • a picking-up step is performed after the shield layer forming step is conducted.
  • the semiconductor package 10 formed with the shield layer 16 is picked up by a picker (not depicted) or the like.
  • deposition (build-up) of the shield layer 16 at the lower side of the vertical surfaces 26 of the package side surfaces 23 or on the groove bottoms 43 between the packages has been restrained.
  • the shield layer 16 is separated between the vertical surface 26 and the shallow groove 42 , the shield layer 16 is left in the shallow groove 42 and generation of burs is restrained at the time of picking-up of the semiconductor package 10 .
  • the side surface shape of the semiconductor package in the first and second embodiments is not limited to that in the above configuration.
  • the side surface shape of the semiconductor package may be any one such that the package interval between the adjacent semiconductor packages becomes smaller on route from the upper surface toward the lower surface of the semiconductor package.
  • Side surface shapes of semiconductor packages according to modifications will be described below.
  • FIGS. 7A to 7E depict an example of variation of the side surface shape of the semiconductor package.
  • a configuration has been adopted in which the package side, surface 23 is formed with the inclined surface 25 over the range of the resin layer 13 and the wiring board 11 , but this configuration is not limitative.
  • a configuration may be adopted in which the inclined surface 25 is formed only in the resin layer 13 . In this case, only the resin layer 13 where the consumption of a blade is comparatively slight is cut by the V blade, whereby consumption of the V blade can be restrained and blade life can be prolonged. Variation in shape due to consumption of the V blade is restrained, whereby angle management in regard of the V groove can be facilitated.
  • a configuration may be adopted in which the package side surface 23 is formed with a step 55 such that the outer shape size of the package becomes larger than that at the package upper surface 22 on route from the package upper surface 22 toward the lower surface.
  • the step 55 is formed in the package side surface 23 , by step cutting conducted using a large-width cutting blade and a small-width cutting blade.
  • the shield layer 16 is formed in an appropriate thickness at the upper-stage side of the package side surface 23 .
  • the aspect ratio between the packages is controlled at the lower-stage side of the package side surface 23 , whereby the shield layer 16 on the groove bottom 38 between the packages can be formed in a thinned form and generation of burrs can be restrained.
  • a configuration may be adopted in which the package side surface 23 is formed with a curved surface 56 such that the outer shape size of the package becomes larger than that at the package upper surface 22 on route from the package upper surface 22 toward the lower surface.
  • the curved surface 56 and a vertical surface 26 are formed in the package side surface 23 , by step cutting conducted using a large-width curved blade and a small-width cutting blade. Since the curved surface 56 intersects the forming direction (vertical direction) of the shield layer 16 , the shield layer 16 can be formed in an appropriate thickness on the curved surface 56 .
  • the aspect ratio between the packages is controlled at the vertical surface 26 side of the semiconductor package 10 , whereby the shield layer 16 on the groove bottom 38 between the packages can be formed in a thinned form and generation of burrs can be restrained.
  • FIG. 7E a configuration may be adopted in which the package side surface 23 is formed with inclined surfaces 58 and 59 such that the outer shape size of the package is maximized on route from the package upper surface 22 toward the lower surface.
  • cutting is conducted by a V blade from the upper side and the lower side, whereby the inclined surfaces 58 and 59 are formed in the package side surface 23 .
  • the package interval at the boundary position between the inclined surfaces 58 and 59 is made to be X mm, and the aspect ratio between the packages on the lower side of the boundary position is controlled, whereby the shield layer 16 can be formed in a thinned form at the lower side of the semiconductor package and generation of burs upon picking-up can be restrained.
  • FIG. 8 is a sectional schematic view of a specimen.
  • FIGS. 9A to 9D are diagrams depicting the relation between step coverage and aspect ratio, for specimens.
  • a shield layer was formed by an ion plating method under the conditions of 180° C. and 8 ⁇ 10 ⁇ 4 Pa.
  • the four kinds of specimens 61 there were prepared specimens 61 formed with rectangular grooves 63 having respective aspect ratios Y/X of 1, 2, 3 and 4, where X (mm) is the groove width and Y (mm) is the groove depth.
  • the thickness of the shield layer on the upper surface 64 the thickness of the shield layer at a V groove lower portion 65 , the thickness of the shield layer at a rectangular groove upper portion 66 , the thickness of the shield layer at a rectangular groove lower portion 67 , and the thickness of the shield layer on the groove bottom 68 were measured based on images observed under an electron microscope.
  • step coverages of the thickness of the shield layer at the V groove lower portion 65 , the rectangular groove upper portion 66 , the rectangular groove lower portion 67 , and the groove bottom 68 were summarized in FIGS. 9A to 9D .
  • the step coverage at each of specific portions namely, the V groove lower portion 65 , the rectangular groove upper portion 66 , the rectangular groove lower portion 67 and the groove bottom 68 is calculated from the thickness of the shield layer at the specific portion and the thickness of the shield layer on the upper surface from the following formula (1).
  • the aspect ratio is calculated from the width and the depth of the rectangular groove 63 from the following formula (2).
  • Step coverage ((Thickness at specific portion)/(Thickness on upper surface)) ⁇ 100[%] Formula (1)
  • Aspect ratio (Depth of rectangular groove)/(Width of rectangular groove) Formula (2)
  • the step coverage at the V groove lower portion 65 in relation to the upper surface 64 of the specimen 61 was maintained at approximately 90%, irrespectively of variations in the aspect ratio of the rectangular groove 63 .
  • the step coverage at the rectangular groove upper portion 66 in relation to the upper surface 64 of the specimen 61 was maintained at approximately 60%, irrespectively of variations in the aspect ratio of the rectangular groove 63 . Therefore, the thicknesses of the shield layer at the V groove lower portion 65 and the rectangular groove upper portion 66 were found to be independent from the aspect ratio of the rectangular groove 63 .
  • the step coverage at the rectangular groove lower portion 67 in relation to the upper surface 64 for the specimen 61 was maintained at approximately 60% when the aspect ratio of the rectangular groove 63 was not more than 2, but the step coverage was lowered to approximately 35% when the aspect ratio was increased to 4.
  • the step coverage at the groove bottom 68 in relation to the upper surface 64 of the specimen 61 was decreased with an increase in the aspect ratio of the rectangular groove 63 , and the step coverage was lowered to approximately 40% when the aspect ratio was increased to 4. Therefore, the thicknesses of the shield layer at the rectangular groove lower portion 67 and the groove bottom 68 were found to be heavily dependent on the aspect ratio of the rectangular groove 63 .
  • a semiconductor package in which one semiconductor chip is mounted on a wiring board has been described as an example in the first and second embodiments, this configuration is not restrictive.
  • a semiconductor package in which a plurality of semiconductor chips are mounted on a wiring board may be manufactured.
  • a semiconductor package 70 may be manufactured by mounting a plurality (for example, three) of semiconductor chips 72 a to 72 c on a wiring board 71 and shielding the semiconductor chips 72 a to 72 c collectively.
  • a semiconductor package substrate 75 is formed with V grooves on a package basis, and the semiconductor package substrate 75 is divided on a package basis.
  • the semiconductor chips 72 a to 72 c may have the same function or may have different functions.
  • a semiconductor package (SIP) 80 in which a plurality (for example, two) of semiconductor chips 82 a and 82 b are mounted on a wiring board 82 and the semiconductor chips 82 a and 82 b are individually shielded may be manufactured.
  • a semiconductor package substrate 80 is formed with V grooves on a chip basis, and the semiconductor package substrate is divided on a package basis.
  • a shield layer 86 is formed between the semiconductor chips 82 a and 82 b, whereby influences of electromagnetic noises between the semiconductor chips 82 a and 82 b can be prevented.
  • the semiconductor chips 82 a and 82 b may have the same function or may have different functions.
  • V grooves may be formed in a semiconductor package substrate 15 by use of an ordinary cutting blade 91 as a processing tool.
  • cutting is conducted with the cutting blade 91 inclined at a predetermined angle to one side relative to a vertical plane P on a division line of the semiconductor package substrate 15 , after which cutting is conducted with the cutting blade 91 inclined at the predetermined angle to the other side relative to the vertical plane P.
  • an upper surface of the semiconductor package substrate 15 is cut away in a V shape by the cutting blade 91 , and the V groove is formed along the division line.
  • V grooves may be formed in a semiconductor package substrate 15 by use of a processing head 93 for laser ablation as a processing tool.
  • ablation processing is conducted with the processing head 93 inclined at a predetermined angle to one side relative to a vertical plane P on a division line of the semiconductor package substrate 15 , after which ablation processing is conducted with the processing head 93 inclined at the predetermined angle to the other side relative to the vertical plane P.
  • An upper surface of the semiconductor package substrate 15 is cut away in a V shape by a laser beam such as to be absorbed in the semiconductor package substrate 15 , and the V groove is formed along the division line.
  • laser ablation refers to a phenomenon in which when the irradiation intensity of a laser beam reaches or exceeds a predetermined processing threshold, the laser beam is converted into electronic, thermal, optical and kinetic energy at the surface of a solid, with the result that neutral atoms, molecules, positive or negative ions, radicals, clusters, electrons and/or light is released in an explosive manner, whereby the surface of the solid is etched.
  • V grooves may be formed in a semiconductor package substrate 15 by use of a profiler 95 as a processing tool.
  • the profiler 35 is configured by electrodeposition of an abrasive grain layer 97 of diamond abrasive grains on a substantially V-shaped processing surface of an aluminum base member 96 .
  • the profiler 95 is less susceptible to consumption and can retain the V shape for a long time, as compared to a V blade.
  • the processing head for laser processing or the profiler may be used as a processing tool, at the time of forming grooves in a package substrate or dividing the package substrate.
  • a semiconductor package 89 may adopt flip chip bonding in which a semiconductor chip 12 is directly connected to electrodes of a wiring board 11 .
  • the formation of V grooves, in the semiconductor package substrate and the division of the semiconductor package substrate may be carried out by use of the same apparatus or may be performed by use of different apparatuses.
  • the division of the semiconductor package substrate has been conducted using a cutting blade in the first and second embodiments described above, this configuration is not limitative.
  • the division of the semiconductor package substrate need only be division of the semiconductor package substrate into individual semiconductor packages; for example, the semiconductor package substrate may be divided into individual semiconductor packages by ablation processing.
  • the groove forming step has been cutting in to an intermediate position of thickness of the wiring board by a processing tool in the first embodiment above, this configuration is not restrictive.
  • the groove forming step need only be cutting in at least to an intermediate position of thickness of the resin layer by a processing tool.
  • the adhesive tape has been mentioned as an example of the support member in the first embodiment above, this configuration is not limitative.
  • the support member need only be a member that supports the semiconductor package substrate, and may be composed of a substrate, for example. Therefore, in the adhering step, a configuration in which the wiring board side of the semiconductor package substrate is adhered to the adhesive tape attached to the ring frame is not restrictive, and a configuration may be adopted in which the wiring board side of the semiconductor package substrate is adhered to a substrate through an adhesive layer.
  • the semiconductor package aligning step has consisted in aligning the semiconductor packages on the protective tape or holding jig formed with the shallow grooves in the second embodiment above, this configuration is not limitative.
  • the semiconductor package aligning step may consist in aligning the semiconductor packages on a flat protective tape or holding jig that is not formed with shallow grooves. In this case, the aspect ratio between the packages is controlled according to the depth from the inclination or step of the semiconductor package to the holding surface of the protective tape or holding jig.
  • the protective tape has been mentioned as an example of the support member in the second embodiment above, this configuration is not restrictive.
  • the support member need only be a member that supports the semiconductor packages through an adhesive layer, and may be composed of a substrate, for example. This substrate may or may not be formed with shallow grooves.
  • a configuration in which the semiconductor packages are aligned on a protective tape or holding jig is not limitative, and the semiconductor packages may be aligned on a substrate in the state of being fixed with a wax.
  • the semiconductor package is used for portable communication apparatuses such as mobile phones is not restrictive, and the semiconductor package may be used for such electronic apparatuses as cameras.
  • the embodiments and modifications have been described above, other embodiments of the present invention include those obtained by combining, entirely or partly, the above embodiments and/or modifications.
  • the embodiment of the present invention is not limited to the above-described embodiments and modifications, and various changes, replacements and modifications may be made without departing from the gist of the technical thought of the invention. Furthermore, if the technical thought of the present invention can be realized in a different manner, owing to the progress of technology or by other derived technology, the present invention may be carried out by the different method.
  • the present invention is applicable also to a method of manufacturing other package parts in which a shield layer having a predetermined film thickness is formed.
  • the present invention has an effect to make it possible to restrain generation of burs upon picking-up of the semiconductor package, and is particularly useful as a method of manufacturing a semiconductor package for use in portable communication apparatuses.

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