JP2018182236A - 半導体パッケージの製造方法 - Google Patents
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Abstract
Description
式(1)
step coverage=(特定部分厚/上面厚)×100[%]
式(2)
アスペクト比=矩形溝の溝幅/矩形溝の深さ
11 配線基板
12 半導体チップ
13 樹脂層(封止剤)
15 半導体パッケージ基板
16 シールド層
22 パッケージ上面(封止剤上面)
23 パッケージ側面(側面)
24 封止剤
25 斜面(側面の傾斜)
28 Vブレード(加工工具)
29 V溝(溝)
35 粘着テープ
36 切削ブレード
37 矩形溝
38 矩形溝の溝底
41 保護テープ
42 浅溝(溝)
55 段差
Claims (3)
- 交差する分割予定ラインによって区画された配線基板上の複数領域に複数の半導体チップがマウントされて封止剤により封止された半導体パッケージ基板を該分割予定ラインに沿って分割された半導体パッケージを製造する半導体パッケージの製造方法であって、
該半導体パッケージ基板の該配線基板側を粘着層を有する支持部材上に貼着する貼着工程と、
該貼着工程を実施した後に、該封止剤側から該分割予定ラインに沿って加工工具で少なくとも該封止剤の途中まで切り込み、該封止剤の少なくとも上面が第1の幅である溝を形成する溝形成工程と、
該溝形成工程を実施した後に、該封止剤側から該第1の幅よりも細い第2の幅の切削ブレードを使用して該溝に沿って該支持部材の途中まで切り込み、隣接する該半導体パッケージ間が所定間隔Xmm離間するように分割する分割工程と、
該分割工程を実施した後に、該封止剤側上方から導電性材料で、該半導体パッケージの側面及び該封止剤上面にシールド層を形成するシールド層形成工程と、
該シールド層形成工程を実施した後に、該シールド層が形成された半導体パッケージをピックアップするピックアップ工程と、を備え、
該第1の幅と該第2の幅は、分割後の各半導体パッケージの該封止剤上面から下面に向かう途中で、該封止剤上面よりも外形サイズが大きくなるように各側面に傾斜又は段差が生じる幅に設定され、
該半導体パッケージの該傾斜又該段差の下端から該支持部材に切り込んだ溝底までの側面長さをYmmとした際に、該シールド層形成時に該側面には形成されるが該半導体パッケージ間の該溝底に形成される量が低減するアスペクト比Y/Xになるように、該第1の幅、該第2の幅、該側面長さYmm及びシールド層形成条件が設定されること、を特徴とする半導体パッケージの製造方法。 - 交差する分割予定ラインによって区画された配線基板上の複数領域に複数の半導体チップがマウントされて封止剤により封止された半導体パッケージ基板を該分割予定ラインに沿って分割された半導体パッケージを製造する半導体パッケージの製造方法であって、
該半導体パッケージ基板を該分割予定ラインに沿って分割すると共に、各半導体パッケージの該封止剤上面から下面に向かう途中で、該封止剤上面よりも外形サイズが大きくなるように各側面に傾斜又は段差を形成する分割工程と、
該分割された個々の半導体パッケージの隣接する該半導体パッケージ同士を所定間隔Xmm離間させて整列して、該配線基板側を保持ジグに保持又は支持部材に貼着する半導体パッケージ整列工程と、
該封止剤側上方から導電性材料で、該半導体パッケージの側面及び該封止剤上面にシールド層を形成するシールド層形成工程と、
該シールド層形成工程を実施した後に、該シールド層が形成された半導体パッケージをピックアップするピックアップ工程と、を備え、
該半導体パッケージの該傾斜又は該段差の下端から該保持ジグ又は該支持部材までの側面長さをYmmとした際に、該シールド層形成時に該側面には形成されるが該半導体パッケージ間底面に形成される量が低減するアスペクト比Y/Xになるように、該傾斜又は該段差、該側面長さYmm、該所定間隔Xmm及びシールド層形成条件が設定されること、を特徴とする半導体パッケージの製造方法。 - 該半導体パッケージ整列工程では、該保持ジグ又は該支持部材の保持面を格子状の溝で区画した各領域に該半導体パッケージが載置され、隣接する該半導体パッケージ同士が該所定間隔Xmm離間して整列し、
該溝の溝幅が該半導体パッケージ同士の該所定間隔Xmmよりも大きく形成されていることを特徴とする請求項2に記載の半導体パッケージの製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017084105A JP6974960B2 (ja) | 2017-04-21 | 2017-04-21 | 半導体パッケージの製造方法 |
TW107108534A TWI749188B (zh) | 2017-04-21 | 2018-03-14 | 半導體封裝之製造方法 |
KR1020180039326A KR102311487B1 (ko) | 2017-04-21 | 2018-04-04 | 반도체 패키지의 제조 방법 |
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JP7207927B2 (ja) * | 2018-09-28 | 2023-01-18 | 株式会社ディスコ | 半導体パッケージの製造方法 |
US11355451B2 (en) | 2019-08-28 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11004801B2 (en) | 2019-08-28 | 2021-05-11 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US20230170245A1 (en) * | 2021-12-01 | 2023-06-01 | STATS ChipPAC Pte. Ltd. | Semiconductor Device and Method for Reducing Metal Burrs Using Laser Grooving |
CN114622164B (zh) * | 2022-03-10 | 2023-10-20 | 江苏长电科技股份有限公司 | 无毛刺镀膜器件制备方法及镀膜贴合结构、器件拾取结构 |
CN114465595B (zh) * | 2022-04-12 | 2022-08-16 | 深圳新声半导体有限公司 | 一种体声波滤波器芯片的封装结构和方法 |
CN117611952B (zh) * | 2024-01-17 | 2024-04-12 | 南京阿吉必信息科技有限公司 | 一种led封装结构的制备方法 |
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US10497623B2 (en) | 2019-12-03 |
JP6974960B2 (ja) | 2021-12-01 |
CN108735668B (zh) | 2023-09-12 |
DE102018205895A1 (de) | 2018-10-25 |
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