US10403703B2 - Display device and electronic device - Google Patents

Display device and electronic device Download PDF

Info

Publication number
US10403703B2
US10403703B2 US14/741,873 US201514741873A US10403703B2 US 10403703 B2 US10403703 B2 US 10403703B2 US 201514741873 A US201514741873 A US 201514741873A US 10403703 B2 US10403703 B2 US 10403703B2
Authority
US
United States
Prior art keywords
electrode
layer
substrate
light
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US14/741,873
Other languages
English (en)
Other versions
US20150372065A1 (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMAZAKI, SHUNPEI
Publication of US20150372065A1 publication Critical patent/US20150372065A1/en
Application granted granted Critical
Publication of US10403703B2 publication Critical patent/US10403703B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H01L27/3276—
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H01L2251/5315—
    • H01L2251/5338—
    • H01L27/322—
    • H01L27/323—
    • H01L51/003—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

Definitions

  • the present invention relates to a display device.
  • the present invention also relates to a method of manufacturing the display device.
  • One embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.
  • the term display device refers to a device including a display element.
  • the display device may include a driver circuit driving a plurality of pixels, a control circuit, a power supply circuit, a signal generation circuit, or the like.
  • the term display device may refer to, for example, a module to which a connector such as a flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP) is attached, a module in which the end of TAB tape or a TCP is provided with a printed wiring board, and a module in which an integrated circuit (IC) is directly mounted on the display element by a chip on glass (COG) method.
  • FPC flexible printed circuit
  • TAB tape automated bonding
  • TCP tape carrier package
  • semiconductor device in this specification and the like refers to all the devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor or a diode and a semiconductor circuit are semiconductor devices.
  • a display device, a light-emitting device, a lighting device, an electro-optical device, an electronic device, and the like may include a semiconductor element or a semiconductor circuit. Therefore, a display device, a light-emitting device, a lighting device, an electro-optical device, an electronic device, and the like may include a semiconductor device.
  • Flat panel displays widely used for TVs, portable terminals, and the like are expected to be used in watches, and car electronics, in particular, instrument panels and the like, which meet new needs.
  • Patent Documents 1 to 3 Display devices including non-rectangular display regions are disclosed in Patent Documents 1 to 3 and Non-Patent Document 1, for example.
  • the display device needs to include an input terminal region for inputting an external signal, such as an image signal, into the display device.
  • the input terminal region is usually provided in a frame region outside the display region and thus requires a frame region with a certain width outside the display region, which have prevented the maximization of the display region.
  • an object of one embodiment of the present invention is to provide a display device having a reduced frame width and a shape that is not significantly different from the shape of a display region included in the display device regardless of whether the display region has a rectangular or non-rectangular shape. Another object is to provide a display device in which a display region can be maximized. Another object is to provide a display device that can be easily downsized. Another object of one embodiment of the present invention is to provide a display device having a novel structure.
  • One embodiment of the present invention is a display device comprising a display region and a terminal electrode.
  • the terminal electrode overlaps with the display region.
  • the display region is capable of displaying an image on one surface of the display region.
  • the terminal electrode is electrically connected to an external electrode through the other surface of the display region.
  • Another embodiment of the present invention is a display device comprising a first substrate, a second substrate, a light-emitting element, and, a first electrode.
  • the first electrode is provided above the first substrate.
  • the light-emitting element is provided above the first electrode.
  • the second substrate is provided above the light-emitting element. Light emitted from the light-emitting element exits through the second substrate.
  • the first electrode is electrically connected to a second electrode.
  • first substrate and the second substrate each have flexibility.
  • a high degree of flexibility of the shape of a display region and minimization of the external shape of a display device with a reduced frame width can be achieved; thus, a display device with less limitation of design flexibility can be provided.
  • a display device having a reduced frame width and a shape that is not significantly different from the shape of a display region included in the display device can be provided regardless of whether the display region has a rectangular or non-rectangular shape.
  • a display device in which a display region can be maximized can be provided.
  • a display device that can be easily downsized can be provided.
  • a novel display device can be provided.
  • FIGS. 1A and 1B are a perspective view and a cross-sectional view illustrating one mode of a display device
  • FIGS. 2A and 2B are a perspective view and a cross-sectional view illustrating one mode of a display device
  • FIGS. 3A to 3D illustrate a manufacturing process of one mode of a display device
  • FIGS. 4A to 4C illustrate a manufacturing process of one mode of a display device
  • FIGS. 5A and 5B illustrate a manufacturing process of one mode of a display device
  • FIGS. 6A to 6E illustrate a manufacturing process of one mode of a display device
  • FIGS. 7A and 7B illustrate a manufacturing process of one mode of a display device
  • FIGS. 8A and 8B illustrate a manufacturing process of one mode of a display device
  • FIGS. 9A and 9B illustrate a manufacturing process of one mode of a display device
  • FIGS. 10A and 10B illustrate a manufacturing process of one mode of a display device
  • FIGS. 11A and 11B are a perspective view and a cross-sectional view illustrating one mode of a display device
  • FIGS. 12A and 12B each illustrate an example of a pixel structure of one mode of a display device
  • FIGS. 13A and 13B each illustrate an example of a pixel structure of one mode of a display device
  • FIGS. 14A to 14C are a block diagram and circuit diagrams illustrating one mode of a display device
  • FIGS. 15 A 1 , 15 A 2 , 15 B 1 , 15 B 2 , 15 C 1 , and 15 C 2 are each a cross-sectional view of one mode of a transistor
  • FIGS. 16A to 16C are a top view and cross-sectional views illustrating one mode of a transistor
  • FIGS. 17 A 1 , 17 A 2 , 17 A 3 , 17 B 1 , and 17 B 2 are each a cross-sectional view of one mode of transistors
  • FIGS. 18A to 18C are a top view and cross-sectional views illustrating one mode of a transistor
  • FIGS. 19A and 19B each illustrate a structure example of a light-emitting element
  • FIGS. 20A to 20C each illustrate one mode of a display device
  • FIGS. 21A to 21D each illustrate an example of an electronic device
  • FIGS. 22A to 22D are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of the CAAC-OS;
  • FIGS. 23A to 23D are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS
  • FIGS. 24A to 24C show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD;
  • FIGS. 25A and 25B show electron diffraction patterns of a CAAC-OS
  • FIG. 26 shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation
  • FIGS. 27A and 27B are schematic diagrams illustrating deposition models of a CAAC-OS and an nc-OS;
  • FIGS. 28A to 28C illustrate an InGaZnO 4 crystal and a pellet
  • FIGS. 29A to 29D are schematic views showing a deposition model of a CAAC-OS.
  • an “electrode” or a “wiring” does not limit a function of a component.
  • an “electrode” is used as part of a “wiring” in some cases, and vice versa.
  • the term “electrode” or “wiring” can also mean a combination of a plurality of “electrodes” and “wirings” formed in an integrated manner.
  • an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, another element may be provided between elements having a connection relation illustrated in drawings and texts, without limitation on a predetermined connection relation, for example, the connection relation illustrated in the drawings and the texts.
  • X and Y each denote an object (e.g., a device, an element, a circuit, a line, an electrode, a terminal, a conductive film, a layer, or the like).
  • Examples of the case where X and Y are directly connected include the case where an element that allows an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load) is not connected between X and Y, and the case where X and Y are connected without the element that allows the electrical connection between X and Y provided therebetween.
  • an element that allows an electrical connection between X and Y e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load
  • one or more elements that enable electrical connection between X and Y can be connected between X and Y.
  • a switch is controlled to be on or off. That is, a switch is conducting or not conducting (is turned on or off) to determine whether current flows therethrough or not.
  • the switch has a function of selecting and changing a current path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • one or more circuits that enable functional connection between X and Y can be connected between X and Y
  • a logic circuit such as an inverter, a NAND circuit, or a NOR circuit
  • a signal converter circuit such as a DA converter circuit, an AD converter circuit, or a gamma correction circuit
  • a potential level converter circuit such as a power supply circuit (e.g., a dc-dc converter, a step-up dc-dc converter, or a step-down dc-dc converter) or a level shifter circuit for changing the potential level of a signal
  • a voltage source e.g., a dc-dc converter, a step-up dc-dc converter, or a step-down dc-dc converter
  • an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit
  • X and Y are functionally connected even if another circuit is provided between X and Y.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, in this specification and the like, the explicit description “X and Y are electrically connected” is the same as the description “X and Y are connected”.
  • a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z 1 and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z 2
  • a source (or a first terminal or the like) of a transistor is directly connected to one part of Z 1 and another part of Z 1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to one part of Z 2 and another part of Z 2 is directly connected to Y
  • the expressions include, for example, “X, Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, “a source (or a first terminal or the like) of a transistor is electrically connected to X a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or
  • a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor,Z 1 is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, andZ 2 is on the third connection path”.
  • a source (or a first terminal or the like) of a transistor is electrically connected to X through at leastZ 1 on a first connection path, the first connection path does not include a second connection path, the second connection path includes a connection path through the transistor, a drain (or a second terminal or the like) of the transistor is electrically connected to Y through at leastZ 2 on a third connection path, and the third connection path does not include the second connection path”.
  • Still another example of the expression is “source (or a first terminal or the like) of a transistor is electrically connected to X through at leastZ 1 on a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at leastZ 2 on a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor”.
  • the connection path in a circuit structure is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.
  • X, Y, Z 1 , and Z 2 each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, and a layer).
  • one component has functions of a plurality of components in some cases.
  • one conductive film functions as the wiring and the electrode.
  • electrical connection in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
  • a transistor can be formed using a variety of substrates.
  • the type of a substrate is not limited to a certain type.
  • a semiconductor substrate e.g., a single crystal substrate or a silicon substrate
  • SOI substrate a glass substrate
  • quartz substrate a quartz substrate
  • plastic substrate a metal substrate
  • stainless steel substrate a substrate including stainless steel foil
  • tungsten substrate a substrate including tungsten foil
  • flexible substrate an attachment film, paper including a fibrous material, a base material film, or the like
  • an attachment film paper including a fibrous material, a base material film, or the like
  • a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, soda lime glass substrate, and the like can be given.
  • a flexible synthetic resin such as plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES), or acrylic can be used, for example.
  • the material for an attachment film include vinyl such as polyvinyl fluoride or vinyl chloride, polypropylene and polyester.
  • polyester, polyamide, polyimide, an inorganic vapor deposition film, paper, or the like can be used, for example.
  • a transistor when a transistor is formed using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to form a transistor with few variations in characteristics, size, shape, or the like and with high current supply capability and a small size.
  • power consumption of the circuit can be reduced or the circuit can be highly integrated.
  • a transistor may be formed using one substrate, and then the transistor may be transferred to another substrate.
  • a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupra, rayon, or regenerated polyester), or the like), a leather substrate, a rubber substrate, or the like can be used as a substrate to which the transistor is transferred.
  • a transistor with excellent properties or a transistor with low power consumption can be formed, a device with high durability can be formed, heat resistance can be provided, or reduction in weight or thickness can be achieved.
  • a top view also referred to as a plan view
  • some components might not be illustrated for easy understanding.
  • an illustration of a hidden line or the like is partly omitted.
  • electrode B over insulating layer A does not necessarily mean that the electrode B is on and in direct contact with the insulating layer A and can mean the case where another component is provided between the insulating layer A and the electrode B.
  • Source and drain Functions of a source and a drain might be switched depending on operation conditions, for example, when a transistor having opposite polarity is employed or the direction of current flow is changed in circuit operation. Thus, it is difficult to define which is a source or a drain. Accordingly, the terms “source” and “drain” can be switched in this specification.
  • the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to ⁇ 10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to ⁇ 5° and less than or equal to 5°.
  • the term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to ⁇ 30° and less than or equal to 30°.
  • the term “perpendicular” or “orthogonal” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.
  • the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.
  • a voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a source potential or a ground potential (a GND potential)).
  • a reference potential e.g., a source potential or a ground potential (a GND potential)
  • a voltage can be referred to as a potential and vice versa.
  • an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor.
  • an element with a concentration lower than 0.1 atomic % can be regarded as an impurity.
  • the density of states (DOS) in a semiconductor may be increased, the carrier mobility may be decreased, or the crystallinity may be decreased, for example.
  • examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the semiconductor; specifically, there are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example.
  • oxygen vacancies may be formed by entry of impurities such as hydrogen.
  • impurities such as hydrogen.
  • examples of an impurity which changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
  • ordinal numbers such as “first” and “second” in this specification and the like are used in order to avoid confusion among components and do not denote the priority or the order such as the order of steps or the stacking order.
  • a term without an ordinal number in this specification and the like might be provided with an ordinal number in a claim in order to avoid confusion among components.
  • a term with an ordinal number in this specification and the like might be provided with a different ordinal number in a claim.
  • a term with an ordinal number in this specification and the like might not be provided with any ordinal number in a claim.
  • the channel length refers to, for example, a distance, observed in a top view of a transistor, between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when the transistor is on) and a gate electrode overlap with each other or a region where a channel is formed.
  • channel lengths are not necessarily the same in all regions.
  • the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed.
  • channel widths are not necessarily the same in all regions.
  • the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, a channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • a channel width in a region where a channel is formed actually (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases.
  • an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases.
  • the proportion of a channel region formed in a side surface of a semiconductor is higher than the proportion of a channel region formed in a top surface of a semiconductor in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.
  • an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known as an assumption condition. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.
  • an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases.
  • SCW surrounded channel width
  • channel width in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by analyzing a cross-sectional TEM image and the like.
  • a surrounded channel width might be used for the calculation.
  • a value might be different from one calculated by using an effective channel width.
  • trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.
  • FIG. 1A is a perspective view of the display device 100 to which an external electrode 124 is connected.
  • the external shape of the display device 100 illustrated in FIG. 1A is a non-rectangular shape.
  • the display device 100 includes a display region 131 that has a non-rectangular shape.
  • FIG. 1B is a cross-sectional view taken along the dash-dot line A 1 -A 2 in FIG. 1A .
  • the display device 100 disclosed in this specification is a display device in which a light-emitting element is used as a display element.
  • a display device having a top-emission structure is described as an example.
  • the display device 100 described in this embodiment includes the display region 131 .
  • the display device 100 also includes a terminal electrode 216 and a light-emitting element 125 including an electrode 115 , an EL layer 117 , and an electrode 118 .
  • a plurality of light-emitting elements 125 are formed in the display region 131 .
  • a transistor 232 which controls the amount of light emitted from each of the light-emitting elements 125 is connected to the light-emitting element 125 .
  • the transistor 232 is formed over a substrate 111 with a bonding layer 112 , insulating layers 221 , 223 , and 205 positioned therebetween.
  • the terminal electrode 216 is formed between the insulating layers 221 and 223 .
  • the terminal electrode 216 overlaps with an opening 132 passing through the substrate 111 , the bonding layer 112 , and the insulating layer 221 .
  • the terminal electrode 216 is electrically connected to the external electrode 124 through an anisotropic conductive connection layer 138 in the opening 132 .
  • the terminal electrode 216 is electrically or functionally connected to the transistor 232 .
  • the terminal electrode 216 may be connected to a driver circuit such that a signal supplied to the terminal electrode 216 can be supplied to the transistor 232 through the driver circuit.
  • the driver circuit is an electrical circuit having a function of determining which light-emitting element 125 in the display region 131 is supplied with the signal, and may be provided in the display device 100 at the same time as when the transistor 232 is formed in the display device 100 .
  • the transistor 232 includes an electrode 206 , an insulating layer 207 , a semiconductor layer 208 , an electrode 214 , and an electrode 215 .
  • the electrode 206 can function as a gate electrode.
  • the insulating layer 207 can function as a gate insulating layer.
  • the electrode 214 and the electrode 215 can function as a source electrode and a drain electrode.
  • a wiring 219 is formed in the same layer as the electrodes 214 and 215 .
  • an insulating layer 210 is formed over the transistor 232
  • an insulating layer 211 is formed over the insulating layer 210
  • an insulating layer 212 is formed over the insulating layer 211 .
  • the electrode 115 is formed over the insulating layer 211 .
  • the electrode 115 is electrically connected to the electrode 215 through an opening formed in the insulating layers 210 to 212 .
  • a partition 114 is formed over the electrode 115 , and the EL layer 117 and the electrode 118 are formed over the electrode 115 and the partition 114 .
  • One side of a substrate 121 is provided with an insulating layer 129 , a light-blocking layer 264 , coloring layers 266 , and an overcoat layer 268 with a bonding layer 122 positioned therebetween.
  • the substrate 111 and the substrate 121 are attached with a bonding layer 120 such that the one side of the substrate 121 faces the side of the substrate 111 which is provided with the light-emitting element 125 .
  • the insulating layer 205 functions as a base layer and can prevent or reduce diffusion of moisture and impurity elements from the substrate 111 , the bonding layer 112 , or the like to the transistor or the light-emitting element.
  • the insulating layer 129 functions as a base layer and can prevent or reduce diffusion of moisture and impurity elements from the substrate 121 , the bonding layer 122 , or the like to the transistor or the light-emitting element.
  • the insulating layer 129 can be formed using a material and a method similar to those of the insulating layer 205 .
  • a flexible material such as an organic resin material, or the like can be used.
  • a material that transmits light emitted from the EL layer 117 is used for the substrate 111 .
  • a material that transmits light emitted from the EL layer 117 is used for the substrate 121 .
  • the display device 100 is a so-called bottom-emission display device or a dual-emission display device
  • a material that transmits light emitted from the EL layer 117 is used for the substrate 111 .
  • a material that transmits light emitted from the EL layer 117 is used for the substrate 121 .
  • the substrate 111 and the substrate 121 be formed using the same material and have the same thickness. However, depending on the purpose, the substrates 111 and 121 may be formed using different materials or have different thicknesses.
  • Examples of materials that have flexibility and transmit visible light which can be used for the substrates 111 and 121 , include a polyethylene terephthalate resin, a polyethylene naphthalate resin, a polyacrylonitrile resin, a polyimide resin, a polymethylmethacrylate resin, a polycarbonate resin, a polyethersulfone resin, a polyamide resin, a cycloolefin resin, a polystyrene resin, a polyamide imide resin, a polyvinylchloride resin, and the like.
  • a non-light-transmitting substrate may be used.
  • aluminum or the like may be used for the substrate 121 or the substrate 111 .
  • the thermal expansion coefficients of the substrate 121 and the substrate 111 are preferably less than or equal to 30 ppm/K, or further preferably less than or equal to 10 ppm/K.
  • a protective film having low water permeability may be formed in advance; examples of the protective film include a film containing nitrogen and silicon such as a silicon nitride film or a silicon oxynitride film and a film containing nitrogen and aluminum such as an aluminum nitride film.
  • an organic resin also called prepreg
  • a display device that does not break easily, a lightweight display device, or an easily bendable display device can be provided.
  • FIG. 2A illustrates the display device 100 a having a rectangular external shape.
  • FIG. 2A is a perspective view of the display device 100 a having a rectangular shape to which the external electrode 124 is connected.
  • FIG. 2B is a cross-sectional view taken along the dash-dot line A 3 -A 4 in FIG. 2A . Note that components identical with those of the display device 100 illustrated in FIG. 1A are not described here.
  • the display device 100 a illustrated in FIG. 2A includes the display region 131 having a rectangular shape. Outside the display region 131 , a driver circuit 133 , a driver circuit 142 a , and a driver circuit 142 b are provided. Note that in this specification and the like, one or more of the driver circuits 133 , 142 a , and 142 b may be simply referred to as a driver circuit or a peripheral driver circuit.
  • the driver circuits 133 , 142 a , and 142 b each include a plurality of transistors 252 .
  • the driver circuits 133 , 142 a , and 142 b each have a function of determining which light-emitting element 125 in the display region 131 is supplied with a signal through the external electrode 124 .
  • the transistors 252 and 232 can be formed through the same process. Note that the structures of the transistors 232 and 252 may be the same or different.
  • the light-blocking layer 264 , the coloring layers 266 , or the overcoat layer 268 may be provided in the region(s) of the substrate 121 which overlap(s) with the driver circuit 133 , the driver circuit 142 a , and/or the driver circuit 142 b .
  • the light-blocking layer 264 and the overcoat layer 268 are provided so as to overlap with the driver circuit 133 in FIG. 2B .
  • the light-blocking layer 264 provided to overlap with the transistor 252 can reduce the effect of the entrance of external light which changes characteristics of the transistor 252 .
  • the electrode 216 and the opening 132 may be provided to overlap with the driver circuit such that the terminal electrode 216 can be electrically connected to the external electrode 124 through the anisotropic conductive connection layer 138 .
  • the electrode 216 and the opening 132 are provided to overlap with the driver circuit 133 such that the terminal electrode 216 can be electrically connected to the external electrode 124 through the anisotropic conductive connection layer 138 .
  • the terminal electrode 216 is electrically connected to one of a source electrode and a drain electrode of the transistor 252 through an electrode 224 in an opening formed by removal of part of the insulating layers 205 and 223 .
  • a driver circuit can be provided in a display device even when the external shape of the display device or the shape of a display region is not rectangular.
  • FIGS. 3A to 3D , FIGS. 4A to 4C , FIGS. 5A and 5B , FIGS. 6A to 6E , FIGS. 7A and 7B , FIGS. 8A and 8B , and FIGS. 9A and 9B correspond to cross-sectional views taken along the dash-dot line A 1 -A 2 in FIG. 1A .
  • a peeling layer 113 is formed over a substrate 101 (see FIG. 3A ).
  • a substrate 101 a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used.
  • a plastic substrate having heat resistance to the processing temperature in this embodiment may be used.
  • the glass substrate for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. Note that when the glass substrate contains a large amount of barium oxide (BaO), the glass substrate can be heat-resistant and more practical. Alternatively, crystallized glass or the like can be used.
  • a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used.
  • barium oxide BaO
  • crystallized glass or the like can be used.
  • the peeling layer 113 can be formed using an element selected from tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, ruthenium, rhodium, palladium, osmium, iridium, and silicon; an alloy material containing any of the elements; or a compound material containing any of the elements.
  • the peeling layer 113 can also be formed to have a single-layer structure or a stacked-layer structure using any of the materials. Note that the crystalline structure of the peeling layer 113 may be amorphous, microcrystalline, or polycrystalline.
  • the peeling layer 113 can also be formed using a metal oxide such as aluminum oxide, gallium oxide, zinc oxide, titanium dioxide, indium oxide, indium tin oxide, indium zinc oxide, or InGaZnO (IGZO).
  • IGZO InGaZnO
  • the peeling layer 113 can be formed by a sputtering method, a CVD method, a coating method, a printing method, or the like.
  • the coating method includes a spin coating method, a droplet discharge method, and a dispensing method.
  • the peeling layer 113 has a single-layer structure
  • a material containing tungsten, a material containing molybdenum, or a material containing tungsten and molybdenum is preferably used.
  • an oxide or oxynitride of tungsten, an oxide or oxynitride of molybdenum, or an oxide or oxynitride of a material containing tungsten and molybdenum is preferably used.
  • the layer containing an oxide of tungsten may be formed as follows: the layer containing tungsten is formed first and then an oxide insulating layer is formed in contact therewith, so that the layer containing an oxide of tungsten is formed at the interface between the layer containing tungsten and the oxide insulating layer.
  • the layer containing an oxide of tungsten may be formed by performing thermal oxidation treatment, oxygen plasma treatment, treatment with a highly oxidizing solution such as ozone water, or the like on the surface of the layer containing tungsten.
  • a glass substrate is used as the substrate 101 .
  • a tungsten layer is formed over the substrate 101 by a sputtering method.
  • the insulating layer 221 is formed over the peeling layer 113 (see FIG. 3A ).
  • the insulating layer 221 is preferably formed using silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, or an insulating material containing oxygen such as aluminum nitride oxide.
  • the insulating layer 221 can be formed using a material not containing oxygen, such as silicon nitride or aluminum nitride.
  • the insulating layer 221 is preferably a single layer or a multilayer.
  • the insulating layer 221 may have, for example, a two-layer structure of silicon oxide and silicon nitride or a five-layer structure in which materials selected from the above materials are combined.
  • the insulating layer 221 can be formed by a sputtering method, a CVD method, a thermal oxidation method, a coating method, a printing method, or the like.
  • the thickness of the insulating layer 221 is greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm.
  • a stack of a 200-nm-thick silicon oxynitride film and a 50-nm-thick silicon nitride oxide film formed by a plasma CVD method is used as the insulating layer 221 .
  • the terminal electrode 216 is formed over the insulating layer 221 (see FIG. 3A ).
  • the terminal electrode 216 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing any of these metal elements in combination; or the like.
  • One or more metal elements selected from manganese and zirconium may be used.
  • the terminal electrode 216 may have a single-layer structure or a stacked structure of two or more layers.
  • Examples include a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked over a titanium film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked over a titanium film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like.
  • an alloy film or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
  • the terminal electrode 216 can also be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.
  • the terminal electrode 216 can have a stacked structure formed using the above-described light-transmitting conductive material and the above-described metal element.
  • a conductive film to be the terminal electrode 216 is stacked over the insulating layer 221 by a sputtering method, a CVD method, an evaporation method, or the like, and a resist mask is formed over the conductive film by a photolithography process. Then, part of the conductive film is etched using the resist mask to form the terminal electrode 216 . At the same time, a wiring and another electrode can be formed.
  • the conductive film may be etched by a dry etching method, a wet etching method, or both a dry etching method and a wet etching method. Note that in the case where the conductive film is etched by a dry etching method, ashing treatment may be performed before the resist mask is removed, whereby the resist mask can be easily removed using a stripper.
  • terminal electrode 216 may be formed by an electrolytic plating method, a printing method, an inkjet method, or the like instead of the above formation method.
  • the thickness of the terminal electrode 216 is greater than or equal to 5 nm and less than or equal to 500 nm, preferably greater than or equal to 10 nm and less than or equal to 300 nm, more preferably greater than or equal to 10 nm and less than or equal to 200 nm.
  • the insulating layer 223 is formed over the terminal electrode 216 (see FIG. 3A ).
  • the insulating layer 223 is preferably formed using a single layer or a multilayer of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or the like.
  • the insulating layer 223 may be a stacked layer of silicon oxide and silicon nitride.
  • the insulating layer 223 can be formed by a sputtering method, a CVD method, a thermal oxidation method, a coating method, a printing method, or the like.
  • Planarization treatment may be performed on the insulating layer 223 to reduce unevenness of a surface.
  • the planarization treatment may be, but not particularly limited to, polishing treatment (e.g., chemical mechanical polishing (CMP)) or dry etching treatment.
  • polishing treatment e.g., chemical mechanical polishing (CMP)
  • dry etching treatment e.g., dry etching
  • the insulating layer 205 is formed as a base layer over the insulating layer 223 (see FIG. 3B ).
  • the insulating layer 205 is preferably formed as a single layer or a multilayer using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or the like.
  • the insulating layer 205 may have, for example, a two-layer structure of silicon oxide and silicon nitride or a five-layer structure in which materials selected from the above are combined.
  • the insulating layer 205 can be formed by a sputtering method, a CVD method, a thermal oxidation method, a coating method, a printing method, or the like.
  • the thickness of the insulating layer 205 is greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm.
  • the insulating layer 205 has a function of preventing or reducing diffusion of impurity elements from the substrate 101 , the peeling layer 113 , or the like. Even after the substrate 101 is replaced by the substrate 111 , the insulating layer 205 can prevent or reduce diffusion of impurity elements into the transistor 232 or the light-emitting element 125 from the substrate 111 , the bonding layer 112 , or the like.
  • a stacked film of a 200-nm-thick silicon oxynitride film and a 50-nm-thick silicon nitride oxide film is formed by a plasma CVD method.
  • the electrode 206 is formed over the insulating layer 205 (see FIG. 3B ).
  • the electrode 206 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing any of these metal elements in combination; or the like.
  • One or more metal elements selected from manganese and zirconium may be used.
  • the electrode 206 may have a single-layer structure or a stacked structure of two or more layers.
  • Examples include a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked over a titanium film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked over a titanium film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like.
  • an alloy film or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
  • the electrode 206 can be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible to have a stacked-layer structure formed using the above light-transmitting conductive material and the above metal element.
  • a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible to have a stacked-layer structure formed using the above light-transmitting conductive material and the above metal element.
  • a conductive film to be the electrode 206 is stacked over the insulating layer 205 by a sputtering method, a CVD method, an evaporation method, or the like, and a resist mask is formed over the conductive film by a photolithography process.
  • part of the conductive film to be the electrode 206 is etched with the use of the resist mask to form the electrode 206 .
  • a wiring and another electrode can be formed.
  • the conductive film may be etched by a dry etching method, a wet etching method, or both a dry etching method and a wet etching method. Note that in the case where the conductive film is etched by a dry etching method, ashing treatment may be performed before the resist mask is removed, whereby the resist mask can be easily removed using a stripper.
  • the electrode 206 may be formed by an electrolytic plating method, a printing method, an inkjet method, or the like instead of the above formation method.
  • the thickness of the electrode 206 is greater than or equal to 5 nm and less than or equal to 500 nm, preferably greater than or equal to 10 nm and less than or equal to 300 nm, further preferably greater than or equal to 10 nm and less than or equal to 200 nm.
  • the electrode 206 is formed using a light-blocking conductive material, external light can be prevented from reaching the semiconductor layer 208 from the electrode 206 side. As a result, a variation in electrical characteristics of the transistor due to light irradiation can be suppressed.
  • the insulating layer 207 is formed (see FIG. 3B ).
  • the insulating layer 207 is formed to have a single-layer structure or a stacked-layer structure using any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, a mixture of aluminum oxide and silicon oxide, hafnium oxide, gallium oxide, Ga—Zn-based metal oxide, and the like.
  • the insulating layer 207 can be formed using a high-k material such as hafnium silicate (HfSiO x ), hafnium silicate to which nitrogen is added (HfSi x O y N z ), hafnium aluminate to which nitrogen is added (HfAl x O y N z ), hafnium oxide, or yttrium oxide, so that gate leakage current of the transistor can be reduced.
  • a stacked layer of silicon oxynitride and hafnium oxide may be used.
  • the thickness of the insulating layer 207 is preferably greater than or equal to 5 nm and less than or equal to 400 nm, further preferably greater than or equal to 10 nm and less than or equal to 300 nm, still further preferably greater than or equal to 50 nm and less than or equal to 250 nm.
  • the insulating layer 207 can be formed by a sputtering method, a CVD method, an evaporation method, or the like.
  • a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas.
  • the deposition gas containing silicon include silane, disilane, trisilane, silane fluoride, and the like.
  • oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given.
  • the insulating layer 207 may have a stacked-layer structure in which a nitride insulating layer and an oxide insulating layer are stacked in this order from the electrode 206 side.
  • a nitride insulating layer When the nitride insulating layer is provided on the electrode 206 side, hydrogen, nitrogen, an alkali metal, an alkaline earth metal, or the like from the electrode 206 side can be prevented from moving to the semiconductor layer 208 .
  • nitrogen, an alkali metal, an alkaline earth metal, or the like generally serves as an impurity element of a semiconductor.
  • hydrogen serves as an impurity element of an oxide semiconductor.
  • an “impurity” in this specification and the like includes hydrogen, nitrogen, an alkali metal, an alkaline earth metal, or the like.
  • the density of defect states at the interface between the insulating layer 207 and the semiconductor layer 208 can be reduced by providing the oxide insulating layer on the semiconductor layer 208 side. Consequently, a transistor whose electrical characteristics are hardly degraded can be obtained.
  • an oxide insulating layer containing oxygen in a proportion higher than that in the stoichiometric composition is preferably formed as the oxide insulating layer. This is because the density of defect states at the interface between the insulating layer 207 and the semiconductor layer 208 can be further reduced.
  • the insulating layer 207 is a stacked layer of a nitride insulating layer and an oxide insulating layer as described above, it is preferable that the nitride insulating layer be thicker than the oxide insulating layer.
  • the nitride insulating layer has a dielectric constant higher than that of the oxide insulating layer; therefore, an electric field generated from the electrode 206 can be efficiently transmitted to the semiconductor layer 208 even when the insulating layer 207 has a large thickness.
  • the withstand voltage of the insulating layer 207 can be increased. Accordingly, the reliability of the display device can be improved.
  • the insulating layer 207 can have a stacked-layer structure in which a first nitride insulating layer with few defects, a second nitride insulating layer with a high blocking property against hydrogen, and an oxide insulating layer are stacked in that order from the electrode 206 side.
  • the first nitride insulating layer with few defects is used in the insulating layer 207 , the withstand voltage of the insulating layer 207 can be improved.
  • the use of the second nitride insulating layer with a high blocking property against hydrogen in the insulating layer 207 makes it possible to prevent hydrogen contained in the electrode 206 and the first nitride insulating layer from moving to the semiconductor layer 208 .
  • first and second nitride insulating layers An example of a method of forming the first and second nitride insulating layers is described below.
  • a silicon nitride film with few defects is formed using a mixed gas of silane, nitrogen, and ammonia as a source gas by a plasma CVD method.
  • a mixed gas of silane and nitrogen is used as a source gas, so that a silicon nitride film in which the hydrogen concentration is low and which can block hydrogen is formed as the second nitride insulating layer.
  • the insulating layer 207 in which nitride insulating layers with few defects and a blocking property against hydrogen are stacked can be formed.
  • the insulating layer 207 can have a structure in which a third nitride insulating layer with a high blocking property against an impurity, the first nitride insulating layer with few defects, the second nitride insulating layer with a high blocking property against hydrogen, and the oxide insulating layer are stacked in that order from the electrode 206 side.
  • a third nitride insulating layer with a high blocking property against an impurity is provided in the insulating layer 207 , hydrogen, nitrogen, an alkali metal, an alkaline earth metal, or the like, can be from the electrode 206 prevented from moving to the semiconductor layer 208 .
  • a silicon nitride film with a high blocking property against an impurity is formed using a mixed gas of silane, nitrogen, and ammonia as a source gas by a plasma CVD method.
  • the flow rate of ammonia is increased, so that a silicon nitride film with few defects is formed as the first nitride insulating layer.
  • a mixed gas of silane and nitrogen is used as a source gas, so that a silicon nitride film in which the hydrogen concentration is low and which can block hydrogen is formed as the second nitride insulating layer.
  • MOCVD metal organic chemical vapor deposition
  • the threshold voltage of the transistor can be changed by stacking the semiconductor layer 208 in which a channel of the transistor is formed and an insulating layer containing hafnium oxide with an oxide insulating layer positioned therebetween and injecting electrons into the insulating layer containing hafnium oxide.
  • the semiconductor layer 208 can be formed using an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, or the like.
  • amorphous silicon, microcrystalline germanium, or the like can be used.
  • a compound semiconductor such as silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used.
  • a semiconductor film for forming the semiconductor layer 208 is formed by a CVD method such as a plasma CVD method, an LPCVD method, a metal CVD method, or an MOCVD method, an ALD method, a sputtering method, an evaporation method, or the like.
  • a CVD method such as a plasma CVD method, an LPCVD method, a metal CVD method, or an MOCVD method, an ALD method, a sputtering method, an evaporation method, or the like.
  • the thickness of the semiconductor film is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 50 nm.
  • an oxide semiconductor film with a thickness of 30 nm is formed by a sputtering method.
  • a resist mask is formed over the semiconductor film, and part of the semiconductor film is selectively etched using the resist mask to form the semiconductor layer 208 .
  • the resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate. Formation of the resist mask by an inkjet method needs no photomask; thus, fabrication cost can be reduced.
  • the etching of the semiconductor film may be performed by either one or both of a dry etching method and a wet etching method. After the etching of the semiconductor film, the resist mask is removed (see FIG. 3C ).
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
  • an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure.
  • an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order.
  • an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic e.g., an oxide semiconductor that has a periodic structure in a microscopic region
  • an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.
  • the CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM)
  • TEM transmission electron microscope
  • a boundary between pellets, that is, a grain boundary is not clearly observed.
  • a reduction in electron mobility due to the grain boundary is less likely to occur.
  • FIG. 22A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface.
  • the high-resolution TEM image is obtained with a spherical aberration corrector function.
  • the high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 22B is an enlarged Cs-corrected high-resolution TEM image of a region ( 1 ) in FIG. 22A .
  • FIG. 22B shows that metal atoms are arranged in a layered manner in a pellet.
  • Each metal atom layer has a configuration reflecting unevenness of a surface over which a CAAC-OS film is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged parallel to the formation surface or the top surface of the CAAC-OS film.
  • the CAAC-OS has a characteristic atomic arrangement.
  • the characteristic atomic arrangement is denoted by an auxiliary line in FIG. 22C .
  • FIGS. 22B and 22C prove that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc).
  • the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC).
  • the schematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120 is illustrated by such a structure in which bricks or blocks are stacked (see FIG. 22D ).
  • the part in which the pellets are tilted as observed in FIG. 22C corresponds to a region 5161 shown in FIG. 22D .
  • FIG. 23A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.
  • FIGS. 23B, 23C , and 23 D are enlarged Cs-corrected high-resolution TEM images of regions ( 1 ), ( 2 ), and ( 3 ) in FIG. 23A , respectively.
  • FIGS. 23B, 23C, and 23D indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets.
  • a CAAC-OS analyzed by X-ray diffraction will be described.
  • XRD X-ray diffraction
  • a CAAC-OS analyzed by electron diffraction will be described.
  • a diffraction pattern also referred to as a selected-area transmission electron diffraction pattern
  • spots derived from the (009) plane of an InGaZnO 4 crystal are included.
  • the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS.
  • FIG. 25B shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 25B , a ring-like diffraction pattern is observed.
  • the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment.
  • the first ring in FIG. 25B is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO 4 crystal.
  • the second ring in FIG. 25B is considered to be derived from the (110) plane and the like.
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element specifically, silicon or the like
  • a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • the characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like.
  • impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources.
  • oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.
  • the CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with a low carrier density (specifically, lower than 8 ⁇ 10 11 /cm 3 , preferably lower than 1 ⁇ 10 11 /cm 3 , further preferably lower than 1 ⁇ 10 10 /cm 3 , and is higher than or equal to 1 ⁇ 10 ⁇ 9 /cm 3 ).
  • Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • a CAAC-OS has a low impurity concentration and a low density of defect states.
  • the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.
  • An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image.
  • the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm.
  • an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor.
  • a grain boundary is not clearly observed in some cases.
  • a crystal part of the nc-OS may be referred to as a pellet in the following description.
  • nc-OS In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.
  • nc-OS when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied.
  • a probe diameter e.g. 50 nm or larger
  • a nanobeam electron diffraction pattern of the nc-OS bright regions in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots are shown in a ring-like region in some cases.
  • the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).
  • RNC random aligned nanocrystals
  • NANC non-aligned nanocrystals
  • the nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
  • An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.
  • a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed.
  • the a-like OS has an unstable structure because it contains a void.
  • an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.
  • Sample A An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide.
  • a unit cell of an InGaZnO 4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction.
  • the distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value).
  • the value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO 4 .
  • Each of lattice fringes corresponds to the a-b plane of the InGaZnO 4 crystal.
  • FIG. 26 shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 26 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by ( 1 ) in FIG. 26 , a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2 ⁇ 10 8 e ⁇ /nm 2 .
  • the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2 ⁇ 10 8 e ⁇ /nm 2 .
  • the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose.
  • the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
  • the a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void.
  • the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition.
  • the density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. It is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.
  • the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm 3 and lower than 6.3 g/cm 3 .
  • the density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.
  • oxide semiconductors have various structures and various properties.
  • an oxide semiconductor may be a stacked layer including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
  • FIG. 27A is a schematic view of the inside of a deposition chamber where a CAAC-OS is deposited by a sputtering method.
  • a target 5130 is attached to a backing plate.
  • a plurality of magnets is provided to face the target 5130 with the backing plate positioned therebetween.
  • the plurality of magnets generates a magnetic field.
  • the above description on the deposition chamber is referred to for the layout and structure of magnets.
  • a sputtering method in which the disposition rate is increased by utilizing a magnetic field of magnets is referred to as a magnetron sputtering method.
  • the target 5130 has a polycrystalline structure in which a cleavage plane exists in at least one crystal grain.
  • FIG. 28A shows a structure of an InGaZnO 4 crystal included in the target 5130 . Note that FIG. 28A shows a structure of the case where the InGaZnO 4 crystal is observed from a direction parallel to the b-axis when the c-axis is in an upward direction.
  • FIG. 28A indicates that oxygen atoms in a Ga—Zn—O layer are positioned close to those in an adjacent Ga—Zn—O layer.
  • the oxygen atoms have negative charge, whereby the two Ga—Zn—O layers repel each other.
  • the InGaZnO 4 crystal has a cleavage plane between the two adjacent Ga—Zn—O layers.
  • the substrate 5120 is placed to face the target 5130 , and the distance d (also referred to as a target-substrate distance (T-S distance)) is greater than or equal to 0.01 m and less than or equal to 1 m, preferably greater than or equal to 0.02 m and less than or equal to 0.5 m.
  • the deposition chamber is mostly filled with a deposition gas (e.g., an oxygen gas, an argon gas, or a mixed gas containing oxygen at 5 vol % or higher) and the pressure in the deposition chamber is controlled to be higher than or equal to 0.01 Pa and lower than or equal to 100 Pa, preferably higher than or equal to 0.1 Pa and lower than or equal to 10 Pa.
  • a deposition gas e.g., an oxygen gas, an argon gas, or a mixed gas containing oxygen at 5 vol % or higher
  • discharge starts by application of a voltage at a certain value or higher to the target 5130 , and plasma is observed.
  • the magnetic field forms a high-density plasma region in the vicinity of the target 5130 .
  • the deposition gas is ionized, so that an ion 5101 is generated.
  • the ion 5101 include an oxygen cation (O + ) and an argon cation (Ar + ).
  • the ion 5101 is accelerated toward the target 5130 side by an electric field, and then collides with the target 5130 .
  • a pellet 5100 a and a pellet 5100 b which are flat-plate-like (pellet-like) sputtered particles are separated and sputtered from the cleavage plane. Note that structures of the pellet 5100 a and the pellet 5100 b may be distorted by an impact of collision of the ion 5101 .
  • the pellet 5100 a is a flat-plate-like (pellet-like) sputtered particle having a triangle plane, e.g., regular triangle plane.
  • the pellet 5100 b is a flat-plate-like (pellet-like) sputtered particle having a hexagon plane, e.g., regular hexagon plane.
  • flat-plate-like (pellet-like) sputtered particles such as the pellet 5100 a and the pellet 5100 b are collectively called pellets 5100 .
  • the shape of a flat plane of the pellet 5100 is not limited to a triangle or a hexagon.
  • the flat plane may have a shape formed by combining two or more triangles.
  • a quadrangle e.g., rhombus
  • the thickness of the pellet 5100 is determined depending on the kind of deposition gas and the like. The thicknesses of the pellets 5100 are preferably uniform; the reason for this is described later.
  • the sputtered particle preferably has a pellet shape with a small thickness as compared to a dice shape with a large thickness.
  • the thickness of the pellet 5100 is greater than or equal to 0.4 nm and less than or equal to 1 nm, preferably greater than or equal to 0.6 nm and less than or equal to 0.8 nm.
  • the width of the pellet 5100 is greater than or equal to 1 nm and less than or equal to 3 nm, preferably greater than or equal to 1.2 nm and less than or equal to 2.5 nm.
  • the pellet 5100 corresponds to the initial nucleus in the description of ( 1 ) in FIG. 26 .
  • the pellet 5100 that includes three layers of a Ga—Zn—O layer, an In—O layer, and a Ga—Zn—O layer as shown in FIG. 28B is ejected.
  • FIG. 28C shows the structure of the pellet 5100 observed from a direction parallel to the c-axis. Therefore, the pellet 5100 has a nanometer-sized sandwich structure including two Ga—Zn—O layers (pieces of bread) and an In—O layer (filling).
  • the pellet 5100 may receive a charge when passing through the plasma, so that side surfaces thereof are negatively or positively charged.
  • the pellet 5100 includes an oxygen atom on its side surface, and the oxygen atom may be negatively charged. In this manner, when the side surfaces are charged with the same polarity, charges repel each other, and accordingly, the pellet 5100 can maintain a flat-plate shape.
  • a CAAC-OS is an In—Ga—Zn oxide
  • there is a possibility that an oxygen atom bonded to an indium atom is negatively charged.
  • an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged.
  • the pellet 5100 may grow by being bonded with an indium atom, a gallium atom, a zinc atom, an oxygen atom, or the like when passing through plasma. This is a cause of a difference in size between ( 2 ) and ( 1 ) in FIG. 26 .
  • the pellet 5100 does not grow anymore; thus, an nc-OS is formed (see FIG. 27B ).
  • An nc-OS can be deposited when the substrate 5120 has a large size because a temperature at which the deposition of an nc-OS is carried out is approximately room temperature. Note that in order that the pellet 5100 grows in plasma, it is effective to increase deposition power in sputtering. High deposition power can stabilize the structure of the pellet 5100 .
  • the pellet 5100 flies like a kite in plasma and flutters up to the substrate 5120 . Since the pellets 5100 are charged, when the pellet 5100 gets close to a region where another pellet 5100 has already been deposited, repulsion is generated.
  • a magnetic field in a direction parallel to the top surface of the substrate 5120 (also referred to as a horizontal magnetic field) is generated.
  • a potential difference is given between the substrate 5120 and the target 5130 , and accordingly, current flows from the substrate 5120 toward the target 5130 .
  • the pellet 5100 is given a force (Lorentz force) on the top surface of the substrate 5120 by an effect of the magnetic field and the current. This is explainable with Fleming's left-hand rule.
  • the mass of the pellet 5100 is larger than that of an atom. Therefore, to move the pellet 5100 over the top surface of the substrate 5120 , it is important to apply some force to the pellet 5100 from the outside.
  • One kind of the force may be force which is generated by the action of a magnetic field and current.
  • it is preferable to provide, on the top surface, a region where the magnetic field in a direction parallel to the top surface of the substrate 5120 is 10 G or higher, preferably 20 G or higher, further preferably 30 G or higher, still further preferably 50 G or higher.
  • a region where the magnetic field in a direction parallel to the top surface of the substrate 5120 is 1.5 times or higher, preferably twice or higher, further preferably 3 times or higher, still further preferably 5 times or higher as high as the magnetic field in a direction perpendicular to the top surface of the substrate 5120 .
  • magnet units and/or the substrate 5120 are moved or rotated relatively, whereby the direction of the horizontal magnetic field on the top surface of the substrate 5120 continues to change. Therefore, the pellet 5100 can be moved in various directions on the top surface of the substrate 5120 by receiving forces in various directions.
  • the temperature of the top surface of the substrate 5120 is, for example, higher than or equal to 100° C. and lower than 500° C., higher than or equal to 150° C. and lower than 450° C., or higher than or equal to 170° C. and lower than 400° C.
  • the substrate 5120 has a large size, it is possible to deposit a CAAC-OS.
  • the pellet 5100 is heated on the substrate 5120 , whereby atoms are rearranged, and the structure distortion caused by the collision of the ion 5101 can be reduced.
  • the pellet 5100 whose structure distortion is reduced is substantially single crystal. Even when the pellets 5100 are heated after being bonded, expansion and contraction of the pellet 5100 itself hardly occur, which is caused by turning the pellet 5100 into substantially single crystal. Thus, formation of defects such as a grain boundary due to expansion of a space between the pellets 5100 can be prevented, and accordingly, generation of crevasses can be prevented.
  • the CAAC-OS does not have a structure like a board of a single crystal oxide semiconductor but has arrangement with a group of pellets 5100 (nanocrystals) like stacked bricks or blocks. Furthermore, a grain boundary does not exist therebetween. Therefore, even when deformation such as shrink occurs in the CAAC-OS owing to heating during deposition, heating or bending after deposition, it is possible to relieve local stress or release distortion. Therefore, this structure is suitable for a flexible semiconductor device.
  • FIGS. 29A to 29D are cross-sectional schematic views.
  • a pellet 5105 a and a pellet 5105 b are deposited over the zinc oxide layer 5102 .
  • side surfaces of the pellet 5105 a and the pellet 5105 b are in contact with each other.
  • a pellet 5105 c is deposited over the pellet 5105 b , and then glides over the pellet 5105 b .
  • a plurality of particles 5103 ejected from the target together with the zinc oxide is crystallized by heating of the substrate 5120 to form a region 5105 a 1 on another side surface of the pellet 5105 a .
  • the plurality of particles 5103 may contain oxygen, zinc, indium, gallium, or the like.
  • the region 5105 a 1 grows to part of the pellet 5105 a to form a pellet 5105 a 2 .
  • a side surface of the pellet 5105 c is in contact with another side surface of the pellet 5105 b.
  • a pellet 5105 d is deposited over the pellet 5105 a 2 and the pellet 5105 b , and then glides over the pellet 5105 a 2 and the pellet 5105 b . Furthermore, a pellet 5105 e glides toward another side surface of the pellet 5105 c over the zinc oxide layer 5102 .
  • the pellet 5105 d is placed so that a side surface of the pellet 5105 d is in contact with a side surface of the pellet 5105 a 2 . Furthermore, a side surface of the pellet 5105 e is in contact with another side surface of the pellet 5105 c .
  • a plurality of particles 5103 ejected from the target together with the zinc oxide is crystallized by heating of the substrate 5120 to form a region 5105 d 1 on another side surface of the pellet 5105 d.
  • each pellet of the CAAC-OS is larger than that of the nc-OS.
  • a difference in size between ( 3 ) and ( 2 ) in FIG. 26 corresponds to the amount of growth after deposition.
  • the pellets may form a large pellet.
  • the large pellet has a single crystal structure.
  • the size of the large pellet may be greater than or equal to 10 nm and less than or equal to 200 nm, greater than or equal to 15 nm and less than or equal to 100 nm, or greater than or equal to 20 nm and less than or equal to 50 nm, when seen from the above. Therefore, when a channel formation region of a transistor is smaller than the large pellet, the region having a single crystal structure can be used as the channel formation region. Furthermore, when the size of the pellet is increased, the region having a single crystal structure can be used as the channel formation region, the source region, and the drain region of the transistor.
  • the frequency characteristics of the transistor can be increased in some cases.
  • the pellets 5100 are considered to be deposited on the substrate 5120 .
  • a CAAC-OS can be deposited even when a formation surface does not have a crystal structure, which is different from film deposition by epitaxial growth.
  • the top surface (formation surface) of the substrate 5120 has an amorphous structure (e.g., the top surface is formed of amorphous silicon oxide), a CAAC-OS can be formed.
  • the pellets 5100 are arranged in accordance with the top surface shape of the substrate 5120 that is the formation surface even when the formation surface has unevenness.
  • the pellets 5100 are arranged so that flat planes parallel to the a-b plane face downwards.
  • a CAAC-OS in which n layers (n is a natural number) in each of which the pellets 5100 are arranged along the unevenness are stacked is formed. Since the substrate 5120 has unevenness, a gap is easily generated between the pellets 5100 in the CAAC-OS in some cases. Note that owing to intermolecular force, the pellets 5100 are arranged so that a gap between the pellets is as small as possible even on the unevenness surface. Therefore, even when the formation surface has unevenness, a CAAC-OS with high crystallinity can be obtained.
  • the sputtered particle preferably has a pellet shape with a small thickness. Note that when the sputtered particles have a dice shape with a large thickness, planes facing the substrate 5120 vary; thus, the thicknesses and orientations of the crystals cannot be uniform in some cases.
  • a CAAC-OS with high crystallinity can be formed even on a formation surface with an amorphous structure.
  • the electrodes 214 and 215 and the wiring 219 are formed (see FIG. 3D ).
  • a conductive film for forming the electrodes 214 and 215 and the wiring 219 is formed over the insulating layer 207 and the semiconductor layer 208 .
  • the conductive film can have a single-layer structure or a stacked-layer structure containing any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten or an alloy containing any of these metals as its main component.
  • metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten or an alloy containing any of these metals as its main component.
  • the following structures can be given: a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked over a titanium film, a two-layer structure in which an aluminum film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked over a titanium film, a two-layer structure in which a copper film is stacked over a tungsten film, a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order, a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride
  • a conductive material containing oxygen such as indium tin oxide, zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added, or a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. It is also possible to use a stacked-layer structure formed using a material containing the above metal element and conductive material containing oxygen. It is also possible to use a stacked-layer structure formed using a material containing the above metal element and a conductive material containing nitrogen. It is also possible to use a stacked-layer structure formed using a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • the thickness of the conductive film is greater than or equal to 5 nm and less than or equal to 500 nm, preferably greater than or equal to 10 nm and less than or equal to 300 nm, further preferably greater than or equal to 10 nm and less than or equal to 200 nm.
  • a 300-nm-thick tungsten film is formed as the conductive film.
  • the resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate. Formation of the resist mask by an inkjet method needs no photomask; thus, fabrication cost can be reduced.
  • the conductive film may be etched by a dry etching method, a wet etching method, or both a dry etching method and a wet etching method. Note that an exposed portion of the semiconductor layer 208 is removed by the etching step in some cases. After the etching of the conductive film, the resist mask is removed.
  • the electrodes 214 and 215 are provided, thereby forming the transistor 232 (see FIG. 3D ).
  • the insulating layer 210 and the insulating layer 211 are formed over the electrodes 214 and 215 and the wiring 219 (see FIG. 4A ).
  • the insulating layers 210 and 211 can be formed using a material and a method similar to those of the insulating layer 205 .
  • an insulating layer containing oxygen is preferably used for at least part of the insulating layer 210 which is in contact with the semiconductor layer 208 .
  • the insulating layer 210 which is a stack including a plurality of layers at least a layer that is in contact with the semiconductor layer 208 is preferably formed using silicon oxide.
  • part of the insulating layers 210 and 211 are selectively etched using a resist mask to form an opening 128 (see FIG. 4A ).
  • a resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate. Formation of the resist mask by an inkjet method needs no photomask; thus, fabrication cost can be reduced.
  • the insulating layers 210 and 211 may be etched by a dry etching method, a wet etching method, or both a dry etching method and a wet etching method.
  • the drain electrode 215 and the terminal electrode 216 are partly exposed by the formation of the opening 128 .
  • the resist mask is removed after the formation of the opening 128 .
  • the insulating layer 212 is formed over the insulating layer 211 (see FIG. 4B ).
  • the insulating layer 212 can be formed using a material and a method similar to those of the insulating layer 205 .
  • Planarization treatment may be performed on the insulating layer 212 to reduce unevenness of a surface on which the light-emitting element 125 is formed.
  • the planarization treatment may be, but not particularly limited to, polishing treatment (e.g., CMP) or dry etching treatment.
  • Forming the insulating layer 212 using an insulating material with a planarization function can make polishing treatment unnecessary.
  • an organic material such as a polyimide resin or an acrylic resin can be used.
  • a low-dielectric constant material a low-k material or the like can be used.
  • the insulating layer 212 may be formed by stacking a plurality of insulating layers formed of any of these materials.
  • Part of the insulating layer 212 which overlaps with the opening 128 is removed to form an opening 127 .
  • another opening that is not illustrated is also formed.
  • the insulating layer 211 in a region to which the external electrode 124 is connected later is removed.
  • the opening 127 or the like can be formed in such a manner that a resist mask is formed by a photolithography process over the insulating layer 212 and a region of the insulating layer 212 which is not covered with the resist mask is etched. A surface of the electrode 215 is exposed by the formation of the opening 127 (see FIG. 4B ).
  • the opening 127 can be formed without the resist mask.
  • a photosensitive polyimide resin is used to form the insulating layer 212 and the opening 127 .
  • the electrode 115 is formed over the insulating layer 212 (see FIG. 4C ).
  • the electrode 115 is preferably formed using a conductive material that efficiently reflects light emitted from the EL layer 117 formed later. Note that the electrode 115 may have a stacked-layer structure of a plurality of layers without limitation to a single-layer structure.
  • the electrode 115 may have a structure in which, for example, in contact with the EL layer 117 , a layer having a light-transmitting property and a work function higher than the EL layer 117 , such as an indium tin oxide layer, is provided and in contact therewith, a layer having high reflectance (e.g., a layer of aluminum, an alloy containing aluminum, or silver) is provided.
  • a layer having high reflectance e.g., a layer of aluminum, an alloy containing aluminum, or silver
  • the display device having a top-emission structure is described as an example in this embodiment, a display device having a bottom-emission structure or a dual-emission structure can be used.
  • the electrode 115 is preferably formed using a light-transmitting conductive material.
  • the electrode 115 can be formed in such a manner that a conductive film to be the electrode 115 is formed over the insulating layer 212 , a resist mask is formed over the conductive film, and a region of the conductive film which is not covered with the resist mask is etched.
  • the conductive film can be etched by a dry etching method, a wet etching method, or both a dry etching method and a wet etching method.
  • the resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate. Formation of the resist mask by an inkjet method needs no photomask; thus, fabrication cost can be reduced.
  • the resist mask is removed after the formation of the electrode 115 .
  • the partition 114 is formed (see FIG. 5A ).
  • the partition 114 is provided in order to prevent an unintended electrical short-circuit between the light-emitting elements 125 in adjacent pixels and unintended light emission from the light-emitting elements 125 .
  • the partition 114 also has a function of preventing the contact of a metal mask with the electrode 115 in the case where the metal mask is used to form the EL layer 117 described later.
  • the partition 114 can be formed of an organic resin material such as an epoxy resin, an acrylic resin, or an imide resin or an inorganic material such as silicon oxide.
  • the partition 114 is preferably formed so that its sidewall has a tapered shape or a tilted surface with a continuous curvature. The sidewall of the partition 114 having the above-described shape enables favorable coverage with the EL layer 117 and the electrode 118 formed later.
  • a structure of the EL layer 117 is described in Embodiment 4.
  • the electrode 118 is used as a cathode in this embodiment, and thus is preferably formed using a material that has a low work function and can inject electrons into the EL layer 117 described later.
  • a stack in which a metal material such as aluminum, a conductive oxide material such as indium tin oxide, or a semiconductor material is formed over a several-nanometer-thick buffer layer formed of an alkali metal or an alkaline earth metal having a low work function may be used.
  • As the buffer layer an oxide of an alkaline earth metal, a halide, a magnesium-silver alloy, or the like can also be used.
  • the electrode 118 preferably has a property of transmitting visible light.
  • the light-emitting element 125 includes the electrode 115 , the EL layer 117 , and the electrode 118 (see FIG. 5B ).
  • a structure including the substrate 101 and the transistor 232 and the light-emitting element 125 formed over the substrate 101 is referred to as an element substrate 171 .
  • a structure including the substrate 102 and the coloring layers 266 and the like provided on the substrate 102 is referred to as a counter substrate 181 .
  • a peeling layer 123 is formed over the substrate 102 (see FIG. 6A ).
  • the substrate 102 can be formed using a material similar to that of the substrate 101 . Note that the same material or different materials may be used for the substrate 101 and the substrate 102 .
  • the peeling layer 123 can be formed in a manner similar to that of the peeling layer 113 .
  • an insulating layer may be provided between the substrate 102 and the peeling layer 123 .
  • aluminoborosilicate glass is used for the substrate 102 .
  • a tungsten layer is formed by a sputtering method.
  • an surface of the peeling layer 123 it is preferable to expose an surface of the peeling layer 123 to an atmosphere containing oxygen or a plasma atmosphere containing oxygen after the formation of the peeling layer 123 . Oxidizing the surface of the peeling layer 123 can facilitate peeling of the substrate 102 performed later.
  • the insulating layer 129 is formed over the peeling layer 123 (see FIG. 6A ).
  • the insulating layer 129 can be formed using a material and a method that are similar to those of the insulating layer 205 .
  • the insulating layer 129 is formed by stacking a 200-nm-thick silicon oxynitride film, a 140-nm-thick silicon nitride oxide film, and a 100-nm-thick silicon oxynitride film by a plasma CVD method from the substrate 102 side.
  • a layer 274 for forming the light-blocking layer 264 is formed over the insulating layer 129 (see FIG. 6B ).
  • the light-blocking layer 264 has functions of blocking light emitted from an adjacent display element and suppressing color mixture between adjacent display elements.
  • the coloring layer 266 is provided such that its end portion overlaps with the end portion of the light-blocking layer 264 , whereby light leakage can be reduced.
  • the layer 274 may have a single-layer structure or a stacked-layer structure of two or more layers.
  • Examples of a material that can be used for the layer 274 are a metal material including chromium, titanium, nickel, or the like; an oxide material including chromium, titanium, nickel, or the like; and a resin material including a metal material, a pigment, or dye.
  • a resist mask is formed over the layer 274 , and the layer 274 is etched into a desired shape using the resist mask, so that the light-blocking layer 264 can be formed (see FIG. 6C ).
  • direct writing of the light-blocking layer 264 can be performed over the insulating layer 129 by an inkjet method.
  • the coloring layer 266 is formed over the insulating layer 129 (see FIG. 6D ).
  • the coloring layer is a colored layer that transmits light in a specific wavelength range.
  • a red (R) color filter for transmitting light in a red wavelength range a green (G) color filter for transmitting light in a green wavelength range, a blue (B) color filter for transmitting light in a blue wavelength range, or the like can be used.
  • Each coloring layer 266 is formed in a desired position with any of various materials by a printing method, an inkjet method, or a photolithography method. At this time, the coloring layer 266 is preferably provided so as to partly overlap with the light-blocking layer 264 . Color display can be performed by providing the coloring layers 266 of different colors in different pixels.
  • the overcoat layer 268 is formed over the light-blocking layer 264 and the coloring layer 266 (see FIG. 6E ).
  • an organic insulating layer of an acrylic resin, an epoxy resin, polyimide, or the like can be used as the overcoat layer 268 .
  • an impurity or the like contained in the coloring layer 266 can be prevented from diffusing into the light-emitting element 125 side, for example. Note that the overcoat layer 268 is not necessarily formed.
  • a light-transmitting conductive film may be formed as the overcoat layer 268 .
  • the light-transmitting conductive film is formed as the overcoat layer 268 , light emitted from the light-emitting element 125 can be transmitted through the overcoat layer 268 and transmission of ionized impurities can be prevented.
  • the light-transmitting conductive film can be formed with, for example, the above-described light-transmitting conductive material.
  • a metal film that is thin enough to have a light-transmitting property can also be used.
  • the counter substrate 181 can be formed. Note that the counter substrate 181 is not provided with the coloring layer 266 or the like in some cases when the coloring layer 266 is not needed.
  • the element substrate 171 and the counter substrate 181 are attached to each other with the bonding layer 120 provided therebetween.
  • the light-emitting element 125 included in the element substrate 171 and the coloring layer 266 included in the counter substrate 181 are arranged so as to face each other (see FIG. 7A ).
  • the substrate 101 included in the element substrate 171 is peeled from the insulating layer 221 together with the peeling layer 113 (see FIG. 7B ).
  • mechanical force e.g., a process with a human hand or a gripper, a process by rotation of a roller, or ultrasonic waves
  • a cut is made in the peeling layer 113 with a sharp edged tool, by laser light irradiation, or the like and water is injected into the cut.
  • a portion between the peeling layer 113 and the insulating layer 221 absorbs water through capillarity action, so that the substrate 101 can be peeled together with the peeling layer 113 easily.
  • part of the insulating layer 221 which overlaps with the terminal electrode 216 is removed to form an opening 132 a .
  • a surface of the terminal electrode 216 is partly exposed.
  • the substrate 111 including the opening 132 b is attached to the insulating layer 221 with the bonding layer 112 (see FIG. 8B ).
  • the attachment is performed such that the openings 132 a and 132 b overlap with each other.
  • the overlap of the openings 132 a and 132 b forms the opening 132 (see FIG. 9A ).
  • the surface of the terminal electrode 216 is exposed inside the opening 132 .
  • FIG. 11A is a perspective view of the display device 100 in which the opening 132 is provided for each terminal electrode 216
  • FIG. 11B is a cross-sectional view taken along the dash-dot line B 1 -B 2 in FIG. 11A .
  • the substrate 102 included in the counter substrate 181 is peeled from the insulating layer 129 together with the peeling layer 123 (see FIG. 9A ).
  • mechanical force e.g., a process with a human hand or a gripper, a process by rotation of a roller, or ultrasonic waves
  • a cut is made in the peeling layer 123 with a sharp edged tool, by laser light irradiation, or the like and water is injected into the cut.
  • a portion between the peeling layer 123 and the insulating layer 129 absorbs water through capillarity action, so that the substrate 102 can be peeled easily.
  • the substrate 121 is attached to the insulating layer 129 with the bonding layer 122 provided therebetween (see FIG. 9B ).
  • the display device 100 can be manufactured (see FIG. 10A ).
  • FIG. 10B is a cross-sectional view of the display device 100 having a top-emission structure including a functional layer 161 .
  • a touch sensor may be provided.
  • a material having a specific function may be used for the substrate 111 or the substrate 121 .
  • a circularly polarizing plate may be used as the substrate 111 or the substrate 121 .
  • the substrate 111 or the substrate 121 may be formed using a retardation plate, and a polarizing plate may be provided so as to overlap with the substrate.
  • the substrate 111 or the substrate 121 may be formed using a prism sheet, and a circularly polarizing plate may be provided so as to overlap with the substrate.
  • the external electrode 124 is electrically connected to the terminal electrode 216 through the anisotropic conductive connection layer 138 (see FIG. 1B ). Consequently, electric power or a signal can be input to the display device 100 .
  • an FPC can be used as the external electrode 124 .
  • a metal wire can also be used as the external electrode 124 .
  • the anisotropic conductive connection layer 138 may be used to connect the metal wire and the terminal electrode 216 to each other, the connection can be made by a wire bonding method without using the anisotropic conductive connection layer 138 .
  • the metal wire and the terminal electrode 216 can be connected to each other by a soldering method.
  • the terminal electrode 216 is provided on the back side of the display region 131 , a reduced frame width and a shape that is not significantly different from the shape of the display region can be achieved even in the case where the display region is non-rectangular.
  • the external shape of the display device 100 can be rectangular, as in FIG. 20A .
  • the external shape of the display device 100 can be formed by combining two or more curves, as in FIG. 20B .
  • the external shape of the display device 100 can be formed so as to fit the shape of an object into which the display device 100 is incorporated, as in FIG. 20C .
  • the external shape of the display device 100 illustrated in FIG. 20C fits a portion of an automobile which displays information such as speed.
  • the display region 131 displays a speedometer, an engine tachometer, and a fuel meter. Two or more portions of the back side of the display region 131 may be provided with the external electrodes 124 .
  • FIGS. 12A and 12B and FIGS. 13A and 13B are enlarged plan views of a region 170 in the display region 131 of FIG. 1A .
  • three pixels 130 function as subpixels and can be collectively used as one pixel 140 .
  • the red, green, and blue coloring layers 266 are used so as to correspond to the three pixels 130 , so that full color display can be achieve.
  • FIG. 12A three pixels 130 function as subpixels and can be collectively used as one pixel 140 .
  • the red, green, and blue coloring layers 266 are used so as to correspond to the three pixels 130 , so that full color display can be achieve.
  • the pixel 130 emitting red light, the pixel 130 emitting green light, and the pixel 130 emitting blue light are illustrated as a pixel 130 R, a pixel 130 G, and a pixel 130 B, respectively.
  • the colors of the coloring layers 266 may be a color other than red, green, and blue; for example, the colors of the coloring layer 266 may be yellow, cyan, magenta, or the like.
  • four pixels 130 may function as subpixels and may be collectively used as one pixel 140 .
  • the coloring layers 266 corresponding to the four pixels 130 may be red, green, blue, and yellow.
  • the pixel 130 emitting red light, the pixel 130 emitting green light, the pixel 130 emitting blue light, and the pixel 130 emitting yellow light are illustrated as a pixel 130 R, a pixel 130 G, a pixel 130 B, and a pixel 130 Y, respectively.
  • the coloring layers 266 corresponding to the four pixels 130 may be red, green, blue, and white (see FIG. 12B ). With the pixel 130 emitting white light (a pixel 130 W), the luminance of the display region can be increased. Note that in the case where the pixel 130 W emitting white light is provided, the coloring layer 266 corresponding to the pixel 130 W may be omitted. Without the coloring layer 266 corresponding to the pixel 130 W, a luminance reduction due to light transmission through the coloring layer 266 does not occur, and the luminance of the display region can be increased accordingly. Moreover, power consumption of the display device can be reduced.
  • each pixel 130 may function as a subpixel and two pixels 130 may be collectively used as one pixel 140 .
  • the four pixels 130 may be arranged in a matrix, as in FIG. 13B .
  • a pixel that emits light of cyan, magenta, or the like may be used instead of the pixel 130 Y or the pixel 130 W.
  • a plurality of pixels 130 that emit light of the same color may be provided in the pixel 140 .
  • the occupation areas or shapes of the pixels 130 included in the pixel 140 may be the same or different.
  • arrangement is not limited to stripe arrangement or matrix arrangement.
  • delta arrangement, Bayer arrangement, pentile arrangement, or the like can be used.
  • FIG. 13A illustrates an example of pentile arrangement.
  • This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments.
  • FIG. 14A is a block diagram of a configuration example of the display device 100 .
  • FIG. 14A illustrates the display region 131 and the driver circuits 133 , 142 a , and 142 b .
  • the driver circuits 133 , 142 a , and 142 b may be provided inside or outside the display device 100 .
  • the driver circuits 142 a and 142 b can function as, for example, scan line driver circuits.
  • the driver circuit 133 can function as, for example, a signal line driver circuit. Note that one of the driver circuits 142 a and 142 b may be omitted. Alternatively, some sort of circuit facing the driver circuit 133 with the display region 131 provided therebetween may be provided.
  • the display device 100 illustrated as an example in FIG. 14A includes m wirings 135 which are arranged substantially parallel to each other and whose potentials are controlled by the driver circuit 142 a and/or the driver circuit 142 b , and n wirings 136 which are arranged substantially parallel to each other and whose potentials are controlled by the driver circuit 133 .
  • the display region 131 includes a plurality of pixel circuits 134 arranged in a matrix. One pixel circuit 134 is used for driving one subpixel (pixel 130 ).
  • Each of the wirings 135 is electrically connected to the n pixel circuits 134 in a given row among the pixel circuits 134 arranged in m rows and n columns in the display region 131 .
  • Each of the wirings 136 is electrically connected to the m pixel circuits 134 in a given column among the pixel circuits 134 arranged in m rows and n columns. Note that m and n are each an integer of 1 or more.
  • FIGS. 14B and 14C illustrate circuit configurations that can be used for the pixel circuits 134 in the display device in FIG. 14A .
  • the pixel circuit 134 illustrated in FIG. 14B includes a transistor 431 , a capacitor 233 , the transistor 232 , and a transistor 434 .
  • the pixel circuit 134 is electrically connected to the light-emitting element 125 .
  • One of a source electrode and a drain electrode of the transistor 431 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n).
  • a gate electrode of the transistor 431 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scan line GL_m).
  • the transistor 431 has a function of controlling whether to write a data signal to a node 435 .
  • One of a pair of electrodes of the capacitor 233 is electrically connected to the node 435 , and the other of the pair of electrodes of the capacitor 233 is electrically connected to a node 437 .
  • the other of the source electrode and the drain electrode of the transistor 431 is electrically connected to the node 435 .
  • the capacitor 233 functions as a storage capacitor for storing data written to the node 435 .
  • One of a source electrode and a drain electrode of the transistor 232 is electrically connected to a potential supply line VL_a, and the other of the source electrode and the drain electrode of the transistor 232 is electrically connected to the node 437 .
  • a gate electrode of the transistor 232 is electrically connected to the node 435 .
  • One of a source electrode and a drain electrode of the transistor 434 is electrically connected to a potential supply line V 0 , and the other of the source electrode and the drain electrode of the transistor 434 is electrically connected to the node 437 .
  • a gate electrode of the transistor 434 is electrically connected to the scan line GL_m.
  • One of an anode and a cathode of the light-emitting element 125 is electrically connected to a potential supply line VL_b, and the other of the anode and the cathode of the light-emitting element 125 is electrically connected to the node 437 .
  • an organic electroluminescent element also referred to as an organic EL element
  • the light-emitting element 125 is not limited thereto and may be an inorganic EL element containing, for example, an inorganic material.
  • a power supply potential on the high potential side is referred to as a high power supply potential (also referred to as VDD), and a power supply potential on the low potential side is referred to as a low power supply potential (also referred to as VSS).
  • a ground potential can be used as the high power supply potential or the low power supply potential.
  • the low power supply potential is a potential lower than the ground potential
  • the high power supply potential is a potential higher than the ground potential.
  • a high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other, for example.
  • the pixel circuits 134 are sequentially selected row by row by the driver circuit 142 a and/or the driver circuit 142 b , so that the transistors 431 and 434 are turned on and a data signal is written to the nodes 435 .
  • the pixel circuits 134 in which the data has been written to the nodes 435 are brought into a holding state.
  • the amount of current flowing between the source electrode and the drain electrode of the transistor 232 is controlled in accordance with the potential of the data written to the node 435 .
  • the light-emitting element 125 emits light with luminance corresponding to the amount of the flowing current. This operation is sequentially performed row by row; thus, an image can be displayed.
  • the pixel circuit 134 in FIG. 14C includes the transistor 431 and the capacitor 233 .
  • the pixel circuit 134 is electrically connected to a liquid crystal element 432 .
  • the potential of one of a pair of electrodes of the liquid crystal element 432 is set in accordance with the specifications of the pixel circuit 134 as appropriate.
  • the alignment state of the liquid crystal element 432 depends on data written to a node 436 .
  • a common potential may be applied to one of the pair of electrodes of the liquid crystal element 432 included in each of the plurality of pixel circuits 134 .
  • the potential supplied to one of a pair of electrodes of the liquid crystal element 432 in the pixel circuit 134 in one row may be different from the potential supplied to one of a pair of electrodes of the liquid crystal element 432 in the pixel circuit 134 in another row.
  • Examples of a method of driving the display device including the liquid crystal element 432 include a TN mode, an STN mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an MVA mode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFS mode, and a transverse bend alignment (TBA) mode.
  • ECB electrically controlled birefringence
  • PDLC polymer-dispersed liquid crystal
  • PNLC polymer network liquid crystal
  • guest-host mode an electrically controlled birefringence (ECB) mode
  • EMB electrically controlled birefringence
  • PDLC polymer-dispersed liquid crystal
  • PNLC polymer network liquid crystal
  • guest-host mode a guest-host mode
  • the liquid crystal element 432 may be formed using a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral material.
  • the liquid crystal exhibiting a blue phase has a short response time of 1 msec or less and has optical isotropy; thus, an alignment process is not necessary.
  • a liquid crystal exhibiting a blue phase has small viewing angle dependence because the liquid crystal has optical isotropy.
  • one of the source electrode and the drain electrode of the transistor 431 is electrically connected to the signal line DL_n, and the other of the source electrode and the drain electrode of the transistor 431 is electrically connected to the node 436 .
  • the gate electrode of the transistor 431 is electrically connected to the scan line GL_m.
  • the transistor 431 has a function of controlling whether to write a data signal to the node 436 .
  • One of the pair of electrodes of the capacitor 233 is electrically connected to a wiring to which a specific potential is supplied (hereinafter referred to as a capacitor line CL), and the other of the pair of electrodes of the capacitor 233 is electrically connected to the node 436 .
  • the other of the pair of electrodes of the liquid crystal element 432 is electrically connected to the node 436 .
  • the potential of the capacitor line CL is set in accordance with the specifications of the pixel circuit 134 as appropriate.
  • the capacitor 233 functions as a storage capacitor for storing data written to the node 436 .
  • the pixel circuits 134 are sequentially selected row by row by the driver circuit 142 a and/or the driver circuit 142 b , so that the transistors 431 are turned on and a data signal is written to the nodes 436 .
  • the transistors 431 When the transistors 431 are turned off, the pixel circuits 134 in which the data signal has been written to the nodes 436 are brought into a holding state. This operation is sequentially performed row by row; thus, an image can be displayed on the display region 131 .
  • the display device of one embodiment of the present invention can employ various modes and can include various display elements.
  • the display element include a display medium whose contrast, luminance, reflectance, transmittance, or the like is changed by electrical or magnetic effect, such as an electroluminescence (EL) element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical system (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), MIRASOL (registered trademark), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-inter
  • quantum dots may be used as the display element.
  • Examples of display devices having EL elements include an EL display.
  • Examples of a display device including an electron emitter include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display).
  • Examples of display devices including quantum dots include a quantum dot display.
  • Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display).
  • Examples of a display device including electronic ink, electronic liquid powder (registered trademark), or electrophoretic elements include electronic paper.
  • some or all of pixel electrodes function as reflective electrodes.
  • some or all of pixel electrodes are formed to contain aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.
  • This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments.
  • FIGS. 15 A 1 to 15 B 2 an example of a transistor which can be used instead of the transistor 232 and/or the transistor 252 described in the above embodiments will be described with reference to FIGS. 15 A 1 to 15 B 2 .
  • a transistor disclosed in this specification and the like can be used as the transistors 431 , 434 , and the like.
  • a transistor 410 shown in FIG. 15 A 1 as an example is a channel-protective transistor that is a type of bottom-gate transistor.
  • the transistor 410 includes an insulating layer 209 that can function as a channel protective layer over a channel formation region in the semiconductor layer 208 .
  • the insulating layer 209 can be formed using a material and a method that are similar to those of the insulating layer 205 .
  • Part of the electrode 214 and part of the electrode 215 are formed over the insulating layer 209 .
  • the semiconductor layer 208 can be prevented from being exposed at the time of forming the electrode 214 and the electrode 215 .
  • the semiconductor layer 208 can be prevented from being reduced in thickness at the time of forming the electrode 214 and the electrode 215 .
  • a transistor with favorable electrical characteristics can be provided.
  • a transistor 411 illustrated in FIG. 15 A 2 is different from the transistor 410 in that an electrode 213 that can function as a back gate electrode is provided over the insulating layer 211 .
  • the electrode 213 can be formed using a material and a method that are similar to those of the electrode 206 .
  • the electrode 213 may be formed between the insulating layer 210 and the insulating layer 211 .
  • the back gate electrode is formed using a conductive layer and positioned so that the channel formation region of the semiconductor layer is provided between the gate electrode and the back gate electrode.
  • the back gate electrode can function in a manner similar to that of the gate electrode.
  • the potential of the back gate electrode may be the same as that of the gate electrode or may be a GND potential or a predetermined potential.
  • the electrodes 206 and 213 can both function as a gate electrode.
  • the insulating layers 207 , 209 , 210 , and 211 can all function as a gate insulating layer.
  • the other can be referred to as a “back gate electrode”.
  • the electrode 206 in the case where the electrode 213 is referred to as a “gate electrode”, the electrode 206 is referred to as a “back gate electrode”.
  • the transistor 411 in the case where the electrode 213 is used as a “gate electrode”, the transistor 411 is a kind of top-gate transistor.
  • one of the electrode 206 and the electrode 213 may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.
  • the electrode 206 and the electrode 213 With the electrode 206 and the electrode 213 with the semiconductor layer 208 provided therebetween and setting the potentials of the electrode 206 and the electrode 213 to be the same, a region of the semiconductor layer 208 through which carriers flow is enlarged in the film thickness direction; thus, the number of transferred carriers is increased. As a result, the on-state current and the field-effect mobility of the transistor 411 are increased.
  • the transistor 411 has large on-state current for the area occupied thereby. That is, the area occupied by the transistor 411 can be small for required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.
  • the gate electrode and the back gate electrode are formed using conductive layers and thus each have a function of preventing an electric field generated outside the transistor from influencing the semiconductor layer in which the channel is formed (in particular, a function of blocking static electricity).
  • the electrode 206 and the electrode 213 each have a function of blocking an electric field generated outside, charges of charged particles and the like generated on the substrate 111 side or above the electrode 213 do not influence the channel formation region in the semiconductor layer 208 . Therefore, degradation in a stress test (e.g., a negative gate bias temperature ( ⁇ GBT) stress test in which negative charges are applied to a gate) can be reduced, and changes in the rising voltages of on-state current at different drain voltages can be reduced. Note that this effect is caused when the electrodes 206 and 213 have the same potential or different potentials.
  • a stress test e.g., a negative gate bias temperature ( ⁇ GBT) stress test in which negative charges are applied to a gate
  • the BT stress test is one kind of accelerated test and can evaluate, in a short time, a change by long-term use (i.e., a change over time) in characteristics of transistors.
  • a change by long-term use i.e., a change over time
  • the change in threshold voltage of the transistor between before and after the BT stress test is an important indicator when examining the reliability of the transistor. If the change in the threshold voltage between before and after the BT stress test is small, the transistor has higher reliability.
  • the change in threshold voltage is reduced. Accordingly, variation in electrical characteristics among a plurality of transistors is also reduced.
  • the transistor including the back gate electrode has a smaller change in threshold voltage between before and after a positive GBT stress test in which positive charges are applied to a gate than a transistor including no back gate electrode.
  • a transistor with high reliability can be provided.
  • a semiconductor device with high reliability can be provided.
  • a transistor 420 shown in FIG. 15 B 1 as an example is a channel-protective transistor that is a type of bottom-gate transistor.
  • the transistor 420 has substantially the same structure as the transistor 410 but is different from the transistor 410 in that the insulating layer 209 covers the semiconductor layer 208 .
  • the semiconductor layer 208 is electrically connected to the electrode 214 in an opening which is formed by selectively removing part of the insulating layer 209 .
  • the semiconductor layer 208 is electrically connected to the electrode 215 in the opening which is formed by selectively removing part of the insulating layer 209 .
  • a region of the insulating layer 209 which overlaps with the channel formation region can function as a channel protective layer.
  • the semiconductor layer 208 can be prevented from being exposed at the time of forming the electrode 214 and the electrode 215 .
  • the semiconductor layer 208 can be prevented from being reduced in thickness at the time of forming the electrode 214 and the electrode 215 .
  • a transistor 421 illustrated in FIG. 15 B 2 is different from the transistor 420 in that the electrode 213 that can function as a back gate electrode is provided over the insulating layer 211 .
  • the transistor 421 includes the electrode 213 formed over the insulating layer 211 . As described above, the electrode 213 can function as a back gate electrode.
  • the transistor 421 as well as the transistor 411 has large on-state current for the area occupied thereby. That is, the area occupied by the transistor 421 can be small for required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.
  • the semiconductor layer 208 can be prevented from being exposed at the time of forming the electrode 214 and the electrode 215 .
  • the semiconductor layer 208 can be prevented from being reduced in thickness at the time of forming the electrode 214 and the electrode 215 .
  • the length between the electrode 214 and the electrode 206 and the length between the electrode 215 and the electrode 206 in the transistors 420 and 421 are longer than those in the transistors 410 and 411 .
  • the parasitic capacitance generated between the electrode 214 and the electrode 206 can be reduced.
  • the parasitic capacitance generated between the electrode 215 and the electrode 206 can be reduced.
  • a transistor with favorable electrical characteristics can be provided.
  • a transistor 425 illustrated in FIG. 15 C 1 is a channel-etched transistor that is a type of bottom-gate transistor.
  • the electrodes 214 and 215 are formed without using the insulating layer 209 , and therefore the semiconductor layer 208 might be partly exposed and etched when the electrodes 214 and 215 are formed.
  • the productivity of the transistor can be increased.
  • a transistor 426 illustrated in FIG. 15 C 2 is different from the transistor 425 in that the electrode 213 which can function as a back gate electrode is provided over the insulating layer 211 .
  • FIG. 16A is a top view of the transistor 426 .
  • FIG. 16B is a cross-sectional view (in the channel length direction) taken along the dash-dot line X 1 -X 2 in FIG. 16A .
  • FIG. 16C is a cross-sectional view (in the channel width direction) taken along the dash-dot line Y 1 -Y 2 in FIG. 16A .
  • the electrode 206 provided over the insulating layer 119 is electrically connected to the electrode 213 in an opening 247 a and an opening 247 b formed in the insulating layers 211 , 210 , and 207 . Accordingly, the same potential is supplied to the electrodes 206 and 213 . Furthermore, either or both of the openings 247 a and 247 b may be omitted. In the case where both the openings 247 a and 247 b are omitted, different potentials can be supplied to the electrodes 206 and 213 .
  • a transistor 430 shown in FIG. 17 A 1 as an example is a type of top-gate transistor.
  • the transistor 430 includes the semiconductor layer 208 over the insulating layer 119 ; the electrode 214 in contact with part of the semiconductor layer 208 and the electrode 215 in contact with part of the semiconductor layer 208 , over the semiconductor layer 208 and the insulating layer 119 ; the insulating layer 207 over the semiconductor layer 208 , the electrode 214 and the electrode 215 ; and the electrode 206 over the insulating layer 207 .
  • the insulating layer 210 and the insulating layer 211 are formed over the electrode 206 .
  • the electrode 206 overlaps with neither the electrode 214 nor the electrode 215 , the parasitic capacitance generated between the electrode 206 and the electrode 214 and the parasitic capacitance generated between the electrode 206 and the electrode 215 can be reduced.
  • an impurity element 222 is introduced into the semiconductor layer 208 using the electrode 206 as a mask, so that an impurity region can be formed in the semiconductor layer 208 in a self-aligned manner (see FIG. 17 A 3 ).
  • a transistor with favorable electrical characteristics can be provided.
  • the introduction of the impurity element 222 can be performed with an ion implantation apparatus, an ion doping apparatus, or a plasma treatment apparatus.
  • the impurity element 222 In the case where a semiconductor such as silicon is used for the semiconductor layer 208 , for example, at least one kind of element of Group 13 elements and Group 15 elements can be used as the impurity element 222 . In the case where an oxide semiconductor is used for the semiconductor layer 208 , at least one kind of element of rare gases, hydrogen, and nitrogen can also be used as the impurity element 222 .
  • a transistor 440 shown in FIG. 17 B 1 as an example is a type of top-gate transistor.
  • the transistor 440 is different from the transistor 430 in that the semiconductor layer 208 is formed after the formation of the electrode 214 and the electrode 215 .
  • a transistor 441 shown in FIG. 17 B 2 as an example is different from the transistor 431 in that the semiconductor layer 208 is formed after the formation of the electrode 214 and the electrode 215 .
  • part of the semiconductor layer 208 is formed over the electrode 214 and another part of the semiconductor layer 208 is formed over the electrode 215 .
  • the impurity element 222 is introduced into the semiconductor layer 208 using the electrode 206 as a mask, so that an impurity region can be formed in the semiconductor layer 208 in a self-aligned manner.
  • a transistor with favorable electrical characteristics can be provided. Therefore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.
  • films such as the metal film, the semiconductor film, the inorganic insulating film which are disclosed in this specification and the like can be formed by a sputtering method or a plasma chemical vapor deposition (CVD) method
  • such films may be formed by another method, for example, a thermal CVD method.
  • a metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be employed as an example of a thermal CVD method.
  • a thermal CVD method has an advantage that no defect due to plasma damage is generated because it does not utilize plasma for forming a film.
  • Deposition by a thermal CVD method may be performed in such a manner that a source gas and an oxidizer are supplied to a chamber at a time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and they are reacted with each other in the vicinity of the substrate or over the substrate.
  • Deposition by an ALD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated.
  • source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated.
  • two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves).
  • a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time as or after the introduction of the first source gas so that the source gases are not mixed, and then a second source gas is introduced.
  • an inert gas e.g., argon or nitrogen
  • the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the introduction of the second source gas.
  • the first source gas may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then the second source gas may be introduced.
  • the first source gas is adsorbed on a surface of the substrate to form a first layer; then the second source gas is introduced to react with the first layer; as a result, a second layer is stacked over the first layer, so that a thin film is formed.
  • the sequence of the gas introduction is repeated plural times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed.
  • the thickness of the thin film can be adjusted by the number of repetition times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust the film thickness and thus is suitable for manufacturing a minute FET.
  • the variety of films such as the metal film, the semiconductor film, and the inorganic insulating film which are described in the above embodiments can be formed by a thermal CVD method such as a MOCVD method or an ALD method.
  • a thermal CVD method such as a MOCVD method or an ALD method.
  • trimethylindium, trimethylgallium, and dimethylzinc are used.
  • the chemical formula of trimethylindium is In(CH 3 ) 3 .
  • the chemical formula of trimethylgallium is Ga(CH 3 ) 3 .
  • the chemical formula of dimethylzinc is Zn(CH 3 ) 2 .
  • triethylgallium (chemical formula: Ga (C 2 H 5 ) 3 ) can be used instead of trimethylgallium
  • diethylzinc (chemical formula: Zn (C 2 H 5 ) 2 ) can be used instead of dimethylzinc.
  • a hafnium oxide film is formed by a deposition apparatus using an ALD method
  • two kinds of gases i.e., ozone (O 3 ) as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and a hafnium precursor compound (a hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH)
  • a hafnium precursor compound a hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH)
  • TDMAH tetrakis(dimethylamide)hafnium
  • the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH 3 ) 2 ] 4 .
  • another material liquid include tetrakis(ethylmethylamide)hafnium.
  • an aluminum oxide film is formed by a deposition apparatus using an ALD method
  • two kinds of gases e.g., H 2 O as an oxidizer and a source gas which is obtained by vaporizing a solvent and liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) are used.
  • TMA trimethylaluminum
  • the chemical formula of trimethylaluminum is Al (CH 3 ) 3 .
  • another material liquid include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate).
  • hexachlorodisilane is adsorbed on a surface where a film is to be formed, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (e.g., O 2 or dinitrogen monoxide) are supplied to react with the adsorbate.
  • an oxidizing gas e.g., O 2 or dinitrogen monoxide
  • a WF 6 gas and a B 2 H 6 gas are sequentially introduced plural times to form an initial tungsten film, and then a WF 6 gas and an H 2 gas are sequentially introduced plural times to form a tungsten film.
  • an SiH 4 gas may be used instead of a B 2 H 6 gas.
  • an oxide semiconductor film for example, an In—Ga—Zn—O film is formed by a deposition apparatus using an ALD method
  • an In(CH 3 ) 3 gas and an O 3 gas are sequentially introduced plural times to form an In—O layer
  • a Ga(CH 3 ) 3 gas and an O 3 gas are sequentially introduced plural times to form a GaO layer
  • a Zn(CH 3 ) 2 gas and an O 3 gas are sequentially introduced plural times to form a ZnO layer.
  • a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by using these gases.
  • an H 2 O gas which is obtained by bubbling water with an inert gas such as Ar may be used instead of an O 3 gas, it is preferable to use an O 3 gas, which does not contain H.
  • an In (CH 3 ) 3 gas instead of an In (CH 3 ) 3 gas, an In (C 2 H 5 ) 3 gas may be used.
  • a Ga (CH 3 ) 3 gas instead of a Ga (C 2 H 5 ) 3 gas may be used.
  • FIG. 18A is a top view of a transistor 451 .
  • FIG. 18B is a cross-sectional view (in the channel length direction) taken along dash-dot line X 1 -X 2 in FIG. 18A .
  • FIG. 18C is a cross-sectional view (in the channel width direction) taken along dash-dot line Y 1 -Y 2 in FIG. 18A .
  • the semiconductor layer 208 is formed over a convex portion of the insulating layer 217 .
  • the transistor 451 is a type of top-gate transistor including a back gate electrode.
  • FIGS. 18A to 18C illustrate an example in which a layer of an inorganic semiconductor such as silicon is used as the semiconductor layer 208 included in the transistor 451 .
  • the semiconductor layer 208 includes a semiconductor layer 208 i , two semiconductor layers 208 t , and two semiconductor layers 208 u in a region overlapping with the electrode 213 .
  • the semiconductor layer 208 i is positioned between the two semiconductor layers 208 t .
  • the semiconductor layer 208 i and the two semiconductor layers 208 t are positioned between the two semiconductor layers 208 u .
  • the element 206 and the semiconductor layer 208 i overlap with each other with the insulating layer 207 positioned therebetween.
  • the semiconductor layers 208 t and 208 u include an impurity imparting a conductivity type.
  • the concentration of the impurity in the semiconductor layers 208 t is higher than that of the impurity in the semiconductor layer 208 i and lower than that of the impurity in the semiconductor layers 208 u .
  • the concentration of the impurity in the semiconductor layers 208 u is higher than that of the impurity in the semiconductor layers 208 t.
  • the semiconductor layers 208 t function as low concentration impurity regions (LDD).
  • the semiconductor layers 208 u function as high concentration impurity regions. Note that one or both of the two semiconductor layers 208 t may be omitted.
  • One of the semiconductor layers 208 u functions as a source region and the other thereof functions as a drain region.
  • the electrode 214 provided over the insulating layer 211 is electrically connected to one of the semiconductor layers 208 u in an opening 247 c formed in the insulating layers 211 , 210 , and 207 .
  • the electrode 215 provided over the insulating layer 211 is electrically connected to the other of the semiconductor layers 208 u in an opening 247 d formed in the insulating layers 211 , 210 , and 207 .
  • the electrode 206 provided over the insulating layer 211 is electrically connected to the electrode 213 in an opening 247 a and an opening 247 b formed in the insulating layers 207 and 217 . Accordingly, the same potential is supplied to the electrodes 206 and 213 . Furthermore, either or both of the openings 247 a and 247 b may be omitted. In the case where both the openings 247 a and 247 b are omitted, different potentials can be supplied to the electrodes 206 and 213 .
  • This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments.
  • an EL layer 320 described in this embodiment corresponds to the EL layer 117 described in the other embodiments.
  • the EL layer 320 is sandwiched between a pair of electrodes (electrodes 318 and 322 ). Note that the electrode 318 is used as an anode and the electrode 322 is used as a cathode as an example in the following description of this embodiment.
  • the EL layer 320 includes at least a light-emitting layer and may have a stacked-layer structure including a functional layer other than the light-emitting layer.
  • a functional layer other than the light-emitting layer a layer containing a substance having a high hole-injection property, a substance having a high hole-transport property, a substance having a high electron-transport property, a substance having a high electron-injection property, a bipolar substance (a substance having high electron and hole transport properties), or the like can be used.
  • functional layers such as a hole-injection layer, a hole-transport layer, an electron-transport layer, and an electron-injection layer can be used in appropriate combination.
  • the light-emitting element 330 illustrated in FIG. 19A emits light when current flows by applying a potential difference between the electrode 318 and the electrode 322 and holes and electrons are recombined in the EL layer 320 . In other words, a light-emitting region is formed in the EL layer 320 .
  • light emitted from the light-emitting element 330 is extracted to the outside from the electrode 318 side or the electrode 322 side.
  • one of the electrodes 318 and 322 is formed using a light-transmitting substance.
  • a plurality of EL layers 320 may be stacked between the electrode 318 and the electrode 322 as in a light-emitting element 331 illustrated in FIG. 19B .
  • an charge generation layer 320 a is preferably provided between an m-th EL layer 320 and an (m+1)-th EL layer 320 .
  • the charge generation layer 320 a can be formed using a composite material of an organic compound and a metal oxide, a metal oxide, a composite material of an organic compound and an alkali metal, an alkaline earth metal, or a compound thereof; alternatively, these materials can be combined as appropriate.
  • the composite material of an organic compound and a metal oxide include composite materials of an organic compound and a metal oxide such as vanadium oxide, molybdenum oxide, and tungsten oxide.
  • the organic compound a variety of compounds can be used; for example, low molecular compounds such as an aromatic amine compound, a carbazole derivative, and aromatic hydrocarbon and oligomers, dendrimers, and polymers of these low molecular compounds.
  • the organic compound it is preferable to use the organic compound which has a hole-transport property and has a hole mobility of 10 ⁇ 6 cm 2 /Vs or higher.
  • substances other than the substances given above may also be used as long as the substances have hole-transport properties higher than electron-transport properties.
  • These materials used for the charge generation layer 320 a have excellent carrier-injection properties and carrier-transport properties; thus, the light-emitting element 330 can be driven with low current and with low voltage.
  • the charge generation layer 320 a may be formed by a combination of a composite material of an organic compound and a metal oxide with another material.
  • the charge generation layer 320 a may be formed by a combination of a layer containing the composite material of an organic compound and a metal oxide with a layer containing one compound selected from electron-donating substances and a compound having a high electron-transport property.
  • the charge generation layer 320 a may be formed by a combination of a layer containing the composite material of an organic compound and a metal oxide with a transparent conductive film.
  • the light-emitting element 331 having such a structure is unlikely to suffer the problem of energy transfer, quenching, or the like and has an expanded choice of materials, and thus can easily have both high emission efficiency and a long lifetime. Moreover, it is easy to obtain phosphorescence from one light-emitting layer and fluorescence from the other light-emitting layer.
  • the charge generation layer 320 a has a function of injecting holes to one of the EL layers 320 that is in contact with the charge generation layer 320 a and a function of injecting electrons to the other EL layer 320 that is in contact with the charge generation layer 320 a , when voltage is applied to the electrodes 318 and 322 .
  • the light-emitting element 331 illustrated in FIG. 19B can provide a variety of emission colors by changing the type of the light-emitting substance used for the EL layers 320 .
  • a plurality of light-emitting substances having different emission colors may be used as the light-emitting substances, so that light emission having a broad spectrum or white light emission can be obtained.
  • a structure for emitting white light including red light, green light, and blue light may be used; for example, the structure may include a light-emitting layer containing a blue fluorescent substance as a light-emitting substance and a light-emitting layer containing red and green phosphorescent substances as light-emitting substances.
  • a structure including a light-emitting layer emitting red light, a light-emitting layer emitting green light, and a light-emitting layer emitting blue light may be employed.
  • white light emission can be obtained.
  • a stacked-layer element including two light-emitting layers in which light emitted from one of the light-emitting layers and light emitted from the other light-emitting layer have complementary colors to each other the combinations of colors are as follows: blue and yellow, blue-green and red, and the like.
  • the element in the structure of the above-described stacked-layer element, by providing the charge generation layer between the stacked light-emitting layers, the element can have a long lifetime in a high-luminance region while keeping the current density low. In addition, the voltage drop due to the resistance of the electrode material can be reduced, whereby uniform light emission in a large area is possible.
  • This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments.
  • the electronic device that uses the display device of one embodiment of the present invention are as follows: display devices of televisions, monitors, and the like, lighting devices, desktop and laptop personal computers, word processors, image reproduction devices which reproduce still images and moving images stored in recording media such as digital versatile discs (DVDs), portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless phone handsets, sending and receiving devices, mobile phones, car phones, portable game machines, tablet terminals, large game machines such as pachinko machines, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air-conditioning systems such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezer
  • industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for leveling the amount of power supply and smart grid.
  • moving objects and the like driven by electric motors using power from a power storage unit or the like are also included in the category of electronic devices.
  • Examples of the moving objects include electric vehicles (EV), hybrid electric vehicles (HEV) which include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEV), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats, ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecrafts.
  • EV electric vehicles
  • HEV hybrid electric vehicles
  • PHEV plug-in hybrid electric vehicles
  • tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles
  • motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats, ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecrafts.
  • television devices also referred to as televisions or television receivers
  • monitors of computers or the like digital cameras, digital video cameras, digital photo frames
  • mobile phones also referred to as cellular phones or mobile phone devices
  • portable game machines portable information terminals
  • audio reproducing devices large game machines such as pachinko machines, and the like.
  • the display device can be incorporated along a curved inside/outside wall surface of a house or a building or a curved interior/exterior surface of a car.
  • FIG. 21A is an example of a mobile phone.
  • a mobile phone 7400 includes a display portion 7402 that is incorporated in a housing 7401 .
  • the mobile phone 7400 further includes operation buttons 7403 , an external connection port 7404 , a speaker 7405 , a microphone 7406 , and the like.
  • the mobile phone 7400 is manufactured using the display device for the display portion 7402 .
  • the mobile phone 7400 illustrated in FIG. 21A includes a touch sensor in the display portion 7402 .
  • a touch sensor in the display portion 7402 .
  • data can be input into the mobile phone 7400 .
  • operations such as making a call and inputting a letter can be performed by touch on the display portion 7402 with a finger or the like.
  • buttons 7403 power ON/OFF can be switched.
  • types of images displayed on the display portion 7402 can be switched; for example, switching images from a mail creation screen to a main menu screen.
  • the display portion 7402 includes the display device of one embodiment of the present invention.
  • the display portion can be curved, and the external shape of the mobile phone and the like can have a high degree of design flexibility.
  • FIG. 21B is an example of a wristband-type display device.
  • a portable display device 7100 includes a housing 7101 , a display portion 7102 , operation buttons 7103 , and a sending and receiving device 7104 .
  • the portable display device 7100 can receive a video signal with the sending and receiving device 7104 and can display the received video on the display portion 7102 .
  • the portable display device 7100 can send an audio signal to another receiving device.
  • the display portion 7102 includes the display device of one embodiment of the present invention.
  • the display portion of the portable display device can be curved, and the external shape thereof and the like can have a high degree of design flexibility.
  • FIG. 21C illustrates an example of an automobile including a car body 951 , wheels 952 , a dashboard 953 , lights 954 , and the like.
  • FIG. 21D illustrates a driver's seat of the automobile.
  • a display portion 955 provided on the driver's seat displays information such as speed, engine speed, and fuel.
  • the display portion 955 includes the display device of one embodiment of the present invention.
  • the display portion of the display device of one embodiment of the present invention can be curved, and the external shape thereof and the like can have a high degree of design flexibility. The visibility of the display portion 955 can be thus increased.
  • This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments.
  • 100 display device, 101 : substrate, 102 : substrate, 111 : substrate, 112 : bonding layer, 113 : peeling layer, 114 : partition, 115 : electrode, 117 : EL layer, 118 : electrode, 119 : insulating layer, 120 : bonding layer, 121 : substrate, 122 : bonding layer, 123 : peeling layer, 124 : external electrode, 125 : light-emitting element, 127 : opening, 128 : opening, 129 : insulating layer, 130 : pixel, 131 : display region, 132 : opening, 133 : driver circuit, 134 : pixel circuit, 135 : wiring, 136 : wiring, 138 : anisotropic conductive connection layer, 140 : pixel, 151 : light, 161 : functional layer, 170 : region, 171 : element substrate, 181 : counter substrate, 205 : insulating layer, 206 : electrode,

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
US14/741,873 2014-06-23 2015-06-17 Display device and electronic device Expired - Fee Related US10403703B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014128672 2014-06-23
JP2014-128672 2014-06-23

Publications (2)

Publication Number Publication Date
US20150372065A1 US20150372065A1 (en) 2015-12-24
US10403703B2 true US10403703B2 (en) 2019-09-03

Family

ID=54870390

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/741,873 Expired - Fee Related US10403703B2 (en) 2014-06-23 2015-06-17 Display device and electronic device

Country Status (6)

Country Link
US (1) US10403703B2 (ko)
JP (1) JP2016027388A (ko)
KR (1) KR102377341B1 (ko)
CN (1) CN106463082B (ko)
TW (1) TWI708383B (ko)
WO (1) WO2015198183A1 (ko)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11119616B2 (en) 2018-11-01 2021-09-14 Apple Inc. Trace transfer techniques for touch sensor panels with flex circuits
US11275262B2 (en) * 2017-02-15 2022-03-15 Boe Technology Group Co., Ltd. Glass panel for display screen, method of preparing the same, display screen and the method of preparing the same
US11444255B2 (en) * 2017-05-18 2022-09-13 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing display device, display device, display module, and electronic device
US11853515B2 (en) 2018-12-19 2023-12-26 Apple Inc. Ultra-thin touch sensors
US11910661B2 (en) 2019-06-20 2024-02-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate for double-sided display and manufacturing method thereof, display panel and display device

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6497858B2 (ja) * 2014-07-11 2019-04-10 株式会社ジャパンディスプレイ 有機ｅｌ表示装置及び有機ｅｌ表示装置の製造方法
US10204535B2 (en) 2015-04-06 2019-02-12 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
CN104851892A (zh) * 2015-05-12 2015-08-19 深圳市华星光电技术有限公司 窄边框柔性显示装置及其制作方法
JP6412036B2 (ja) * 2015-12-21 2018-10-24 株式会社ジャパンディスプレイ 表示装置
WO2017158757A1 (ja) * 2016-03-16 2017-09-21 パイオニア株式会社 発光装置、電子機器及び発光装置の製造方法
KR102562898B1 (ko) * 2016-03-31 2023-08-04 삼성디스플레이 주식회사 표시 장치
JP6776058B2 (ja) * 2016-08-26 2020-10-28 シャープ株式会社 自律走行車両制御装置、自律走行車両制御システム及び自律走行車両制御方法
US10366919B2 (en) 2017-09-20 2019-07-30 Globalfoundries Inc. Fully aligned via in ground rule region
JP6992369B2 (ja) * 2017-09-27 2022-01-13 凸版印刷株式会社 カラーフィルタ及びそれを用いた表示装置
CN108254984B (zh) * 2018-01-31 2021-06-04 上海天马微电子有限公司 一种显示面板及显示装置
KR102595915B1 (ko) 2018-06-18 2023-10-31 삼성디스플레이 주식회사 디스플레이 장치 및 그 제조방법
CN118301997A (zh) * 2020-06-04 2024-07-05 武汉天马微电子有限公司 一种有机发光显示面板及显示装置
KR20220007754A (ko) * 2020-07-09 2022-01-19 삼성디스플레이 주식회사 표시 장치 및 이를 포함하는 타일형 표시 장치

Citations (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105326A (ja) 1989-09-19 1991-05-02 Tokyo Electric Co Ltd エレクトロクロミックディスプレイ
US20010020922A1 (en) * 2000-01-17 2001-09-13 Shunpei Yamazaki Display system and electrical appliance
JP2002299047A (ja) 2001-03-30 2002-10-11 Sanyo Electric Co Ltd エレクトロルミネッセンス表示装置およびその製造方法
US20030034497A1 (en) * 2001-06-20 2003-02-20 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
JP2003059648A (ja) 2001-08-10 2003-02-28 Sony Corp 表示装置及びその製造方法
JP2003255850A (ja) 2002-03-05 2003-09-10 Pioneer Electronic Corp 表示パネル基板及び表示装置
JP2006276359A (ja) 2005-03-29 2006-10-12 Sanyo Epson Imaging Devices Corp 液晶表示装置
US7253865B2 (en) 2002-05-31 2007-08-07 Koninklijke Philips Electronics N. V. Non rectangular display device
US7259429B2 (en) 2003-10-28 2007-08-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
JP2007272203A (ja) 2006-03-06 2007-10-18 Nec Corp 表示装置
US20080018557A1 (en) 2006-07-20 2008-01-24 Seiko Epson Corporation Display device, method of driving display device, and electronic apparatus
US7453426B2 (en) 2004-01-14 2008-11-18 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic apparatus
JP2009069768A (ja) 2007-09-18 2009-04-02 Toshiba Matsushita Display Technology Co Ltd 液晶表示装置
US20090102758A1 (en) 2007-10-23 2009-04-23 Epson Imaging Devices Corporation Electro-optical device
CN101419349A (zh) 2007-10-23 2009-04-29 爱普生映像元器件有限公司 电光装置
US20090108728A1 (en) 2007-10-30 2009-04-30 Fujitsu Limited Display unit manufacturing method and display unit
TW200926092A (en) 2007-10-23 2009-06-16 Epson Imaging Devices Corp Electro-optical device
JP2009134246A (ja) 2007-11-09 2009-06-18 Epson Imaging Devices Corp 電気光学装置
US20100033450A1 (en) 2008-08-08 2010-02-11 Semiconductor Energy Laboratory Co., Ltd. Display Device and Electronic Device
US20100134743A1 (en) 2008-12-02 2010-06-03 Samsung Electonics Co, Ltd. Display substrate, display panel having the display substrate, and display device having the display panel
US20100148209A1 (en) * 2008-12-17 2010-06-17 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and electronic device
US7897971B2 (en) 2007-07-26 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Display device
US20110101338A1 (en) 2009-10-30 2011-05-05 Semiconductor Energy Laboratory Co., Ltd. Non-linear element, display device including non-linear element, and electronic device including display device
CN102738203A (zh) 2009-05-26 2012-10-17 索尼公司 显示装置、制造显示装置的方法以及电子设备
EP2541371A2 (en) 2011-06-30 2013-01-02 Samsung Display Co., Ltd. Flexible display panel and display apparatus including the flexible display panel
US8367440B2 (en) 2001-07-16 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US20130107476A1 (en) 2011-10-28 2013-05-02 Derek Wright Display with Vias for Concealed Printed Circuit and Component Attachment
US20130240855A1 (en) 2012-03-15 2013-09-19 Semiconductor Energy Laboratory Co., Ltd. Method for Manufacturing Light-Emitting Device
DE102013213552A1 (de) 2012-07-12 2014-01-16 Semiconductor Energy Laboratory Co.,Ltd. Anzeigevorrichtung und Verfahren zum Herstellen der Anzeigevorrichtung
TW201405804A (zh) 2012-07-31 2014-02-01 Sony Corp 顯示單元及電子設備
US20140063364A1 (en) 2012-09-03 2014-03-06 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
US20140125935A1 (en) 2012-11-02 2014-05-08 Semiconductor Energy Laboratory Co., Ltd. Sealed Body and Method for Manufacturing the Same
US20140152912A1 (en) * 2012-11-30 2014-06-05 Lg Display Co., Ltd. Oled display device having touch sensor and method of manufacturing the same
US20140253419A1 (en) 2013-03-05 2014-09-11 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
US20140264425A1 (en) 2013-03-14 2014-09-18 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and method for manufacturing the same
US20150250038A1 (en) 2014-02-28 2015-09-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device and method for manufacturing electronic device
US20150263314A1 (en) 2014-03-13 2015-09-17 Semiconductor Energy Laboratory Co., Ltd. Method for Manufacturing Display Device and Method for Manufacturing Electronic Device
US20150309637A1 (en) * 2014-04-25 2015-10-29 Semiconductor Energy Laboratory Co., Ltd. Display Device and Electronic Device
US20160300853A1 (en) * 2015-04-06 2016-10-13 Semicondudor Energy Laboratory Co., LTD. Display device and electronic device
US20160351641A1 (en) * 2015-05-28 2016-12-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device and method for manufacturing electronic device
US20170033287A1 (en) * 2015-07-29 2017-02-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device and method for manufacturing electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5299730B2 (ja) * 2006-10-13 2013-09-25 Ｎｌｔテクノロジー株式会社 表示装置
JP2012103335A (ja) * 2010-11-08 2012-05-31 Hitachi Displays Ltd 表示装置
US8994827B2 (en) * 2012-11-20 2015-03-31 Samsung Electronics Co., Ltd Wearable electronic device

Patent Citations (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105326A (ja) 1989-09-19 1991-05-02 Tokyo Electric Co Ltd エレクトロクロミックディスプレイ
US20010020922A1 (en) * 2000-01-17 2001-09-13 Shunpei Yamazaki Display system and electrical appliance
JP2002299047A (ja) 2001-03-30 2002-10-11 Sanyo Electric Co Ltd エレクトロルミネッセンス表示装置およびその製造方法
US20080303408A1 (en) * 2001-06-20 2008-12-11 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US20030034497A1 (en) * 2001-06-20 2003-02-20 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US8367440B2 (en) 2001-07-16 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US8415208B2 (en) 2001-07-16 2013-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US20130214324A1 (en) 2001-07-16 2013-08-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
JP2003059648A (ja) 2001-08-10 2003-02-28 Sony Corp 表示装置及びその製造方法
US20030168969A1 (en) 2002-03-05 2003-09-11 Takahisa Tanabe Display panel substrate and display device
JP2003255850A (ja) 2002-03-05 2003-09-10 Pioneer Electronic Corp 表示パネル基板及び表示装置
US7253865B2 (en) 2002-05-31 2007-08-07 Koninklijke Philips Electronics N. V. Non rectangular display device
US7259429B2 (en) 2003-10-28 2007-08-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US7453426B2 (en) 2004-01-14 2008-11-18 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic apparatus
JP2006276359A (ja) 2005-03-29 2006-10-12 Sanyo Epson Imaging Devices Corp 液晶表示装置
JP2007272203A (ja) 2006-03-06 2007-10-18 Nec Corp 表示装置
US7859525B2 (en) 2006-03-06 2010-12-28 Nec Corporation Display apparatus
US20080018557A1 (en) 2006-07-20 2008-01-24 Seiko Epson Corporation Display device, method of driving display device, and electronic apparatus
US7897971B2 (en) 2007-07-26 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2009069768A (ja) 2007-09-18 2009-04-02 Toshiba Matsushita Display Technology Co Ltd 液晶表示装置
KR20090041336A (ko) 2007-10-23 2009-04-28 엡슨 이미징 디바이스 가부시키가이샤 전기 광학 장치
TW200926092A (en) 2007-10-23 2009-06-16 Epson Imaging Devices Corp Electro-optical device
CN101419349A (zh) 2007-10-23 2009-04-29 爱普生映像元器件有限公司 电光装置
US20090102758A1 (en) 2007-10-23 2009-04-23 Epson Imaging Devices Corporation Electro-optical device
US20090108728A1 (en) 2007-10-30 2009-04-30 Fujitsu Limited Display unit manufacturing method and display unit
JP2009134246A (ja) 2007-11-09 2009-06-18 Epson Imaging Devices Corp 電気光学装置
US20100033450A1 (en) 2008-08-08 2010-02-11 Semiconductor Energy Laboratory Co., Ltd. Display Device and Electronic Device
US20100134743A1 (en) 2008-12-02 2010-06-03 Samsung Electonics Co, Ltd. Display substrate, display panel having the display substrate, and display device having the display panel
US20100148209A1 (en) * 2008-12-17 2010-06-17 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and electronic device
CN102738203A (zh) 2009-05-26 2012-10-17 索尼公司 显示装置、制造显示装置的方法以及电子设备
US8482196B2 (en) 2009-05-26 2013-07-09 Sony Corporation Display, method for producing display, and electronic apparatus
US9024524B2 (en) 2009-05-26 2015-05-05 Sony Corporation Display, method for producing display, and electronic apparatus
US20110101338A1 (en) 2009-10-30 2011-05-05 Semiconductor Energy Laboratory Co., Ltd. Non-linear element, display device including non-linear element, and electronic device including display device
EP2541371A2 (en) 2011-06-30 2013-01-02 Samsung Display Co., Ltd. Flexible display panel and display apparatus including the flexible display panel
JP2013015836A (ja) 2011-06-30 2013-01-24 Samsung Display Co Ltd 可撓性表示パネル及び該可撓性表示パネルを備える表示装置
US20180364758A1 (en) 2011-06-30 2018-12-20 Samsung Display Co., Ltd. Flexible display panel and display apparatus including the flexible display panel
US10061356B2 (en) 2011-06-30 2018-08-28 Samsung Display Co., Ltd. Flexible display panel and display apparatus including the flexible display panel
CN104025178A (zh) 2011-10-28 2014-09-03 苹果公司 具有用于附接隐藏式印刷电路和部件的通孔的显示器
KR20140092363A (ko) 2011-10-28 2014-07-23 애플 인크. 컨실드 인쇄 회로 및 컴포넌트 부착용 비아를 갖는 디스플레이
US20130107476A1 (en) 2011-10-28 2013-05-02 Derek Wright Display with Vias for Concealed Printed Circuit and Component Attachment
WO2013062707A1 (en) 2011-10-28 2013-05-02 Apple Inc. Display with vias for concealed printed circuit and component attachment
JP2015501451A (ja) 2011-10-28 2015-01-15 アップル インコーポレイテッド 隠蔽プリント回路及び構成要素取り付け部のためのビアを有するディスプレイ
US20130240855A1 (en) 2012-03-15 2013-09-19 Semiconductor Energy Laboratory Co., Ltd. Method for Manufacturing Light-Emitting Device
US9082678B2 (en) 2012-07-12 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Display device including a touch sensor and method for manufacturing display device including a touch sensor
TW201407225A (zh) 2012-07-12 2014-02-16 Semiconductor Energy Lab 顯示裝置和用於製造顯示裝置的方法
KR20140009024A (ko) 2012-07-12 2014-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치, 및 표시 장치의 제작 방법
DE102013213552A1 (de) 2012-07-12 2014-01-16 Semiconductor Energy Laboratory Co.,Ltd. Anzeigevorrichtung und Verfahren zum Herstellen der Anzeigevorrichtung
JP2014032960A (ja) 2012-07-12 2014-02-20 Semiconductor Energy Lab Co Ltd 表示装置、及び表示装置の作製方法
US20140014960A1 (en) 2012-07-12 2014-01-16 Semiconductor Energy Laboratory Co., Ltd. Display Device and Method for Manufacturing Display Device
KR20150040270A (ko) 2012-07-31 2015-04-14 소니 주식회사 표시 장치 및 전자 기기
WO2014020899A2 (en) 2012-07-31 2014-02-06 Sony Corporation Display unit and electronic apparatus
CN104471736A (zh) 2012-07-31 2015-03-25 索尼公司 具有防湿密封件的显示单元
JP2014044793A (ja) 2012-07-31 2014-03-13 Sony Corp 表示装置および電子機器
TW201405804A (zh) 2012-07-31 2014-02-01 Sony Corp 顯示單元及電子設備
US20150207100A1 (en) 2012-07-31 2015-07-23 Sony Corporation Display unit and electronic apparatus
US20140063364A1 (en) 2012-09-03 2014-03-06 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP2014063484A (ja) 2012-09-03 2014-04-10 Semiconductor Energy Lab Co Ltd 表示装置、及びその作製方法
KR20140031110A (ko) 2012-09-03 2014-03-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 그 제작 방법
US20140125935A1 (en) 2012-11-02 2014-05-08 Semiconductor Energy Laboratory Co., Ltd. Sealed Body and Method for Manufacturing the Same
JP2014112666A (ja) 2012-11-02 2014-06-19 Semiconductor Energy Lab Co Ltd 封止体及び封止体の作製方法
CN103811528A (zh) 2012-11-02 2014-05-21 株式会社半导体能源研究所 密封体及密封体的制造方法
KR20140057164A (ko) 2012-11-02 2014-05-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 밀봉체 및 밀봉체의 제작 방법
US20140152912A1 (en) * 2012-11-30 2014-06-05 Lg Display Co., Ltd. Oled display device having touch sensor and method of manufacturing the same
US20140253419A1 (en) 2013-03-05 2014-09-11 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
US20140273317A1 (en) 2013-03-14 2014-09-18 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and method for manufacturing the same
US20140264425A1 (en) 2013-03-14 2014-09-18 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and method for manufacturing the same
US20150250038A1 (en) 2014-02-28 2015-09-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device and method for manufacturing electronic device
US20150263314A1 (en) 2014-03-13 2015-09-17 Semiconductor Energy Laboratory Co., Ltd. Method for Manufacturing Display Device and Method for Manufacturing Electronic Device
US20150309637A1 (en) * 2014-04-25 2015-10-29 Semiconductor Energy Laboratory Co., Ltd. Display Device and Electronic Device
US20160300853A1 (en) * 2015-04-06 2016-10-13 Semicondudor Energy Laboratory Co., LTD. Display device and electronic device
US20160351641A1 (en) * 2015-05-28 2016-12-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device and method for manufacturing electronic device
US20170033287A1 (en) * 2015-07-29 2017-02-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device and method for manufacturing electronic device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Chinese Office Action (Application No. 201580033644.3) dated Sep. 20, 2018.
International Search Report (Application No. PCT/IB2015/054444) dated Sep. 15, 2015.
Nonaka.Y et al., "A Non-Rectangular Heart-Shaped SOG-LCD", SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, No. 1, pp. 951-954.
Written Opinion (Application No. PCT/IB2015/054444) dated Sep. 15, 2015.

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11275262B2 (en) * 2017-02-15 2022-03-15 Boe Technology Group Co., Ltd. Glass panel for display screen, method of preparing the same, display screen and the method of preparing the same
US11444255B2 (en) * 2017-05-18 2022-09-13 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing display device, display device, display module, and electronic device
US11119616B2 (en) 2018-11-01 2021-09-14 Apple Inc. Trace transfer techniques for touch sensor panels with flex circuits
US11853515B2 (en) 2018-12-19 2023-12-26 Apple Inc. Ultra-thin touch sensors
US11910661B2 (en) 2019-06-20 2024-02-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate for double-sided display and manufacturing method thereof, display panel and display device

Also Published As

Publication number Publication date
WO2015198183A1 (en) 2015-12-30
CN106463082B (zh) 2019-07-16
CN106463082A (zh) 2017-02-22
KR102377341B1 (ko) 2022-03-21
JP2016027388A (ja) 2016-02-18
TW201607021A (zh) 2016-02-16
TWI708383B (zh) 2020-10-21
KR20170020854A (ko) 2017-02-24
WO2015198183A9 (en) 2017-01-05
US20150372065A1 (en) 2015-12-24

Similar Documents

Publication Publication Date Title
US10403703B2 (en) Display device and electronic device
JP7118111B2 (ja) 表示装置
US10115631B2 (en) Semiconductor device
US10038171B2 (en) Method for manufacturing display device and method for manufacturing electronic device
US9917267B2 (en) Electronic device comprising first opening and second opening with different widths
US10243012B2 (en) Method for manufacturing display device and method for manufacturing electronic device
JP2020129128A (ja) 表示装置の作製方法
JP2024116141A (ja) 半導体装置
US20200313005A1 (en) Semiconductor device and display device
JP2019216247A (ja) トランジスタの作製方法
US10777685B2 (en) Transistor
US9876058B2 (en) Display device, light-emitting device, and electronic appliance having organic resin film
US10522574B2 (en) Manufacturing method of display device and manufacturing method of electronic device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YAMAZAKI, SHUNPEI;REEL/FRAME:036321/0021

Effective date: 20150630

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20230903