US10025685B2 - Impedance compensation based on detecting sensor data - Google Patents

Impedance compensation based on detecting sensor data Download PDF

Info

Publication number
US10025685B2
US10025685B2 US14/670,411 US201514670411A US10025685B2 US 10025685 B2 US10025685 B2 US 10025685B2 US 201514670411 A US201514670411 A US 201514670411A US 10025685 B2 US10025685 B2 US 10025685B2
Authority
US
United States
Prior art keywords
memory
impedance
impedance compensation
change
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/670,411
Other languages
English (en)
Other versions
US20160284386A1 (en
Inventor
James A McCall
Kuljit S Bains
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US14/670,411 priority Critical patent/US10025685B2/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MCCALL, JAMES A, BAINS, KULJIT S
Priority to TW105103783A priority patent/TWI643206B/zh
Priority to CN201910052999.7A priority patent/CN110059048B/zh
Priority to EP16773699.0A priority patent/EP3274994B1/en
Priority to CN201680019113.3A priority patent/CN107408099B/zh
Priority to KR1020187037130A priority patent/KR102617628B1/ko
Priority to EP19211469.2A priority patent/EP3657506B1/en
Priority to JP2017541939A priority patent/JP6729940B2/ja
Priority to PCT/US2016/021153 priority patent/WO2016160276A1/en
Priority to KR1020177023566A priority patent/KR102581206B1/ko
Publication of US20160284386A1 publication Critical patent/US20160284386A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAINS, KULJIT S., MCCALL, JAMES A.
Priority to US15/993,245 priority patent/US10552285B2/en
Publication of US10025685B2 publication Critical patent/US10025685B2/en
Application granted granted Critical
Priority to JP2020112055A priority patent/JP6965494B2/ja
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Multimedia (AREA)
US14/670,411 2015-03-27 2015-03-27 Impedance compensation based on detecting sensor data Active 2035-05-31 US10025685B2 (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
US14/670,411 US10025685B2 (en) 2015-03-27 2015-03-27 Impedance compensation based on detecting sensor data
TW105103783A TWI643206B (zh) 2015-03-27 2016-02-04 基於偵測感測器資料之阻抗補償的技術
PCT/US2016/021153 WO2016160276A1 (en) 2015-03-27 2016-03-07 Impedance compensation based on detecting sensor data
KR1020177023566A KR102581206B1 (ko) 2015-03-27 2016-03-07 센서 데이터를 검출하는 것에 기초하는 임피던스 보상
CN201680019113.3A CN107408099B (zh) 2015-03-27 2016-03-07 基于检测传感器数据的阻抗补偿
KR1020187037130A KR102617628B1 (ko) 2015-03-27 2016-03-07 센서 데이터를 검출하는 것에 기초하는 임피던스 보상
EP19211469.2A EP3657506B1 (en) 2015-03-27 2016-03-07 Impedance compensation based on detecting sensor data
JP2017541939A JP6729940B2 (ja) 2015-03-27 2016-03-07 センサデータ検出に基づくインピーダンス補償
CN201910052999.7A CN110059048B (zh) 2015-03-27 2016-03-07 基于检测传感器数据的阻抗补偿
EP16773699.0A EP3274994B1 (en) 2015-03-27 2016-03-07 Impedance compensation based on detecting sensor data
US15/993,245 US10552285B2 (en) 2015-03-27 2018-05-30 Impedance compensation based on detecting sensor data
JP2020112055A JP6965494B2 (ja) 2015-03-27 2020-06-29 センサデータ検出に基づくインピーダンス補償

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/670,411 US10025685B2 (en) 2015-03-27 2015-03-27 Impedance compensation based on detecting sensor data

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/993,245 Continuation US10552285B2 (en) 2015-03-27 2018-05-30 Impedance compensation based on detecting sensor data

Publications (2)

Publication Number Publication Date
US20160284386A1 US20160284386A1 (en) 2016-09-29
US10025685B2 true US10025685B2 (en) 2018-07-17

Family

ID=56974261

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/670,411 Active 2035-05-31 US10025685B2 (en) 2015-03-27 2015-03-27 Impedance compensation based on detecting sensor data
US15/993,245 Active US10552285B2 (en) 2015-03-27 2018-05-30 Impedance compensation based on detecting sensor data

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/993,245 Active US10552285B2 (en) 2015-03-27 2018-05-30 Impedance compensation based on detecting sensor data

Country Status (7)

Country Link
US (2) US10025685B2 (ko)
EP (2) EP3657506B1 (ko)
JP (2) JP6729940B2 (ko)
KR (2) KR102581206B1 (ko)
CN (2) CN110059048B (ko)
TW (1) TWI643206B (ko)
WO (1) WO2016160276A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10418112B2 (en) 2016-08-19 2019-09-17 Toshiba Memory Corporation Semiconductor memory device

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325655B2 (en) * 2015-04-10 2019-06-18 Hewlett Packard Enterprise Development Lp Temperature compensation circuits
US10141935B2 (en) * 2015-09-25 2018-11-27 Intel Corporation Programmable on-die termination timing in a multi-rank system
US10284198B2 (en) * 2015-10-02 2019-05-07 Samsung Electronics Co., Ltd. Memory systems with ZQ global management and methods of operating same
US9653144B1 (en) 2016-06-28 2017-05-16 Intel Corporation Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate management
JP2018045743A (ja) 2016-09-13 2018-03-22 東芝メモリ株式会社 半導体装置及びメモリシステム
US9965222B1 (en) * 2016-10-21 2018-05-08 Advanced Micro Devices, Inc. Software mode register access for platform margining and debug
US10348270B2 (en) * 2016-12-09 2019-07-09 Micron Technology, Inc. Apparatuses and methods for calibrating adjustable impedances of a semiconductor device
US10366765B2 (en) * 2016-12-15 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Adjustment circuit for partitioned memory block
US10062453B1 (en) * 2017-03-09 2018-08-28 Toshiba Memory Corporation Calibrating I/O impedances using estimation of memory die temperature
US10193711B2 (en) 2017-06-22 2019-01-29 Micron Technology, Inc. Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device
KR102396741B1 (ko) * 2017-09-11 2022-05-12 에스케이하이닉스 주식회사 임피던스 캘리브레이션 회로를 포함하는 메모리 시스템
KR102391503B1 (ko) * 2017-09-11 2022-04-28 에스케이하이닉스 주식회사 임피던스 캘리브레이션 회로를 포함하는 메모리 시스템
US10615798B2 (en) 2017-10-30 2020-04-07 Micron Technology, Inc. Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
KR102649322B1 (ko) 2018-05-25 2024-03-20 삼성전자주식회사 메모리 장치, 메모리 시스템, 및 메모리 장치의 동작 방법
US11977770B2 (en) * 2018-06-04 2024-05-07 Lodestar Licensing Group Llc Methods for generating notifications for updated information from mode registers of a memory device to a host and memory devices and systems employing the same
US10692560B2 (en) * 2018-06-06 2020-06-23 Intel Corporation Periodic calibrations during memory device self refresh
US11570685B2 (en) 2018-10-24 2023-01-31 Carrier Corporation Power savings for wireless sensors
US11074976B2 (en) * 2019-08-26 2021-07-27 Sandisk Technologies Llc Temperature dependent impedance mitigation in non-volatile memory
KR20210047475A (ko) 2019-10-22 2021-04-30 삼성전자주식회사 센서를 구비한 멀티 디스플레이 장치
CN112817884A (zh) * 2019-11-15 2021-05-18 安徽寒武纪信息科技有限公司 一种存储器以及包括该存储器的设备
US10747245B1 (en) 2019-11-19 2020-08-18 Micron Technology, Inc. Apparatuses and methods for ZQ calibration
US11579784B2 (en) * 2019-11-27 2023-02-14 Micron Technology, Inc. Refresh counters in a memory system
US20200125446A1 (en) * 2019-12-20 2020-04-23 Intel Corporation Error Correcting Code Circuitry Compatible with Multi-Width Interfaces
JP6890701B1 (ja) * 2020-05-19 2021-06-18 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． コードシフト算出回路およびコードシフト値の算出方法
US11621038B2 (en) * 2021-07-21 2023-04-04 Micron Technology, Inc. Driver for non-binary signaling
US20230133234A1 (en) * 2021-11-04 2023-05-04 Samsung Electronics Co., Ltd. Electronic device controlling an operation of a volatile memory and method for operating the same
KR20230112334A (ko) 2022-01-20 2023-07-27 에스케이하이닉스 주식회사 반도체 장치, 반도체 시스템, 및 반도체 장치의 동작 방법

Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292059B1 (en) * 1999-10-29 2001-09-18 Scientific-Atlanta, Inc. Systems, methods, and circuits for providing thermal compensation in amplifiers
US6476392B1 (en) * 2001-05-11 2002-11-05 Irvine Sensors Corporation Method and apparatus for temperature compensation of an uncooled focal plane array
US6668162B1 (en) * 1999-02-03 2003-12-23 Nokia Mobile Phones Ltd. Method and an arrangement for compensating the temperature drift of a detector and a control signal in periodic control
US20040260713A1 (en) 2003-06-18 2004-12-23 Olympus Corporation LSI apparatus
US20050242833A1 (en) 2004-04-28 2005-11-03 Nak Kyu Park On-die termination impedance calibration device
US20060097749A1 (en) 2004-11-05 2006-05-11 Ati Technologies, Inc. Dynamic impedance compensation circuit and method
US7114087B2 (en) * 2003-05-27 2006-09-26 Intel Corporation Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change
US20080198666A1 (en) 2007-02-20 2008-08-21 Aaron Nygren Semiconductor device including adjustable driver output impedances
US7683712B2 (en) * 2007-03-23 2010-03-23 Panasonic Corporation Wireless frequency power amplifier, semiconductor device, and wireless frequency power amplification method
US7859296B2 (en) 2008-09-05 2010-12-28 Hynix Semiconductor Inc. Calibration circuit, on die termination device and semiconductor memory device using the same
US8111085B2 (en) 2009-08-11 2012-02-07 Renesas Electronics Corporation Semiconductor integrated circuit, semiconductor storage device and impedance adjustment method
US20120150481A1 (en) 2006-06-21 2012-06-14 Cox Christopher E Thermal sensor having toggle control
US20120206165A1 (en) 2009-06-09 2012-08-16 Google Inc. Programming of dimm termination resistance values
US20130132779A1 (en) 2005-06-24 2013-05-23 Google, Inc. Memory modules with reliability and serviceability functions
US8482339B1 (en) * 2009-06-12 2013-07-09 National Acquisition Sub, Inc. Method and apparatus for temperature compensation of filter circuits
US20140016404A1 (en) 2012-07-11 2014-01-16 Chan-kyung Kim Magnetic random access memory
US20150067292A1 (en) 2013-08-29 2015-03-05 Micron Technology, Inc. Impedance adjustment in a memory device
US20160042769A1 (en) 2014-08-07 2016-02-11 Qualcomm Incorporated Semiconductor package on package memory channels with arbitration for shared calibration resources
US20160182044A1 (en) 2014-12-17 2016-06-23 Sandisk Technologies Inc. On Chip ZQ Calibration Resistor Trimming
US20160259385A1 (en) 2015-03-05 2016-09-08 Micron Technology, Inc. Impedance adjustment

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517613A (en) * 1991-12-12 1996-05-14 Emc Corporation Environment sensing/control circuit
US6262625B1 (en) * 1999-10-29 2001-07-17 Hewlett-Packard Co Operational amplifier with digital offset calibration
US6785793B2 (en) * 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
US7111143B2 (en) * 2003-12-30 2006-09-19 Infineon Technologies Ag Burst mode implementation in a memory device
US7138823B2 (en) * 2005-01-20 2006-11-21 Micron Technology, Inc. Apparatus and method for independent control of on-die termination for output buffers of a memory device
US7432731B2 (en) * 2005-06-30 2008-10-07 Intel Corporation Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations
JP4916699B2 (ja) * 2005-10-25 2012-04-18 エルピーダメモリ株式会社 Ｚｑキャリブレーション回路及びこれを備えた半導体装置
US7644250B2 (en) * 2006-06-30 2010-01-05 Intel Corporation Defining pin functionality at device power on
US7459930B2 (en) * 2006-11-14 2008-12-02 Micron Technology, Inc. Digital calibration circuits, devices and systems including same, and methods of operation
JP2010117987A (ja) * 2008-11-14 2010-05-27 Denso Corp メモリ制御装置、およびメモリ制御プログラム
JP5287599B2 (ja) * 2009-08-24 2013-09-11 株式会社リコー 電子機器
US8307270B2 (en) * 2009-09-03 2012-11-06 International Business Machines Corporation Advanced memory device having improved performance, reduced power and increased reliability
JP2011081893A (ja) * 2009-09-11 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備えるデータ処理システム
US20110068765A1 (en) * 2009-09-22 2011-03-24 Qualcomm Incorporated System and method for power calibrating a pulse generator
JP2011101143A (ja) * 2009-11-05 2011-05-19 Elpida Memory Inc 半導体装置及びそのシステムとキャリブレーション方法
JP2011170943A (ja) * 2010-02-22 2011-09-01 Sony Corp 記憶制御装置、記憶装置、記憶装置システム
KR101206498B1 (ko) * 2010-07-08 2012-11-29 에스케이하이닉스 주식회사 임피던스 캘리브레이션 회로 및 그 동작 방법
US8738852B2 (en) * 2011-08-31 2014-05-27 Nvidia Corporation Memory controller and a dynamic random access memory interface
JP2013085078A (ja) * 2011-10-07 2013-05-09 Elpida Memory Inc 半導体装置及びこれを備える半導体モジュール
FR2987210B1 (fr) * 2012-02-22 2014-02-21 Ulis Procede de correction de la derive d'un detecteur de rayonnement infrarouge comportant une matrice de bolometres resistifs d'imagerie et dispositif mettant en oeuvre un tel procede
KR20140100330A (ko) * 2013-02-06 2014-08-14 삼성전자주식회사 메모리 시스템 및 그것의 동작 방법
KR20140107890A (ko) * 2013-02-28 2014-09-05 에스케이하이닉스 주식회사 메모리, 이를 포함하는 메모리 시스템 및 메모리 콘트롤러의 동작 방법
TWI508087B (zh) * 2013-07-01 2015-11-11 Mstar Semiconductor Inc 記憶體信號的動態相位追蹤方法及其相關控制電路
US9292076B2 (en) * 2013-09-16 2016-03-22 Intel Corporation Fast recalibration circuitry for input/output (IO) compensation finite state machine power-down-exit
US9704557B2 (en) * 2013-09-25 2017-07-11 Qualcomm Incorporated Method and apparatus for storing retention time profile information based on retention time and temperature
US20160378366A1 (en) * 2015-06-24 2016-12-29 Intel Corporation Internal consecutive row access for long burst length

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6668162B1 (en) * 1999-02-03 2003-12-23 Nokia Mobile Phones Ltd. Method and an arrangement for compensating the temperature drift of a detector and a control signal in periodic control
US6292059B1 (en) * 1999-10-29 2001-09-18 Scientific-Atlanta, Inc. Systems, methods, and circuits for providing thermal compensation in amplifiers
US6476392B1 (en) * 2001-05-11 2002-11-05 Irvine Sensors Corporation Method and apparatus for temperature compensation of an uncooled focal plane array
US7114087B2 (en) * 2003-05-27 2006-09-26 Intel Corporation Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change
US20040260713A1 (en) 2003-06-18 2004-12-23 Olympus Corporation LSI apparatus
US20050242833A1 (en) 2004-04-28 2005-11-03 Nak Kyu Park On-die termination impedance calibration device
US20060097749A1 (en) 2004-11-05 2006-05-11 Ati Technologies, Inc. Dynamic impedance compensation circuit and method
US20130132779A1 (en) 2005-06-24 2013-05-23 Google, Inc. Memory modules with reliability and serviceability functions
US20120150481A1 (en) 2006-06-21 2012-06-14 Cox Christopher E Thermal sensor having toggle control
US20080198666A1 (en) 2007-02-20 2008-08-21 Aaron Nygren Semiconductor device including adjustable driver output impedances
US7683712B2 (en) * 2007-03-23 2010-03-23 Panasonic Corporation Wireless frequency power amplifier, semiconductor device, and wireless frequency power amplification method
US7859296B2 (en) 2008-09-05 2010-12-28 Hynix Semiconductor Inc. Calibration circuit, on die termination device and semiconductor memory device using the same
US20120206165A1 (en) 2009-06-09 2012-08-16 Google Inc. Programming of dimm termination resistance values
US8482339B1 (en) * 2009-06-12 2013-07-09 National Acquisition Sub, Inc. Method and apparatus for temperature compensation of filter circuits
US8111085B2 (en) 2009-08-11 2012-02-07 Renesas Electronics Corporation Semiconductor integrated circuit, semiconductor storage device and impedance adjustment method
US20140016404A1 (en) 2012-07-11 2014-01-16 Chan-kyung Kim Magnetic random access memory
US20150067292A1 (en) 2013-08-29 2015-03-05 Micron Technology, Inc. Impedance adjustment in a memory device
US20160042769A1 (en) 2014-08-07 2016-02-11 Qualcomm Incorporated Semiconductor package on package memory channels with arbitration for shared calibration resources
US20160182044A1 (en) 2014-12-17 2016-06-23 Sandisk Technologies Inc. On Chip ZQ Calibration Resistor Trimming
US20160259385A1 (en) 2015-03-05 2016-09-08 Micron Technology, Inc. Impedance adjustment

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
English Translation of Search Report of R.O.C. Patent Application No. 105103783 1 page.
English Translation of Search Report of R.O.C. Patent Application No. 105103783, 2 pages.
International Preliminary Report on Patentability, PCT/US2016/021153, dated Oct. 12, 2017, 7 pages.
International Search Report and Written Opinion for PCT Patent Application No. PCT/US2016/021153, dated Jun. 29, 2016, 10 pages.
Nanya Technology Corp, Commercial and Industrial DDR4 4Gb SDRAM, ZQ Calibration Commands, Version 11, Mar. 2016, pp. 192-193.
Sk hynix, Computing DDR4 Device Operation, pp. 54-55.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10418112B2 (en) 2016-08-19 2019-09-17 Toshiba Memory Corporation Semiconductor memory device

Also Published As

Publication number Publication date
JP6965494B2 (ja) 2021-11-10
KR20170131371A (ko) 2017-11-29
CN107408099B (zh) 2021-04-20
US20190004919A1 (en) 2019-01-03
KR20190000387A (ko) 2019-01-02
EP3274994A4 (en) 2018-11-21
CN110059048A (zh) 2019-07-26
TWI643206B (zh) 2018-12-01
KR102581206B1 (ko) 2023-09-21
EP3274994A1 (en) 2018-01-31
EP3274994B1 (en) 2019-12-04
JP6729940B2 (ja) 2020-07-29
KR102617628B1 (ko) 2023-12-27
JP2018511108A (ja) 2018-04-19
CN110059048B (zh) 2024-02-02
US20160284386A1 (en) 2016-09-29
EP3657506A1 (en) 2020-05-27
CN107408099A (zh) 2017-11-28
TW201642257A (zh) 2016-12-01
US10552285B2 (en) 2020-02-04
EP3657506B1 (en) 2022-01-12
WO2016160276A1 (en) 2016-10-06
JP2020170532A (ja) 2020-10-15

Similar Documents

Publication Publication Date Title
US10552285B2 (en) Impedance compensation based on detecting sensor data
US11789880B2 (en) Load reduced nonvolatile memory interface
US10109340B2 (en) Precharging and refreshing banks in memory device with bank group architecture
US9948299B2 (en) On-die termination control without a dedicated pin in a multi-rank system
TWI605460B (zh) 自晶粒上動態隨機存取記憶體（ｒａｍ）錯誤校正碼（ｅｃｃ）擷取選擇性資訊的技術
US10872647B2 (en) Flexible DLL (delay locked loop) calibration
US20170285992A1 (en) Memory subsystem with narrow bandwidth repeater channel
US9953694B2 (en) Memory controller-controlled refresh abort
US9390785B2 (en) Method, apparatus and system for determining a write recovery time of a memory based on temperature

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MCCALL, JAMES A;BAINS, KULJIT S;SIGNING DATES FROM 20150929 TO 20151028;REEL/FRAME:036952/0190

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MCCALL, JAMES A.;BAINS, KULJIT S.;SIGNING DATES FROM 20170613 TO 20170621;REEL/FRAME:042779/0379

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4