TWM504425U - 具有定位層之金屬圖案結構 - Google Patents

具有定位層之金屬圖案結構 Download PDF

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TWM504425U
TWM504425U TW103220302U TW103220302U TWM504425U TW M504425 U TWM504425 U TW M504425U TW 103220302 U TW103220302 U TW 103220302U TW 103220302 U TW103220302 U TW 103220302U TW M504425 U TWM504425 U TW M504425U
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layer
metal
metal pattern
pattern structure
positioning
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TW103220302U
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Babak Radi
Tzu-Wen Chuang
Shih-Hong Chen
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Wistron Neweb Corp
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Priority to TW103220302U priority Critical patent/TWM504425U/zh
Publication of TWM504425U publication Critical patent/TWM504425U/zh
Priority to US14/825,184 priority patent/US9385084B2/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

具有定位層之金屬圖案結構
本創作是關於一種具有定位層之金屬圖案結構。
隨著科技進步，可攜式電子裝置例如智慧型手機、平板電腦、筆記型電腦等，變得更為輕巧而易於攜帶。為了微型化以及裝置的小巧與效率，可攜式電子裝置多包含複雜的電路、天線結構以及各種不同電子元件。
本創作提供一種具有定位層之金屬圖案結構。所述定位層乃位於所述金屬圖案結構之所述預定區域內，且直接位於所述預定區域內的所述金屬圖案結構之金屬層表面上。
本創作提供一種金屬圖案結構，包括金屬圖案、定位層與有機保護層。所述金屬圖案具有第一金屬層與位於所述第一金屬層上之第二金屬層。所述定位層位於所述金屬圖案之預定區域內，且直接位於所述預定區域內的所述金屬圖案的所述第二金屬層表面上。所述有機保護層位於所述金屬圖案的表面上，所述有 機保護層包覆住沒有被所述定位層覆蓋住的所述第二金屬層表面。
依照本創作實施例，所述第一金屬層包括銅層，而所述第二金屬層包括鎳層。
依照本創作實施例，所述金屬圖案結構包括天線圖案結構，所述定位層可為金(Au)層或導電有機保焊劑(Conductive Organic Solderability Preservatives)層。
依照本創作實施例，所述預定區域內的所述第二金屬層表面被有機保護層覆蓋，以雷射將特定區域移除後，未被有機保護層覆蓋之第二金屬層圖案區域後續可以化學浸鍍方式形成金層。所述第二金屬層上之有機保護層是以浸塗、噴灑塗佈、旋轉塗佈、浸漬塗佈、網版印刷、移印或塗抹等方式塗佈至第二金屬層表面。
依照本創作實施例，所述有機保護層可包括防焊油墨、硫醇類化合物、或其它可被雷射移除之有機化合物。
依照本創作實施例，先利用雷射處理將欲形成圖案區域處理，確保化學鍍製程中定位層形成在預定位置，故製得定位層圖案精確度良好，使得後續銲接對準度提升，電子元件連接的可靠性會更好。而未經雷射處理區域不會上鍍，避免浪費化學鍍液而進一步節省生產成本。
為讓本創作能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧金屬圖案結構
110‧‧‧基板
120‧‧‧金屬圖案
122‧‧‧銅層
124‧‧‧鎳層
130‧‧‧有機保護層
140‧‧‧定位層
200‧‧‧銲料
300、310‧‧‧被動元件
A、B‧‧‧雷射處理區域
圖1A-1E為依照本創作一實施例於金屬圖案結構上局部形成定位層與焊接被動元件的製作步驟剖面示意圖。
圖2是依照本創作實施例之金屬圖案結構的俯視示意圖。
本創作提供金屬圖案結構與其製造方法。金屬圖案結構 包括直接形成於金屬圖案局部表面上的定位層。透過雷射處理，將金屬圖案層上特定區域之有機保護層移除，而後經化學鍍製程於金屬圖案表面上之預定區域形成一定位層。雷射處理可以直接在第二金屬層圖案的表面上之有機薄層，依照預定圖案針對預定區域進行局部移除，而未經雷射處理之區域在後續化學鍍製程中不會形成金層。因此，透過此製造方式，在金屬圖案表面上之預定區域以化學鍍形成出具有精準圖案、邊界分明的局部定位層。
此處金屬圖案可以是含鎳金屬疊層材料。
圖1A-1E為依照本創作一實施例於金屬圖案結構上形成定位層的製作步驟剖面示意圖。
首先，請參照圖1A，提供一基板110，其上表面具有一金屬圖案120，該基板110可為聚合物基材、塑膠材料或金屬殼體乃至電路板，該基板110可為電子裝置的一或多個部件，且電子裝置可例如為智慧型電話或平板型電腦，而金屬圖案120可為併入於電子裝置內的天線部件或三維電路。本實施例的金屬圖案120可以是單層金屬圖案或包括多層金屬層的天線圖案，本實施例的金屬圖案120可由連續圖案或不連續圖案構成。金屬圖案120例如是銅層 122與鎳層124疊層所構成的天線圖案，銅層122為由銅或銅合金所構成6-20微米厚度的銅層圖案，而鎳層124為3-8微米厚度的鎳圖案。金屬圖案120覆蓋有一層有機保護層130，有機保護層130的材料可為防焊油墨、硫醇類化合物、或其它可被雷射移除之有機化合物。
該有機保護層130例如是透過噴灑塗佈、旋轉塗佈、浸漬塗佈、網版印刷、移印或塗抹而在該金屬圖案120表面上所形成的保護層。一般而言，可以雷射處理將特定區域之有機保護層移除。
參見圖1B與圖2，移除有機保護層130的一部分來形成圖案開口S。舉例而言，可以利用雷射處理步驟來移除部分有機保護層130。然後在圖案開口S內形成定位層140，可利用例如化學鍍製程來形成定位層。
此實施例中，進行雷射處理步驟來處理有機保護層130之預定區域A&B，將預定區域內A&B的有機保護層130去除(形成圖案開口S)而露出其下金屬圖案120的鎳層124表面。前述雷射處理過程中，雷射會將處理區域內的有機保護層移除，並留下被雷射處理過之有機保護層殘留物。定位層形成步驟中所使用的雷射的類型取決於有機保護層130的材質。雷射處理步驟中所使用的雷射可例如為波長1064微米的紅外線(IR)雷射。被雷射局部移除之有機保護層上形成的圖案開口相當精確，更可精確地控制後續形成定位層的位置及形狀。而沒有被雷射處理的區域的部份仍被有機保護層130所覆蓋而與外在環境隔離，因此，在後續要進行化學鍍處理的程序中，金屬圖案120表面的其它位置(亦即非預定區域)，由於受到有機保護層130的隔離，故不會與化學鍍液產生反應。在 雷射處理步驟後，將僅部分被有機保護層130覆蓋的金屬圖案120浸於化學鍍液中以進行化學鍍金製程，而在預定區域A&B內、在圖案開口S所暴露出金屬圖案120之鎳層124上形成定位層140。至此，金屬圖案結構10包括金屬圖案120、有機保護層130以及直接形成於金屬圖案120局部表面上的定位層140。
以此實施例而言，化學鍍金製程是以未被有機保護層保 護之鎳層充當化學鍍的晶種圖案，所以定位層140準確地形成於預定區域A&B的分佈區域。事實上，定位層140可作為焊墊。以此化學鍍金製程為例，所形成的定位層140例如為具有20~80微米厚度的金圖案，其表面略高於有機保護層表面。本實施例的定位層140為分別位於預定區域A&B、不連續的兩金質焊墊。
此處，也可視為定位層選擇性鍍於金屬圖案120之局部區域上。因此，本創作透過雷射與有機保護層之搭配使用能於金屬圖案120的局部區域內選擇性地鍍上定位層而無需將金屬圖案120的整個表面鍍上金，除了可以節省材料成本外，更避免過度繁瑣製程或過多額外模具。
具體而言，由於利用雷射處理與有機保護層，將欲形成圖案區域活化，確保化學鍍製程中定位層形成在預定位置，故形成定位層圖案精確度良好。而未處理區域不會上鍍，不會浪費化學鍍液的用量，可以進一步節省成本。
藉由使用雷射，所獲得的定位層可具有極精確的圖案輪廓。且由於雷射處理可因應於不同金屬材料的外型或結構，所以定位層可準確地形成於平坦表面上或非平坦物件上方。
繼續參見圖1C-1E，利用噴塗、點錫或印刷等方式，填入 一銲料200於預定區域A&B之定位層140上。接著以表面黏著技術(Surface Mount Technology,SMT)將被動元件300與310分別固著至預定區域A&B之定位層140的銲料200上。然後，迴銲銲料200，將銲料200熔融，而將被動元件300與310牢固黏結至預定區域A&B之定位層140。值得注意的是，由於熔融之銲料200會自動侷限於定位層140之圖案區域內，而不會移動或溢流至定位層140之區域外，有自動對準或矯正銲料之對位精度不足之功能，也因此減輕或改善被動元件300與310銲接偏移之狀況。更進而提高元件與銲料之間的接合性，增強元件結合可靠度。被動元件300與310例如是電容器、電阻、電感。
圖2是依照本創作實施例位於金屬圖案上的定位層結構 之俯視示意圖。圖2僅顯示金屬圖案結構與其上的定位層之一部分。圖2所示金屬圖案結構乃是天線結構的一部分，天線結構可以是磁感應天線，或是近場通訊(Near-Field Communications，NFC)天線，其大小及形狀可視其設計而調整。此實施例中，金屬圖案120的總厚度可小於約500微米；較薄的金屬天線結構適用於可撓基板，能被添加至行動裝置周邊設備。
圖2之金屬圖案結構10類似於前述實施例所述(參見圖 1B)，金屬圖案結構10包括金屬圖案120、有機保護層130以及直接形成於金屬圖案120局部表面上的定位層140。此處，參見前述實施例可以理解，金屬圖案120例如是銅層122與鎳層124疊層所構成的天線圖案，銅層122為由銅或銅合金所構成6-20微米厚度的銅層圖案，而所述第二金屬層為3-8微米的鎳層圖案金屬圖案120表面上覆蓋有一層有機保護層130。由於有機保護層130很薄，為顯示 定位層140與金屬圖案120之相對位置配置等，在圖2中省略繪出有機保護層130；不過，有機保護層130之配製乃是覆蓋定位層140位置以外之金屬圖案120表面。而在預定區域A&B內金屬圖案120上的定位層140例如為具有20~80微米厚度的金圖案，但其表面略高於有機保護層表面。本實施例的定位層140為分別位於預定區域A&B、不連續的兩金接觸墊。
相較於傳統製程中將金屬圖案全部鍍上的定位層之結構，本創作之定位層僅局部位於金屬圖案層表面上，而可用以限制後續焊接時銲料分布區域，提高銲接對準度與可靠度。此外，避免大區域或全面鍍金除節省成本外，局部選鍍定位層可防止銲料溢流，限制銲料流動而有自動對準或調整減輕非預期偏移之功能。
本創作所提供的金屬圖案結構包括直接形成於金屬圖案局部表面上的定位層，其適用於通訊產業或可攜式電子產品。
雖然本創作已以實施例揭露如上，然其並非用以限定本創作，任何所屬技術領域中具有通常知識者，在不脫離本創作的精神和範圍內，當可作些許的更動與潤飾，故本創作的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧金屬圖案結構
110‧‧‧基板
120‧‧‧金屬圖案
140‧‧‧定位層
A、B‧‧‧雷射處理區域

Claims (10)

  1. 一種具有定位層之金屬圖案結構，包括：金屬圖案，所述金屬圖案具有第一金屬層與位於所述第一金屬層上之第二金屬層；有機保護層，位於所述金屬圖案的表面上，所述有機保護層包覆住一預定區域之外的所述第二金屬層表面；以及定位層，位於所述預定區域內且直接位於所述預定區域內的所述金屬圖案的所述第二金屬層表面上。
  2. 如申請專利範圍第1項所述的金屬圖案結構，其中所述第一金屬層包括銅層，而所述第二金屬層包括鎳層。
  3. 如申請專利範圍第1項所述的金屬圖案結構，其中所述第一金屬層為由銅或銅合金所構成6-20微米厚度的銅層圖案，而所述第二金屬層為3-8微米厚度的鎳層圖案。
  4. 如申請專利範圍第1項所述的金屬圖案結構，其中所述金屬圖案包括天線圖案結構。
  5. 如申請專利範圍第4項所述的金屬圖案結構，其中所述定位層包括金層。
  6. 如申請專利範圍第5項所述的金屬圖案結構，其中所述預定區域內的所述第二金屬層表面具有被雷射處理過之有機保護層殘留物。
  7. 如申請專利範圍第1項所述的金屬圖案結構，其中所述有機保護層包括防焊油墨、硫醇類化合物、或其它可被雷射移除之 有機化合物。
  8. 如申請專利範圍第1項所述的金屬圖案結構，更包括至少一被動元件固著於所述定位層之上。
  9. 如申請專利範圍第8項所述的金屬圖案結構，更包括銲料位於所述定位層上且位於所述被動元件與所述定位層之間，而將所述被動元件固著於所述定位層之上。
  10. 如申請專利範圍第8項所述的金屬圖案結構，其中所述被動元件包括電容器、電阻或電感。
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