TWM359156U - Level converter for low voltage operation - Google Patents

Description

M359156 V. New description: [New technical field] This is a voltage level converter for low input voltage, especially using a first inverter, a second inverter, and a third An inverter, a current mirror circuit, a first switching transistor, a second switching transistor, a control transistor, and a pull-down transistor for obtaining a precise voltage level. Conversion and low power consumption Electronic circuit. _·. [Prior Art] • The voltage level converter is an electronic circuit used to communicate the signal transmission between different integrated circuits (Integrated Circuits, 1C). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level to a peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low voltage operation signal into a high voltage operation signal. . ' ' Fig. 1 shows a prior art latch-type potential converter circuit using a first PMOS (P-cliaimel metal oxide semiconductor) transistor (MP1) a second PMOS transistor (MP2), a first metal 〇xide semiconductor 'N-channel metal oxide semiconductor' transistor (MN1), a second stomach still transistor (MN2), and an inverter (INV) To form a potential converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the potential of the input voltage (v(IN)) is also at the ground ( GND) is between the second high potential voltage (VDDL). The input voltage (V(IN)) and the anti-ruth phase input voltage signal that is rotated by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NM 〇s transistor (MN2) (gate). Therefore, at the same time, only one of the first nm 〇S transistor (MN1) and the second NMOS transistor can be turned ON. In addition, due to the cross-coupied manner of the first pm 〇S transistor (MP1) and the second PMOS transistor (MP2), when the output of the potential converter is in a stable state, the latch type There is no static current generated in the potential converter. In particular, when the first NMOS transistor (MN1) is turned off (〇FF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down _丨doWn) And causing the first PMOS transistor (MP1) to be turned on, so as to pull up (pUu Up) the gate potential of the second pMOS transistor (Mp2) to turn off the second PMOS transistor (MP2); further, when the first NMOS is When the crystal (MN1) is turned on and the second MN8 transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and 3 M359156 turns on the first PMOS transistor (MP2). The gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there is no current between the first PM〇s transistor (MP1) and the first Ncvios transistor_丨 or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2). path. However, the above conventional potential converter is in the process of: PM〇s transistor (MP2) approaching (or turning off) and in the process of: NMOS transistor (MN2) approaching off (or turning on), The pull-up and pull-down of the potential on the output node (〇υτ) have a competing (contenti〇n) phenomenon, so the output voltage signal '(V(0UT)) is slower when it transitions to a low potential. Further, considering that when the input voltage (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the PMOS transistor (MP2) becomes low, so that The two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, since volts cannot be instantaneously converted to 18 volts, the lower input voltage (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second pM 〇s transistor (MP2). The first NMOS transistor (MN1) and the second MN8 transistor (MN2) are fully turned on or completely turned off, which causes a quiescent current between the first high potential voltage (VDDH) and the ground (GND). (static current), this quiescent current increases the power loss. Furthermore, the performance of the latch type potential converter is affected by the first high potential voltage (yDDH), since the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The first high potential voltage (VDDH), and the gate-source voltage of the first: NM〇S transistor (MN1) and the second NM〇s transistor_2) is the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) which can make the latch type potential conversion φ device operate normally is limited. 'Fig. 2 shows another mirror type potential converter circuit of another prior art, which connects the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) by - And connected to the pole of the first PMOS transistor (MP1), so that the first pm 〇S transistor (Μρι) and the second pM 〇s 曰曰 body (MP2) form a current mirror circuit, the first PMOS transistor ( MP1) is in a saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Equally equal. Since the performance of the mirror type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor stomach, the potential converter is changed even if the output first high potential voltage (VDDH) is changed. The performance will not change much. Therefore, the mirror type potential converter can be applied to various output voltage circuits. However, when the first NMOS transistor (MN1) is turned on and the second nm 〇s transistor (face 2) is turned off, the gate potential of the 4 M359156 first PMOS transistor (MP1) and the PMOS transistor (send) Pulled down so that both the first PMOS transistor (MP1) and the PM: PM transistor (Mp2) are turned on. Thus, a quiescent current path is generated between the first brain _) and the -NM 〇S transistor_1}. The main purpose of this creation is to propose a novel structure of voltage level converter, which can not only accurately and quickly drive the 帛-信信县—_二钱, and . Like a pressure sheep [new content] This creation proposes a voltage level converter for low input voltage, which is composed of a first inverter (II), a second reverse phase H (I2), a first a three-inverter (9), a current mirror circuit (1), a first switching transistor (2), a second switching transistor (3), a control transistor (4), and a pull-down transistor (7) in the group 1 An inversion _) is used to control the conduction (〇n) or turn off of the first switching transistor (2) (mail, the first, the inverter (12 to control the conduction of the second switching transistor (3) (4) Or the third inverter (9) is used to control the conduction (〇n) or the off (〇) of the control transistor (4); the current mirror circuit (1) is used as a voltage level control; the control transistor (4) Is used to control the conduction or shutdown of the current mirror circuit (1), so as to effectively reduce the power compensation; and the pull-down transistor (3) gamma provides a path to pull the potential of the output (OUT) to ground (gnd It is confirmed by the simulation results that 'the voltage level level converter for low input voltage proposed by this creation can be accurately and quickly 鄕---------------------- The number of transistors used alone is more important than the miniaturized shirts of the device, and the power is effectively reduced. [Embodiment] According to the purpose of the tenth, the present invention proposes a voltage level for a low input voltage. The converter, as shown in Fig. 3, is composed of - a first inverter (11), a second inverter (9), a third inverter (9), a current mirror circuit (1), - the first a switching transistor (2), a second switching transistor (3), a control transistor B, and a -^lowering transistor (5); wherein the first inverter (11) is adapted to receive the wheel ^;^ (V(IN)) signal 'and controls the conduction (four) or off (four) of the first switching transistor (7); the second inverter (12) is used to provide the inverse of the second input (thin) Phase signal, and controlling the second switching transistor (3) to pass (four) or turn off the third inverter (13) to invert the second node (10) - output signal, 5 M359156 and control the control transistor ( 4) conduction (four) or off (〇 ff); the current mirror circuit (1) is used for voltage level control 'the system of - PMOS transistor (Mpl) and a third pM 〇s transistor (Mp3) Forming, wherein the source of the first PMOS transistor (MP1) is connected to the first high potential voltage, and the gate and the gate are connected to the first node (N1) and the gate of the third pMOS transistor (MP3) a source of the third PMOS transistor (MP3) connected to the first high potential voltage (ydDH), a gate connected to the gate and the drain of the first PMOS transistor (MP1) and the first node (7) 丨), and its drain is connected to the second node (N2); the first switching transistor (2) is composed of a first NMOS transistor (MN1), = source '·-pole and The source of the second transistor (MN2) is connected to ground (GND), the gate is used to accept the inversion voltage of the voltage (V(IN)), and the drain is connected to the first node (10). The second switching transistor (3) is composed of a second NMOS transistor (MN2) whose source is connected to the source of the first NMOS transistor (MN1) to ground (GND), and its gate An inverted voltage signal for receiving the second input terminal (bile), and a drain electrode connected to the first node (N1); the control transistor system is used to control the conduction (4) or _ of the current mirror circuit (1) _) '· Its system tM (Mp2) is composed of Connected to the first high potential voltage (VDDH), its gate is connected to the output (OUT), and its drain is connected to the gate of the first pM〇s transistor (MP1) and the third PMOS transistor (MP3) The gate phase is connected to the first node...丨);= When the control transistor (4) is turned on, a first high potential voltage (VDDH) can be supplied to the gate of the first pM〇s transistor (MP1) and The gate of the third PM0S transistor (MP3), which can reduce the leakage current on the third pM〇s transistor (MP3) to reduce the power consumption of the voltage level converter; and the pull-down transistor (5) Used to provide a discharge path to pull the potential of the output (OUT) to ground (GND); it consists of a • third NMOS transistor _3) whose source is connected to ground (GND) Its gate is used to receive the inverted voltage signal of the second input (_), and its drain is connected to the second node (^2). • Please refer to Figure 3 again. Now consider the steady-state operation of the voltage level converter when the input voltage (V(IN)) is low (0 volts): the signal at the first input (IN) is low. The potential, the signal at the second input (INB) is high, such that the first NMOS transistor (MN1) is turned on, at this time, at the first pM〇s transistor (MP1) to the first NMOS transistor (MN1) There will be a current flowing through the current path, and a mirror current will be generated on the third PMOS transistor (MP3); the low potential voltage outputted through the second inverter (9) will be the second NMOS transistor (_2) and The third NMOS transistor (MN3) is turned off, so the mirror current generated by the second PMOS transistor (MP2) pulls the potential of the second node @2) to the first high potential voltage (VDDH), and the output The potential of the terminal (OUT) is pulled down to a low potential, so that the second PMOS transistor (MP2) connected to the wheel terminal (OUT) is turned on, and the first PM〇s transistor (Mpiw 6 M359156 gate and The gate voltage of the third PMOS transistor (MP3) is pulled up to the first high potential voltage (VDDH), so that the leakage current on the third PMOS transistor (MP3) can be reduced. Considering the steady-state operating condition of the electrical waste level converter when the input voltage (V(IN)) is the second high potential voltage (1.8 volts): the signal at the first input (IN) is high, the second input The signal on the terminal (j^b) is low-potential' such that the first NMOS transistor (MN1) is turned off, and at this time, the current path of the first pM〇s transistor (MP1) to the first NMOS transistor (MN1) There will be no current flowing due to the first NM〇s transistor (_ι) being turned off, therefore, no mirror current will be generated on the third PMOS transistor (MP3); and passing through the second inverter (12) The output high potential voltage causes the second NMOS transistor (dirty 2) and the third NMOS transistor _3) to be turned on, since the source of the third NM〇s electric body _3) is grounded (gnd "it is not The pole is connected to the second node _, so the potential of the second node (four) is pulled down to a low potential, and the potential of the output terminal (OUT) is pulled up to a high potential and will be connected to

The transistor (MP2) is turned off. As described on J ^ MUS U, the input voltage (CUT when the V_ is low (〇V)) is the first -3 volts. Thus, the purpose of voltage level conversion is achieved. [Simple diagram of the diagram] 2 shows the circuit diagram of the voltage level converter in the prior art; the circuit diagram of the voltage level converter in the technology#; Fig. 4 shows the input voltage sequence diagram of the preferred embodiment of the present invention; "~ and transient analysis of output voltage signal [main component symbol description] 1 3 5 12 Ν1 current mirror circuit second switch transistor pull-down transistor first inverter first node 2 4 II 13 Ν 2 first Switching transistor control transistor first inverter third inverter second node 7 M359156 MP1 first PMOS transistor MP2 second PMOS transistor MP3 third PMOS transistor MN1 first NMOS transistor MN2 second NMOS Crystal MN3 Third NMOS transistor IN First input INB Second input OUT Output V(OUT) Output voltage V(IN) Input voltage VDDH First high potential voltage VDDL Second high potential voltage

Claims (1)

M359156 Sixth, the scope of application for patent: = kind = in, the voltage level converter of the input voltage, used to convert a first signal into a second letter and a first node (Nl); a second node (N2) a first input terminal (IN) for providing the first signal; a second input terminal (INB) for providing an inverted signal of the first signal; an output terminal (OUT) for outputting the a second signal; a first-supply voltage for providing a first-high potential voltage required by the voltage level converter device (10) a second power supply tilting for providing a second high potential voltage (10) of the voltage level converter device f. The level of the second high potential voltage (VDDL) is less than the level of the first __high potential voltage (five) - the first-inverter (II) 'to accept the round human voltage (v_signal ' and control the conduction (〇n) or off (off) of the first-switching transistor (2); a phase detector (12) for providing an inverted signal of the second input terminal (leg) and controlling the conduction (〇n) or closing of the second switching transistor (3) and the pull-down transistor (5) a third inverter (9) for inverting the output signal of the second node (four) and controlling the on or off of the control transistor (4); a current mirror circuit (1) 'Used as voltage level control; a first-switching transistor (2) consisting of -D-Cong (10) transistor (MN1) whose source is connected to the first NMOS transistor (MN2) The sources are connected together and connected to ground (GND), the gate is used to sense the inverted signal of the input voltage (V(IN)), and the drain is connected to the first node ^; a second switch a transistor (3) consisting of a second nm 〇s The crystal (MN2) is composed of a source connected to the source of the first NMOS transistor (MN1) and connected to the ground (GND), the gate of which is adapted to receive the inversion of the second input terminal (INB) a voltage signal, and its wave is connected to the first node ^; a control transistor (4) for controlling the conduction (〇n) or off (〇 ff) of the current mirror circuit (1), which is The second PM0S transistor (MP2) is composed of a source connected to a first high potential voltage, a gate connected to the output terminal (OUT), and a drain connected to the first pm〇s transistor (MP1) a gate and a gate of the third PMOS transistor (MP3) are connected 'and connected to the first node (7) 1); and a pull-down transistor (5) is provided to provide a discharge path for the output terminal (〇υτ) The potential is pulled down to ground 9 M359156 (GND), which consists of a third NMOS transistor (should be 3) whose source is connected to ground (GND) and whose 汲 = is connected to the second node (N2) And _ is used to receive the inverted voltage signal of the second input terminal. 2. The voltage level shifter for low input voltage according to claim 1, wherein the current mirror circuit (1) Includes: • The first (10) transistor (10) P1) whose source is connected to the first high potential voltage (VDDH), the gate and the drain are connected to the first node _ and the third pM 〇s transistor (Mp3) And the gate of the 'first PM〇S transistor (Mp3)' whose source is connected to the first high potential voltage (VDDH) whose gate is connected to the first PM0S body_1) And the poleless and the first node (10)), and the poleless is connected to the second node (N2). The voltage level shifter for low turn-in voltage as described in the scope of claim 2, wherein the first signal has an amplitude between 〇VV and the second high potential voltage (VDDL). 4. The voltage level shifter for low input voltage of claim 3, wherein the amplitude of the second signal is between 0 volts and the first high potential voltage (VDDH). 5. The voltage level shifter for low input voltage according to claim 4, wherein the voltage source of the first inverter (11) is the second high potential voltage (VDDL). 6. The voltage level shifter for low input voltage according to claim 5, wherein the voltage source of the second inverter (12) is the second high potential voltage (VDDL). 7. The voltage level shifter for low input voltage according to claim 6, wherein the voltage source of the third inverse phase detector (13) is the first high potential voltage (VDDH).