TWM350180U - Level-shifting circuit - Google Patents

Description

-M350180 -8, new description: [New technical field] This creation is related to a voltage level conversion circuit, especially using an inverter (INV), a charging transistor (1), a charging transistor ( 2) A pull-down transistor (3), a pull-up circuit (4) and a pull-down circuit (5), which can quickly and accurately convert the first signal into a second signal electronic circuit. [Prior Art] 'The voltage level conversion circuit is an electronic circuit for communicating signals between different integrated circuits (K:). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level to a peripheral device with a higher voltage level (for example, a 1.8V output to a 3.3V input), the voltage level conversion circuit is responsible for the low voltage. The voltage working signal is converted into a high voltage operating signal.

In the prior art, as shown in FIG. 1, a conventional voltage level conversion circuit includes an input inverter and an output inversion, wherein the input inverter is composed of a first PMOS (P). a -channel metal oxide semiconductor, a transistor (Mpi) and a first NMOS (N-channel metal oxide semiconductor 'N-channel metal oxide semiconductor) transistor (MN1) The phase device is composed of a second pM〇s transistor (mp2) and a second nm〇S transistor (_2). The first PMOS transistor (MP1) is connected to the gate of the first NMOS transistor (MN1) as an input terminal of the input inverter, the first pM〇s transistor _丨) and the first _8 = crystal (MN1) drain connection as the input of the input inverter, the source of the first pM〇s transistor _P1) is connected to the first high potential voltage (VDDH), the first The source of the s-transistor (MN1) is grounded (GND), and the gate of the second PMOS transistor (mp2) and the second bank 8 transistor_2) is connected in parallel as the input of the output inverter. The second PM〇s transistor (Mp2) and the second Li (7) transistor are connected to the fine end of the secret cell, ^PMQS transistor (shun) source, voltage (VDDH) 'second nm〇s The source of the transistor (brain) is grounded. The input inverter ^ input ^ is connected to the input of the output inverter. The first—high potential electric dust (vddh) is a volt-volt, and is a rectangular wave with a G to U volt. Xia V (IN) is a 0 volt crystal (draw D off (〇FF), while the first PM0S transistor _ turn-on _, ί bit ί pull UU butterfly - high potential voltage (VDDH), and the first The high mark will make the second PMOS of the output inverter, and the second 5 M350180 ·- NMOS transistor (MN2) is turned on, therefore, the output of the output inverter is pulled down (four) 丨 to the ground (GND) However, when the input voltage V(iN) is the second high potential voltage (VDDL), the first transistor (MN1) is turned on, and due to the voltage applied to the drain of the first PMOS transistor (MP1). The first-high potential voltage (VDDH) is not reached, so that the first PMOS transistor (MP1) cannot be completely turned off, causing a quiescent current between the first high potential voltage (VDDH) of the input inverter and the ground (GND). (sMic current), this quiescent current increases the power loss. In many applications, the increase in power loss is not desired. Another prior art technique uses a first PMOS transistor (MPi), a a second pM〇s electric crystal (MP2), a first NMOS transistor (MN1), a second transistor (_2), and an inverting ^^(INV) to form a voltage level conversion circuit, such as 2 eyes. Its towel, the 撼 (Please) bias _ = the first = high potential voltage (VDDL) and ground (GND), and the input voltage v (_ potential is also at the ground (_) with the younger potential Between the voltage (VDDL), the input voltage v(IN) and the inverting input signal through the inverted || (er) output are respectively connected to the first NM〇s transistor (MN1) and the second 〇8 The closed-cell port of the transistor (mn2) is at the same time, and only the first one of the first 〇[〇S transistors (na and the upper (10) transistors will be turned on. In addition, the first output ((10)p) and The second output terminal (〇UTB) is connected to the gate of the first PM〇s transistor (ΜΡ1) and the gate of the second pM〇s transistor (MP2), respectively, using a cross-coupled manner. The source of a PM〇stM_) and the source of the second pM〇s transistor (MP2) are connected to a first-high potential, and the source of the transistor (mni) and the second NMOS transistor_2 The source is grounded (GND), and the drain of the first ship (10) crystal (10)^) and the drain of the J^NMOS transistor_2) are respectively connected to the second output terminal (〇utb) and the first output terminal (OUT). The voltage signal after the level conversion is input by the first output terminal, and the inverted power generation signal now considers that the input voltage V(4) is low (0 volts), and the conversion (4) steady state operation is performed. The low potential input MV_ is dedicated to the gate of the first cis (10), so that the NMOS transistor (MN1) is turned off, so the potential of the second output terminal (〇utb) is not changed. And the inversion =_0 transmits the second high potential electric dust (5) to the gate of the second Cong 8 transistor _), so that an NM0S transistor (ΜΝ2) is turned on, at this time at the first output (〇υτ) and There is a Γ 接 connection between the ground (GND) = 'the first output terminal (the OUT position is pulled down to a low potential (〇 volts) steady state value. The pole is connected to the first output _, therefore, the first An output terminal, - is sent to the interpole of the first PMOS transistor (MP1) such that the first PMOS transistor 6 .. M350180 body (MP1) is turned "on" and will be connected to the first pM 〇s electro-crystal (OUTB) The potential is pulled up to the first-high potential voltage (VDM), and the first-output potential voltage _H is transmitted to the second PM 〇Sf crystal 2 = MJ3UTB) On the first output. = surface electric crystal input voltage V (IN) age quasi-conversion conversion H ^ upper series 'low potential input Next, consider the input potential v (four) is the second potential UT) round low signal. Operational situation. The second high potential input voltage ν (& is transmitted to the steady state of the 'level converter, so that the first NMOS transistor (MN1) is turned on, and there is a direct path between the gates of the transistor) At the second output, the steady-state value of the round-out terminal (◦_) and ground (GND) ▲. The phase-transfer low-voltage H-bit is pulled down to - low potential (〇 volt), "crystal _)) = ::==^^^ The crystal (MP2) is turned on, at this time, the gate of the 〇 1 electric ( body (10), so that the second PM 〇 S electric 靡 wheel earns an output

There is a conteniion problem in the provincial known level converter. To give an example, when the volt is changed by _.8 volts, [German crystal (service) is turned on. Therefore, the closed-pole of the 筮-body (MP2) becomes a low potential, so that f: PMOS transistor_2) and a @_(QUT) WiHH high-potential voltage α1TM). However, from the inability to extend to, 13 this, on the lower input voltage side of the conversion class may be the transistor _), the second PM 〇S transistor (MP2), the first ms transistor • high transistor _ ) to achieve full conduction or complete shutdown, which will cause a static current between the first voltage (DDH) and ground (GND), ^UOS^W2MM^^ Thunder 8 transistor_2) In the process of approaching (or turning on), there is a phenomenon of contention for the pull-up and pull-down of the first output (OUT), so the output voltage signal ν(οπ) 7 M350180 • in the transition At a low potential, the speed is slower. In view of this, the main purpose of this creation is to present – contention is fast and precise, and it is still possible to reduce the power loss.帛一w, and can effectively reduce: [New content] This creation proposes a voltage level conversion circuit, which is converted from an inverting 11_), a charging electric 曰 ^ number to a second letter (3), A pull-up circuit (4) and a pull-down circuit ^ 充电 charging power _), a pull-down transistor = input power __ inverting _, its bias is the second high ^ ^ ^ ^ such as the potential of the end w Up to two high power two = (H) and the charging power body (2) is used to use the first output terminal (the nickname drop circuit (5) is used when the potential of the input signal changes, the first The output of the input terminal (8) is reduced to the ground (GND); the first - the same potential voltage _卩, the second high potential voltage DL is ^^, :ΐ •^ a Uu is Corresponding waveforms between 0 volts and 3·3 volts, and two conversion circuits, which can not only quickly and accurately pass the first signal to the first - (four) and can be effective Reduce the competition (_entiGn) phenomenon, and thus reduce the power loss [Embodiment] According to the above purpose, the author proposes a voltage level = electric crystal (2), - pull-down transistor (3), a pull-up circuit (4) And a pull-down circuit (3), wherein the four charging transistor (1) is used to charge the first output terminal (8) to the first high-potential voltage when the input voltage (v_ is a low potential voltage (〇V)) ( 〇〇Η〇〇Η), and first the third pM〇s transistor (^) 8 M350180 -- is turned off, the charging transistor (1) is composed of a first PMOS transistor (MP1), its source - power Electric "(VDDH), its drain is connected to the second output (8), and its gate is connected to the first input (IN); the charging transistor (2) is used at the input voltage (V (IN) ))) when the second high potential voltage (five) sinks, the first output terminal (0UT) is charged in advance, and the charging transistor (2) is composed of a first (10) transistor (MN1) The first - Wei light (VDDH), its secret is connected to the third ^ 曰 (10) transistor (MN3)'s drain and the first output (〇υτ), while the pole is connected to the second round 〇 s transistor turn 2 a gate and a first input terminal (IN); the pull-down transistor (3) is used to quickly pull the potential of the first output terminal (ουτ) when the input voltage is a low potential voltage (〇 volt) Down to ground (gnd), the pull-down The body (3) is composed of a -4 nm 〇s transistor _4), the source of which is connected to the ground, and the pole is connected to the iij terminal (OUT), and the third phase (10) transistor is formed by the compensation. Turning to 3) and the second input terminal, the pull-up circuit (4) is used to pull the potential of the first output terminal (OUT) or the second output terminal (X) to the first time when the potential of the input signal changes. a high potential voltage (vddh), the pull-up circuit (4) is composed of a first pm 〇S transistor (MP2) and a third pm 〇S transistor (MP3) 'the first MOS transistor (MP2) The source is connected to the first power supply voltage (5), and the pole is connected to the drain of the first PMOS transistor (MP1), the drain of the second Radisson 8 transistor (MN2), and the third OS transistor (MP3). a gate for rotating the inverted signal of the second signal, and a gate connected to the source of the first NMOS transistor (MN1), the gate of the third pM〇s transistor (Mp3), The third salt 〇 § the transistor (deleted) of the pole and the fourth view 08 transistor to 4) the drain, and for outputting the second signal; and the source of the JMOS transistor (MP3) is connected to the a power supply voltage (VDDH) whose drain is connected to the jPljNMOS transistor The source of (MN1), the idle pole of the second 〇8 transistor _2), the immersion of the third 〇8 electrocardiographer ^), and the bungee of the fourth employee 08 transistor (MN4) The second signal is output, and the gate thereof is connected to the drain of the first PMOS transistor (MPi), the drain of the :pM〇s transistor (Mp2), and the first: NM〇S transistor (MN2) a stepless output signal for outputting the second signal; the pull-down circuit (5) is for using the first output terminal (〇υτ) or the second output terminal when the potential of the input signal is recorded ( The potential of the 拉) is pulled down to the ground (GND), and the pull-down circuit (7) is composed of a second 〇8 transistor (cis 2) and a second NMOS transistor (ΜΝ3), the second _8 The source of the transistor (_2) is connected to the ground (GND), the drain of the transistor is connected to the drain of the first PM〇s transistor (_), the second pole of the second pM〇s transistor (Μρ2), a gate of the SPMOS transistor (MP3) for outputting an inverted signal of the second signal, and a gate connected to the gate of the first NM〇S transistor (μν!) and the first input terminal (taken And the source of the third NMOS transistor (_3) is connected to the ground (GND), and the drain is connected to An NMOS transistor M350180 • the source of (MN1), the closed end of the second PMOS transistor (MP2), and the drain of the fourth thin 8 transistor _4) = body (·3) _) the gate and the second input terminal == Ξ = Γ = road T second high potential electric climbing dl), the second j ==: r =: ==:: estrus = ill ill pressure low At the potential (0 volts), the low-potential on the steady-state operation of the voltage level conversion circuit is simultaneously transmitted to the input terminal of the inverter )os transistor (MN1), the second gate a closed pole of the 电8 transistor (MN2) and a gate of the first p(10) electrode body (MP1) such that the first wrist (four) crystallizer "and the second should be turned off, the first PMOS transistor _) is turned on, and The second output terminal (χ) is charged |) before the 0S transistor _) is turned on, the potential of the second round of the output terminal (8) is pulled up to a first high voltage = DH), and the first high potential voltage (VDDH) Transmitted to the third ρ, the transistor _ then pole, t the second PMOS transistor (MP3) is turned off, and the inverter (Teng) transmits the second high potential voltage (Lion l) Thai j second Shun S transistor _ 3) and the gate of the fourth _8 transistor _4), such that the third NMOS per crystal (MN3) and the fourth NM 〇S _ unblock, so ^ quickly pulls down to - low potential (the steady state value of _, the first - output (〇u == 3 = to the first PMOSf: the gate of the crystal (MP2), so that: pM〇 The s transistor (Mp2) is turned on, so the potential of the -output terminal (X) will remain at the first high potential county (VDDH), and the first potential will be turned to low impurity (0 impurity). In a word, electric hard is low.) • The over-conversion conversion is converted into a low-potential (〇V) output signal, which is the second highest by the first _ flip (〇H ... and then the input electric house (V (four)) When the potential voltage (1.8 volts) is used, the voltage level is changed to the state. The second high potential on the first input terminal (IN) is reversed to pass the inverting terminal, the first NMOS transistor (MN1). ) the gate, the second read 电 8 transistor (the gate of the PMOS and PMOS transistor), so that the first pM〇s transistor (Μρι) NM〇S transistor (MN1) and the second nm 〇S transistor_2) is turned on, so that the first power supply voltage is first charged to the VDDH-Vth through the first transistor_1} before the third pM〇10 M350180 and (MP3) are turned on. (Vth is the threshold voltage of the NMOS transistor), and causes the second PMOS transistor (MP2) to be turned off, and since the second NMOS transistor (MN2) is turned on, the second output terminal (X) The potential is pulled down to a low potential (0 volts), which is transferred to the gate of the third pM〇s transistor (MP3), causing the third PMOS transistor _3) to be turned on, at this time, the first output (〇υτ) potential is rapid Raising to the first-high potential voltage, and the inverter transmits the low-potential voltage to the gates of the second NMOS transistor (3) and the fourth NMOS transistor (ΜΝ4), so that the third 〇 § Both the crystal_3) and the fourth nm〇S transistor_4) are _, and therefore, the electric potential of the first output terminal is maintained at the first high potential (VDDH). In a word, the input voltage (when the second high potential voltage potential = Γ., input ^ chat) is low (〇 volt), the output power _)) is also low to the first potential 赖 3.3 volts ). Thus, the purpose of the voltage level conversion - the result of the Spice transient analysis of the voltage level conversion circuit proposed by if Γ, such as the first ==, the quasi-result can confirm the electric phenomenon of the electric phenomenon In turn, the power loss is reduced. This effectively reduces the face of her)

[Creation effect] The electric balance machine circuit proposed by this creation has the following effects · and favorable to his transmission and delivery * less 'saki high accumulation degree, (2) horse accuracy: the electric position proposed by this creation Quasi-land #^人录之杂, the age of wealth and the turn of the Gu, can indeed be accurate () to reduce the competition problem: because the creation is in the loss: ^ two rounds _) charge _- high · series 2 = = bit =), in advance Will be closed first, Ling _ difficult __ (10) Butterfly == = = 11. M350180 One output (0UT) charging 'This can reduce the competition phenomenon at the first output (OUT). Shike titit!1 exposes and reduces the best practice of the series, but the people of this technology in the county have no change in the form or details of the details. Because of the changes in the relevant technical norms, all of the changes are included in the patent application of this creation.

12 M350180 [Simple description of the drawing] Fig. 1 is a circuit diagram showing a voltage level conversion circuit in the first prior art; Fig. 2 is a circuit diagram showing a voltage level conversion circuit in the second prior art. The circuit diagram of the Longguanguan circuit, · Figure 4 ^ Lin _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Input terminal V(OUT) first output voltage OUT first output terminal X second output terminal MP1 first PMOS transistor MP2 second PMOS transistor MP3 third PMOS transistor MN1 first NMOS transistor MN2 second NMOS transistor MN3 third NMOS transistor MN4 fourth NMOS transistor vddl second high potential voltage VDDH first high potential voltage 13

Claims (1)

M350180 'Nine, the scope of application for patents: !·1, = level conversion circuit, receiving - first - weaving into - second money, including: a first input (IN) to provide - input voltage signal a second input (INB) 'Xiao provides an inverted input " voltage signal; a first output (OUT) for outputting the second signal; - a second output (X), For outputting the inverted signal of the second signal, the H source voltage ' is used to provide the first high potential M(vddh) required by the voltage level conversion circuit; ^: the electric "pressure" is used to provide the cage level conversion The second high potential electric second pure bit voltage (VDDL) required by the circuit is less than the first high potential voltage (the level is taken; the inverter (INV) is used to provide - and input The signal in which the voltage signal is inverted is connected to the first input terminal (IN)' and its output is connected to the second input terminal (inb); the electric transistor (1)' is electrically connected by a first PM?s The crystal is composed of ρι), the source of which is connected to the first-electrode potential (VDDH) 'the drain is connected to the second output (χ), and the gate is connected to the input (IN) -, an electro-op crystal (2) consisting of a -first nm〇s transistor (MN1) with its source connected to the first-high potential (VDDH), the secret connected to the three-sided 〇8 The crystal (dirty 3) is brewed and the first output (out)' and its gate is connected to the gate of the second surface 08 transistor (MN2) and the first terminal (IN); a pull-down transistor (3) ), which is composed of a fourth NMOS transistor (MN4) whose source is connected to ground φ (GND), its drain is connected to the first output terminal (〇υτ), and its gate is connected to the first The inter-electrode of the transistor (ΜΝ3) and the second-in terminal (inb); the pull-up circuit (4)' is used to change the first output (out) or the first when the potential of the input signal changes. The potential of the two output terminals (X) is pulled up to the first high potential voltage (VDDH); and a pull-down circuit (5)' is used to change the potential of the input signal to the first output terminal (〇u or The potential of the first-second output terminal (X) is pulled down to the ground (GND). The voltage level conversion circuit according to claim 1, wherein the pull-up circuit (4) comprises: a second PMOS transistor (MP2) 'The source is connected to the first high a potential voltage (VDDH) connected to the drain of the first PMOS transistor (MP1), the drain of the second NMOS transistor (_2), and the gate of the third PMOS transistor (MP3) for output The second signal is inverted, and the open electrode is connected to 14 M350180' to the source of the first NMOS transistor (MN1) and the third PMOS transistor (MP3) of the germanium transistor (L3) And a drain of the fourth NMOS transistor (Li 4) for outputting the second signal; and a second PMOS transistor (MP3) whose source is connected to the first high potential voltage (VDDH), The drain is connected to the source of the first NMOS transistor (MN1), the gate of the second PMOS transistor (Mp2), the drain of the third NMOS transistor (_3), and the NMOS of the fourth NMOS transistor (_4). a pole for outputting the second signal, and a gate connected to the drain of the first PMOS transistor (MP1), the drain of the second pmos transistor (MP2), and the second NMOS transistor (_2) Infinitely, and for outputting the inverting-signal of the second signal. 3. The voltage level conversion circuit of claim 2, wherein the pull-down circuit (5) comprises: repairing a second NMOS transistor (MN2) 'having its source connected to ground (GND), The drain is connected to the > pole of the first pmos electrical aa body (MP1), the drain of the first PMOS transistor (MP2), the gate of the third PMOS transistor (MP3), and is used for outputting the second signal Inverting the signal, and its gate is connected to the gate of the __Nm〇s transistor (MN1) and the first input terminal (IN); and a third NMOS transistor (MN3) 'the source is connected to the ground (GND), the drain of which is connected to the source of the first NM〇s transistor (MN1), the gate of the second PMOS transistor (MP2), and the third pM〇s transistor (]^3); And a drain of the fourth NMOS transistor (MN4) for outputting the second signal, and a gate connected to the gate of the fourth NMOS transistor (_4) and the second input terminal (_). 4. The voltage level conversion circuit of claim 1, wherein the amplitude of the first signal is between 〇V and VDDL. 5. The voltage control circuit of claim 4, wherein the second trust amplitude is between volts volts and the first high potential voltage (VDDH). 6. The voltage scale conversion circuit of claim 5, wherein the power supply voltage of the reverse phase correction is the second high potential voltage (VDDL). 15