TWI814944B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Adhesive Tapes (AREA)
- Die Bonding (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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WOPCT/JP2018/042551 | 2018-11-16 | ||
PCT/JP2018/042551 WO2020100308A1 (ja) | 2018-11-16 | 2018-11-16 | 半導体装置及びその製造方法、並びに半導体装置の製造に使用される構造体 |
Publications (2)
Publication Number | Publication Date |
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TW202038425A TW202038425A (zh) | 2020-10-16 |
TWI814944B true TWI814944B (zh) | 2023-09-11 |
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TW108141611A TWI814944B (zh) | 2018-11-16 | 2019-11-15 | 半導體裝置及其製造方法 |
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JP (1) | JPWO2020100998A1 (ko) |
KR (1) | KR102703891B1 (ko) |
CN (1) | CN113039641A (ko) |
SG (1) | SG11202104932XA (ko) |
TW (1) | TWI814944B (ko) |
WO (2) | WO2020100308A1 (ko) |
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JPWO2022004849A1 (ko) * | 2020-07-03 | 2022-01-06 | ||
WO2022034854A1 (ja) * | 2020-08-11 | 2022-02-17 | 昭和電工マテリアルズ株式会社 | 半導体装置及びその製造方法 |
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US20130049228A1 (en) * | 2011-08-31 | 2013-02-28 | Samsung Electronics Co., Ltd. | Semiconductor package having supporting plate and method of forming the same |
US20150054169A1 (en) * | 2012-12-20 | 2015-02-26 | SK Hynix Inc. | Stack packages having token ring loops |
US20150200187A1 (en) * | 2014-01-16 | 2015-07-16 | Chul Park | Semiconductor package including stepwise stacked chips |
TW201705429A (zh) * | 2015-07-31 | 2017-02-01 | 愛思開海力士有限公司 | 堆疊封裝以及製造該堆疊封裝的方法 |
TW201730990A (zh) * | 2015-09-25 | 2017-09-01 | 英特爾公司 | 用以互連封裝積體電路晶粒之方法、設備及系統 |
US20180211936A1 (en) * | 2017-01-25 | 2018-07-26 | Powertech Technology Inc. | Thin fan-out multi-chip stacked package structure and manufacturing method thereof |
TW201830654A (zh) * | 2016-10-28 | 2018-08-16 | 愛思開海力士有限公司 | 具有不對稱晶片堆疊結構的半導體封裝 |
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US6930378B1 (en) * | 2003-11-10 | 2005-08-16 | Amkor Technology, Inc. | Stacked semiconductor die assembly having at least one support |
JP2010147225A (ja) * | 2008-12-18 | 2010-07-01 | Renesas Technology Corp | 半導体装置及びその製造方法 |
KR20110041301A (ko) * | 2009-10-15 | 2011-04-21 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
KR20120093725A (ko) * | 2011-02-15 | 2012-08-23 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
KR101906269B1 (ko) * | 2012-04-17 | 2018-10-10 | 삼성전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
JP2015120836A (ja) | 2013-12-24 | 2015-07-02 | 日東電工株式会社 | 接着フィルム、ダイシング・ダイボンドフィルム、半導体装置の製造方法及び半導体装置 |
US9418974B2 (en) * | 2014-04-29 | 2016-08-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with support members and associated systems and methods |
-
2018
- 2018-11-16 WO PCT/JP2018/042551 patent/WO2020100308A1/ja active Application Filing
-
2019
- 2019-11-14 JP JP2020556180A patent/JPWO2020100998A1/ja active Pending
- 2019-11-14 SG SG11202104932XA patent/SG11202104932XA/en unknown
- 2019-11-14 KR KR1020217017011A patent/KR102703891B1/ko active IP Right Grant
- 2019-11-14 CN CN201980074797.0A patent/CN113039641A/zh active Pending
- 2019-11-14 WO PCT/JP2019/044761 patent/WO2020100998A1/ja active Application Filing
- 2019-11-15 TW TW108141611A patent/TWI814944B/zh active
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US20130049228A1 (en) * | 2011-08-31 | 2013-02-28 | Samsung Electronics Co., Ltd. | Semiconductor package having supporting plate and method of forming the same |
US20150054169A1 (en) * | 2012-12-20 | 2015-02-26 | SK Hynix Inc. | Stack packages having token ring loops |
US20150200187A1 (en) * | 2014-01-16 | 2015-07-16 | Chul Park | Semiconductor package including stepwise stacked chips |
TW201705429A (zh) * | 2015-07-31 | 2017-02-01 | 愛思開海力士有限公司 | 堆疊封裝以及製造該堆疊封裝的方法 |
TW201730990A (zh) * | 2015-09-25 | 2017-09-01 | 英特爾公司 | 用以互連封裝積體電路晶粒之方法、設備及系統 |
TW201830654A (zh) * | 2016-10-28 | 2018-08-16 | 愛思開海力士有限公司 | 具有不對稱晶片堆疊結構的半導體封裝 |
US20180211936A1 (en) * | 2017-01-25 | 2018-07-26 | Powertech Technology Inc. | Thin fan-out multi-chip stacked package structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2020100998A1 (ja) | 2020-05-22 |
WO2020100308A1 (ja) | 2020-05-22 |
CN113039641A (zh) | 2021-06-25 |
JPWO2020100998A1 (ja) | 2021-09-30 |
KR102703891B1 (ko) | 2024-09-05 |
SG11202104932XA (en) | 2021-06-29 |
TW202038425A (zh) | 2020-10-16 |
KR20210094555A (ko) | 2021-07-29 |
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