TWI801570B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI801570B
TWI801570B TW108114850A TW108114850A TWI801570B TW I801570 B TWI801570 B TW I801570B TW 108114850 A TW108114850 A TW 108114850A TW 108114850 A TW108114850 A TW 108114850A TW I801570 B TWI801570 B TW I801570B
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pad
gate
chip
semiconductor
semiconductor device
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TW108114850A
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TW201946276A (zh
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藤田直樹
中村弘幸
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日商瑞薩電子股份有限公司
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    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
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Abstract

本發明提供一種半導體裝置及其製造方法，改善半導體裝置的可靠度。本發明之半導體裝置SA1中，於半導體晶片CHP之表面，形成與緩衝電容器的電容電極電性連接之緩衝電容墊SNP。

Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造技術，例如，關於應用在具備緩衝電容器之半導體裝置及其製造技術的有效技術。
於日本特開第2017－63124號公報（專利文獻1）及日本特開第2017－143188號公報（專利文獻2），記載關於在半導體晶片的內部形成有緩衝電容器之半導體裝置。 [習知技術文獻] [專利文獻]
專利文獻1：日本特開第2017－63124號公報 專利文獻2：日本特開第2017－143188號公報
[本發明所欲解決的問題]
在包含功率電晶體之半導體裝置中，為了使來自功率電晶體的輸出電壓所包含之突波電壓衰減，防止元件破壞、或抑制基於突波電壓之妨礙電磁波的產生，而有使用與功率電晶體並聯連接之緩衝電容器的情形。尤其是，本案發明人之檢討結果，得知在形成有功率電晶體之半導體晶片的內部設置緩衝電容器之情況，存在有在半導體晶片的外部設置緩衝電容器之構成中尚未浮現之新的改善餘地。因此，具備在形成有功率電晶體之半導體晶片的內部設置緩衝電容器之構成的半導體裝置中，期望對新浮現之改善餘地加以思考。
其他課題與新特徵，應可自本說明書之記述內容及附圖明瞭。 [解決問題之技術手段]
一實施形態之半導體裝置中，在半導體晶片之表面，形成與緩衝電容器的電容電極電性連接之緩衝電容墊。 [本發明之效果]
依一實施形態，可改善半導體裝置的可靠度。
以下實施形態中，雖為了方便在必要時分割為複數個部分或實施形態予以說明，但除了特別指出的情況以外，其等並非彼此全無關聯，而係具有一方為另一方之部分或全部的變形例、細節、補充說明等關係。
此外，以下實施形態中，在提及要素的數目等（包含個數、數值、量、範圍等）之情況，除了特別指出之情況及原理上明顯限定為特定數目之情況等以外，並未限定於該特定數目，可為特定數目以上，亦可為以下。
進一步，以下實施形態中，其構成要素（亦包含要素步驟等），除了特別指出之情況及原理上明顯被視為必須之情況等以外，自然可說是並非為必要。
同樣地，以下實施形態中，在提及構成要素等之形狀、位置關係等時，除了特別指出之情況及原理上明顯被視為並非如此之情況等以外，包含實質上與該形狀等近似或類似者等。此一條件，對於上述數值及範圍亦相同。
此外，在用於說明實施形態之全部附圖中，原則上對同一構件給予同一符號，並省略其重複的說明。另，有即便為俯視圖仍為了容易理解附圖而給予影線之情況。
＜用於減少突波電壓的緩衝電容器＞ 在實際的功率電晶體中，由於寄生電感之影響，而在導通（Turn on）時或關斷（Turn off）時產生突波電壓。若此等突波電壓超過功率電晶體的耐受電壓，則功率電晶體受到破壞。進一步，若產生突波電壓，則產生源自於突波電壓的電磁雜訊，有受到以往周邊機器之源自於電磁雜訊的誤動作為代表之不良影響的疑慮。因而，必須抑制在導通時或關斷時產生的突波電壓。
圖1為，顯示抑制突波電壓之電路構成例的電路圖。圖1中，係功率電晶體之一種的功率MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor, 金屬氧化物半導體場效應電晶體）100，構成為藉由控制施加在閘極電極G的閘極電壓，而控制流通在汲極D與源極S之間的汲極電流。亦即，若對閘極電極G施加閾值電壓以上的閘極電壓，則在汲極D與源極S之間形成成為電流路徑的反轉層，汲極電流在汲極D與源極S之間流通。另一方面，若對閘極電極G施加較閾值電壓更小的閘極電壓，則形成在汲極D與源極S之間的反轉層消失，汲極電流成為未在汲極D與源極S之間流通。
以與如此地構成的功率MOSFET100並聯連接之方式，設置緩衝電容器SC。藉此，圖1所示之電路，可抑制在功率MOSFET100之導通時或關斷時產生的突波電壓。以下，針對其理由予以說明。另，圖1所示之電路中，與功率MOSFET100反向並聯連接的內接二極體BD，係源自於功率MOSFET100之裝置構造而寄生形成的二極體。
例如，圖1中，若功率MOSFET100關斷，則產生基於寄生電感之反電動勢（突波電壓）。此反電動勢，與寄生電感之大小成正比，且亦與電流變化率成正比。亦即，功率MOSFET100關斷時，流通的電流成為不流通，因而電流變化率變大。因此，在關斷時，產生巨大的反電動勢。
此時，如圖1所示，功率MOSFET100與緩衝電容器SC並聯連接之情況，藉由使儲存在緩衝電容器SC的電荷放電，而緩和功率MOSFET100關斷時之急遽的電流變化。此一結果，在圖1所示之電路，相較於未設置緩衝電容器SC之單體的功率MOSFET100之情況，電流變化率變小，故與電流變化率呈正比的反電動勢（突波電壓）之大小變小。此一現象，係指藉由將緩衝電容器SC與功率MOSFET100並聯連接，而可抑制巨大突波電壓之產生。如同上述，藉由將功率MOSFET100與緩衝電容器SC並聯連接，而可抑制巨大突波電壓之產生。此一結果，可抑制源自於突波電壓的電磁雜訊之產生，故可抑制往周邊機器之源自於電磁雜訊的誤動作之產生。進一步，亦可抑制源自於巨大突波電壓的功率MOSFET100之破壞。
＜將緩衝電容器設置於半導體晶片的內部之實用性＞ 例如，上述緩衝電容器，一般設置在形成有功率MOSFET之半導體晶片的外部。然而，在形成有功率MOSFET之半導體晶片的外部設置緩衝電容器之情況，連接功率MOSFET與緩衝電容器之配線的長度變長，因而寄生電感增加。此外，反電動勢（突波電壓）之大小，與寄生電感之大小成正比，因而若寄生電感越大，則基於寄生電感的反電動勢（突波電壓）越大。因此，在形成有功率MOSFET之半導體晶片的外部設置緩衝電容器之構成（外接）中，藉由緩衝電容器，可緩和電流變化率，另一方面，由於難以降低寄生電感之大小，故難以有效地抑制巨大的反電動勢（突波電壓）之產生。
關於此點，檢討在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之情況。在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成中，相較於將緩衝電容器外接之構成，可縮短連接功率MOSFET與緩衝電容器之配線的長度。此一特徵，係指可降低寄生電感。因此，在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成，藉由可由緩衝電容器緩和切換時的電流變化率之效果、及可由長度短的連接功率MOSFET與緩衝電容器之配線降低寄生電感之效果兩者的相乘效果，可有效地抑制巨大的反電動勢（突波電壓）之產生。亦即，得知從有效地抑制巨大的反電動勢（突波電壓）之產生的觀點來看，在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成係有用的方法。進一步，在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成，相較於將緩衝電容器外接之構成，亦能夠追求用於安裝半導體裝置之安裝基板中的零件安裝面積之減少、零件件數之減少。
＜篩選測試的必要性＞ 此處，若採用在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成，則從確保緩衝電容器的可靠度之觀點來看，在包含功率MOSFET之半導體裝置的製程中，緩衝電容器的可靠度測試（篩選測試）成為必要。此係因，在形成有功率MOSFET之半導體晶片的內部包含緩衝電容器之半導體裝置中，若緩衝電容器不良，則即便功率MOSFET為良品，作為包含功率MOSFET與緩衝電容器之半導體裝置仍必須判斷為不良品的緣故。亦即，在包含功率MOSFET與緩衝電容器之半導體裝置中，不僅必須實施對於功率MOSFET的可靠度測試，必須亦實施對於緩衝電容器的可靠度測試。
＜浮現之改善餘地＞ 如此地，從有效地抑制巨大的反電動勢（突波電壓）之產生的觀點來看，若採用在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成，則為了確保緩衝電容器的可靠度，於包含功率MOSFET與緩衝電容器之半導體裝置的製程中，必須實施確保緩衝電容器的可靠度之篩選測試。關於此點，本案發明人新發現，實施與功率MOSFET混載的緩衝電容器之篩選測試時，必須加以思考。亦即，本案發明人發現，若採用在形成有功率MOSFET之半導體晶片的內部設置緩衝電容器之構成，則浮現新的改善餘地。因而，以下，首先，針對新浮現之改善餘地予以說明。
圖2為，顯示包含功率MOSFET與緩衝電容器之半導體裝置的裝置構造之示意構成例的剖面圖。圖2中，於半導體基板（n型基板）SUB上，形成磊晶層（n型半導體層）EPI，於此磊晶層EPI，形成通道區（p型半導體區）CH與p型柱PCR，形成所謂超級接面（Super Junction）構造。
而後，以貫通通道區CH而到達磊晶層EPI的方式形成溝槽，於此溝槽之內壁，例如，形成由氧化矽膜構成的閘極絕緣膜GOX。進一步，以隔著閘極絕緣膜GOX而嵌入溝槽的內部之方式，例如，形成由多晶矽膜構成的閘極電極GE。另一方面，於通道區CH之表面，形成源極區（n型半導體區），進一步，於通道區CH的內部，形成雜質濃度較通道區CH更高的主體接觸區（p型半導體區）BC。如此地，形成功率MOSFET。亦即，功率MOSFET，具備閘極電極GE、作為汲極區作用的磊晶層EPI與半導體基板SUB、及源極區SR。此時，在具有上述構成的功率MOSFET中，藉由n型半導體層即磊晶層EPI、及p型半導體區即通道區CH，而寄生形成pn接合二極體。將此寄生形成之pn接合二極體，稱作內接二極體。
而後，圖2中，以覆蓋功率MOSFET之方式，例如，形成由氧化矽膜構成的層間絕緣層IL1，於此層間絕緣層IL1，形成貫通層間絕緣層IL1的插栓PLG1。插栓PLG1，與源極區SR及主體接觸區BC雙方電性連接。
接著，如圖2所示，於形成有插栓PLG1之層間絕緣層IL1上，例如，形成由氧化矽膜構成的層間絕緣層IL2。此時，於此層間絕緣層IL2，形成貫通層間絕緣層IL2並與插栓PLG1連接的插栓PLG2，且形成緩衝電容器的電容電極CE2。其後，於層間絕緣層IL2上，例如，形成由氧化矽膜構成的層間絕緣層IL3。於此層間絕緣層IL3，形成貫通層間絕緣層IL3並與插栓PLG2連接的插栓PLG3。進一步，於形成有插栓PLG3之層間絕緣層IL3上，形成源極墊（源極電極）SP。因此，源極區SR與源極墊SP，成為經由插栓PLG1、插栓PLG2、插栓PLG3而電性連接。
此處，如圖2所示，緩衝電容器，主要由下述元件構成：形成在層間絕緣層IL2的電容電極CE2、電容電極CE2與相對向的插栓PLG2之間的電容、以及電容電極CE2與源極墊SP之間的電容。此外，圖2雖未圖示，但電容電極CE2，與功率MOSFET的成為汲極區之半導體基板SUB（磊晶層EPI）電性連接。因此，緩衝電容器，在功率MOSFET的源極區SR與汲極區之間並聯連接。
尤其是，圖2所示之裝置構造中，有效活用形成在閘極電極GE的上方之空間，形成緩衝電容器的電容電極CE2。由此，可在形成有功率MOSFET之半導體晶片混載緩衝電容器，而不招致半導體晶片的尺寸之增大。
此處，例如，使用電漿CVD（Chemical Vapor Deposition, 化學氣相沉積）法，形成分別構成層間絕緣層IL1～層間絕緣層IL3之氧化矽膜。此時，以電漿CVD法形成之氧化矽膜，含有汙染物質（雜質）。因此，例如，構成層間絕緣層IL2之氧化矽膜的一部分，成為緩衝電容器之電容絕緣膜，故緩衝電容器之電容絕緣膜，係由以電漿CVD法形成之氧化矽膜構成。此外，對緩衝電容器之電容絕緣膜，要求即便施加突波電壓仍不受到絕緣破壞的耐絕緣性。然而，在以電漿CVD法形成之氧化矽膜中，有部分混入汙染物質的可能性，源自於此汙染物質，有電容絕緣膜的耐絕緣性降低之疑慮。亦即，如圖2所示之裝置構造般地，混載功率MOSFET與緩衝電容器之情況，必須檢測構成緩衝電容器之電容絕緣膜的耐絕緣性是否良好。此係因，若構成緩衝電容器之電容絕緣膜發生絕緣不良，則緩衝電容器成為不良，故必須藉由施行篩選測試以將此等製品排除之緣故。因而，如同上述，在包含功率MOSFET與緩衝電容器之半導體裝置中，不僅必須實施對於功率MOSFET的可靠度測試，必須亦實施對於緩衝電容器的可靠度測試。
關於此點，本案發明人新發現，在混載功率MOSFET與緩衝電容器之半導體裝置中，若於實施緩衝電容器的篩選測試時並未加以思考，則無法實施篩選測試。
＜＜功率MOSFET之情況＞＞ 首先，針對在混載功率MOSFET與緩衝電容器之半導體裝置中，若於實施緩衝電容器的篩選測試時並未加以思考，則無法實施篩選測試之情形予以說明。
圖3為，說明在混載功率MOSFET100與緩衝電容器SC之半導體裝置中，若未加以思考，則無法實施篩選測試的圖。圖3中，在功率MOSFET100的汲極D與源極S之間並聯連接緩衝電容器SC。此時，在檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性是否良好之篩選測試中，對緩衝電容器SC的電容電極間施加脈衝電壓。其後，在對緩衝電容器SC的電容電極間施加脈衝電壓之狀態中，測定流通在包夾於電容電極間的電容絕緣膜之脈衝電流，藉以檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性是否良好。
具體而言，圖4為，顯示對緩衝電容器SC的電容電極間施加之脈衝電壓的圖。例如，如同圖4的虛線所示，為了檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性，而對緩衝電容器SC的電容電極間施加電壓Vc。例如，於篩選測試中，必須對緩衝電容器SC的電容電極間，施加功率MOSFET100的源極・汲極間耐受電壓之4倍程度的電壓V1。然而，緩衝電容器SC，在功率MOSFET100的源極S與汲極D之間並聯連接。由此，為了對緩衝電容器SC的電容電極間施加電壓V1，而對功率MOSFET100的源極S與汲極D之間施加電壓V1。此處，如圖3所示，於功率MOSFET100，在裝置構造上，寄生形成內接二極體BD。此一結果，若為了對緩衝電容器SC的電容電極間施加電壓V1，而對功率MOSFET100的源極S與汲極D之間施加電壓V1，則對寄生形成之內接二極體BD，亦施加電壓V1。尤其是，如圖3所示，內接二極體BD，與功率MOSFET反向並聯連接，因而若對功率MOSFET100的源極S與汲極D之間施加電壓V1，則在內接二極體BD中，電壓V1，作為逆向電壓而施加。此時，內接二極體BD之逆向崩潰電壓，遠較電壓V1更小，故若對內接二極體BD施加電壓V1，則其崩潰（breakdown）。亦即，即便對功率MOSFET100的源極S與汲極D之間施加電壓V1，仍受到內接二極體BD所箝位，其結果如同圖4的實線所示，對功率MOSFET100的源極S與汲極D之間，僅施加受到內接二極體BD箝位的電壓V2。此一情形，儘管必須對緩衝電容器SC的電容電極間施加電壓V1，但由於內接二極體BD的存在，對緩衝電容器SC的電容電極間，僅施加受到內接二極體BD箝位的電壓V2。此一情形，係指變得無法檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性。亦即，在混載功率MOSFET100與緩衝電容器SC之半導體裝置中，由於寄生形成之內接二極體BD的存在，若未進行任何設想，則無法實施檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性之篩選測試。
＜＜IGBT之情況＞＞ 接著，針對在混載係功率電晶體之一種的IGBT（Insulated Gate Bipolar Transistor, 絕緣閘雙極電晶體）與緩衝電容器之半導體裝置中，若於實施緩衝電容器的篩選測試時未加以思考，則亦無法實施篩選測試之情形予以說明。圖5為，說明在混載IGBT200與緩衝電容器SC之半導體裝置中，若未加以思考，則亦無法實施篩選測試的圖。圖5中，在IGBT200的集極C與射極E之間，並聯連接緩衝電容器SC。此時，在檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性是否良好之篩選測試中，對緩衝電容器SC的電容電極間施加脈衝電壓。其後，在對緩衝電容器SC的電容電極間施加脈衝電壓之狀態中，測定流通在包夾於電容電極間的電容絕緣膜之脈衝電流，藉以檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性是否良好。
具體而言，圖6為，顯示對緩衝電容器SC的電容電極間施加之脈衝電壓的圖。例如，如圖6所示，為了檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性，而對緩衝電容器SC的電容電極間施加電壓Vc。例如，於篩選測試中，必須對緩衝電容器SC的電容電極間，施加IGBT耐受電壓之4倍程度的電壓V3。然而，緩衝電容器SC，在IGBT200的射極E與集極C之間並聯連接。由此，為了對緩衝電容器SC的電容電極間施加電壓V3，而對IGBT200的射極E與集極C之間施加電壓V3。此時，於IGBT200中，與功率MOSFET100不同，並未寄生形成內接二極體BD，但若實施構成緩衝電容器SC之電容絕緣膜的篩選測試，則對IGBT200的射極E與集極C之間施加超過耐受電壓的電壓V3。此一情形，係指IGBT200受到破壞。如此地，在混載IGBT200與緩衝電容器SC之半導體裝置中，若未進行任何設想，則無法實施檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性之篩選測試。
＜實施形態之基本思想＞ 因而，本實施形態中，在具備與以功率MOSFET或IGBT為代表之功率電晶體並聯連接的緩衝電容器之半導體裝置中，思考用於實施檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之篩選測試。以下，針對進行此一思考所獲得的實施形態之基本思想予以說明。
圖7為，示意實施篩選測試的篩選步驟中之半導體裝置的電路構成之電路圖。如圖7所示，功率MOSFET100，具備閘極電極G、源極S、及汲極，功率MOSFET的汲極，與汲極墊電性連接。在如此地構成之功率MOSFET100中，於源極S與汲極之間寄生形成內接二極體BD。此外，緩衝電容器SC之一方的電容電極，與功率MOSFET100的源極S電性連接，另一方面，緩衝電容器SC之另一方的電容電極，與緩衝電容墊SNP電性連接。此時，於實施篩選測試的篩選步驟中，如圖7所示，汲極墊DP與緩衝電容墊SNP，並未電性連接。亦即，於篩選步驟中，功率MOSFET100與緩衝電容器SC並未並聯連接。在此一狀態下，對緩衝電容墊SNP與功率MOSFET的源極S之間施加脈衝電壓。此處，本實施形態中，汲極墊DP與緩衝電容墊SNP並未電性連接，因而並未對功率MOSFET100本體，施加超過功率MOSFET100本體之耐受電壓的脈衝電壓。因此，即便實施篩選測試，功率MOSFET100仍不受破壞。進一步，對內接二極體BD亦未施加脈衝電壓，因而可防止由於內接二極體BD之箝位，而未對緩衝電容器SC施加預期的脈衝電壓之情形。如此地，本實施形態之基本思想在於下述點：藉由設置未與功率MOSFET100的汲極電性連接之緩衝電容墊SNP，而構成為在實施篩選測試時，對緩衝電容器SC施加規定的脈衝電壓，另一方面，對功率MOSFET100的源極S與汲極之間並未施加脈衝電壓。藉此，依本實施形態，可確實地實施檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性之篩選測試，而防止功率MOSFET100的破壞，且不受內接二極體BD的存在所干擾。
然則，在最終的半導體裝置中，必須將功率MOSFET100與緩衝電容器SC並聯連接，因而必須於實施篩選測試後，將功率MOSFET100的汲極墊DP，與緩衝電容器SC的緩衝電容墊SNP電性連接。
圖8為，例如，示意篩選測試實施後的組裝步驟中之半導體裝置的電路構成之電路圖。如圖8所示，例如，藉由外部連接構件ECM，將功率MOSFET100的汲極墊DP，與緩衝電容器SC的緩衝電容墊SNP電性連接。藉此，本實施形態之半導體裝置，於實施篩選測試後，可將功率MOSFET100與緩衝電容器SC並聯連接。
本實施形態之基本思想，係考慮在將功率MOSFET100與緩衝電容器SC並聯連接之狀態下，難以檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性後，進行思考所獲得。具體而言，本實施形態之基本思想，係在檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET100的汲極墊DP與緩衝電容器SC的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接之思想。藉此，依本實施形態，可確實地檢測構成緩衝電容器SC之電容絕緣膜的耐絕緣性，且可將功率MOSFET100與緩衝電容器SC並聯連接。此一結果，能夠追求由於篩選測試之可實施所帶來的包含功率MOSFET100與緩衝電容器SC之半導體裝置的良率改善，並於半導體裝置中，抑制巨大的反電動勢（突波電壓）之產生，且相較於將緩衝電容器外接之構成，能夠追求用於安裝半導體裝置之安裝基板的零件安裝面積之減少、零件件數之減少。
＜半導體裝置的構成＞ 接著，針對本實施形態之半導體裝置的構成予以說明。圖9為，顯示本實施形態之半導體裝置SA1的外觀構成之圖。圖9中，本實施形態之半導體裝置SA1，具有俯視形狀呈略矩形形狀之密封體MR；閘極導線GL、導線L、源極導線SL，從此密封體MR突出。
而後，圖10為，顯示本實施形態之半導體裝置SA1的內部構造之圖。圖10中，本實施形態之半導體裝置SA1，具備：晶片搭載部TAB，具有邊S1；半導體晶片CHP，隔著銲料SD，搭載於晶片搭載部TAB上；以及複數導線，與晶片搭載部TAB的邊S1分離而對向配置。此時，複數導線，包含閘極導線GL、源極導線SL、及與晶片搭載部TAB一體地形成之導線L。
於半導體晶片CHP，形成係功率電晶體之一種的功率MOSFET、以及與此功率MOSFET並聯連接的緩衝電容器。此外，功率MOSFET，具備：閘極電極，與閘極導線GL電性連接；源極區，與源極導線SL電性連接；以及汲極區，與晶片搭載部TAB電性連接。另一方面，緩衝電容器，具備：與源極區電性連接之第1電容電極、與第1電容電極分離而對向配置之第2電容電極、以及第1電容電極與第2電容電極所包夾之電容絕緣膜。
如圖10所示，半導體晶片CHP，俯視形狀呈略矩形形狀。具體而言，半導體晶片CHP，具備：晶片邊CS1，與晶片搭載部TAB的邊S1對向配置；晶片邊CS2，位於晶片邊CS1之相反側；晶片邊CS3，與晶片邊CS1及晶片邊CS2交叉；以及晶片邊CS4，與晶片邊CS1及晶片邊CS2交叉，且位於晶片邊CS3之相反側。
此外，於半導體晶片CHP之表面，形成與功率MOSFET的源極區電性連接之複數源極墊SP；複數源極墊SP，藉由源極引線SW，而與源極導線SL電性連接。此外，於半導體晶片CHP之表面，形成與功率MOSFET的閘極電極電性連接之閘極墊GP。此閘極墊GP，藉由閘極引線GW，而與閘極導線GL電性連接。進一步，於半導體晶片CHP之表面，形成與緩衝電容器的第2電容電極電性連接之緩衝電容墊SNP。此外，於半導體晶片CHP之表面，亦形成與功率MOSFET的汲極區電性連接之汲極墊DP。此時，如圖10所示，緩衝電容墊SNP與汲極墊DP，藉由引線W而電性連接。
此處，如圖10所示，閘極引線GW的直徑，成為較源極引線SW的直徑更小。同樣地，引線W的直徑，亦成為較源極引線SW的直徑更小。另一方面，引線W的直徑與閘極引線GW的直徑，成為彼此相等。
接著，圖11為，顯示在本實施形態之半導體晶片CHP中，將緩衝電容器的構成要素即第2電容電極與緩衝電容墊連接之示意佈置構成的圖。圖11中，於形成在半導體晶片CHP之表面的源極墊SP之下層，配置複數電容電極（第2電容電極）CE2。此外，複數電容電極CE2，藉由插栓PLG而與上層之配線WL1及配線WL2連接。此一結果，複數電容電極CE2，藉由配線WL1及配線WL2，而與形成在半導體晶片CHP之表面的緩衝電容墊SNP電性連接。
而後，圖12為，本實施形態之半導體晶片CHP的剖面圖。圖12中，圖示功率MOSFET形成區域A1之剖面構造、汲極墊形成區域A2之剖面構造、及形成有與緩衝電容墊連接之配線WL1的配線形成區域A3之剖面構造。
首先，針對功率MOSFET形成區域A1之剖面構造予以說明。圖12的功率MOSFET形成區域A1中，於半導體基板（n型基板）SUB上，形成磊晶層（n型半導體層）EPI，於此磊晶層EPI，形成通道區（p型半導體區）CH與p型柱PCR，形成所謂的超級接面構造。此時，半導體基板SUB及磊晶層EPI，作為功率MOSFET的汲極區而作用。
例如，具備超級接面構造的功率MOSFET，於關斷狀態中，空乏層仍從形成在p型柱PCR與磊晶層EPI的邊界區域之pn接合往橫方向延伸。因此，具備超級接面構造的功率MOSFET中，即便將電流通路即磊晶層EPI之雜質濃度增高，往2個邊界區域所包夾之磊晶層EPI的內側方向延伸之空乏層仍連結，磊晶層EPI全體變得容易空乏化。
藉此，在關斷狀態下，磊晶層EPI全體空乏化，故可確保耐受電壓。亦即，具備超級接面構造的功率MOSFET中，即便將電流通路即磊晶層EPI之雜質濃度增高，仍可使磊晶層EPI全體空乏化。此一結果，具備超級接面構造的功率MOSFET，可確保高耐受電壓，並降低導通電阻。
而後，以貫通通道區CH而到達磊晶層EPI的方式形成溝槽，於此溝槽之內壁，例如，形成由氧化矽膜構成的閘極絕緣膜GOX。進一步，以隔著閘極絕緣膜GOX而嵌入溝槽的內部之方式，例如，形成由多晶矽膜構成的閘極電極GE。另一方面，於通道區CH之表面，形成源極區（n型半導體區），進一步，於通道區CH的內部，形成雜質濃度較通道區CH更高的主體接觸區（p型半導體區）BC。如此地，形成功率MOSFET。亦即，功率MOSFET，具備閘極電極GE、作為汲極區作用的磊晶層EPI與半導體基板SUB、及源極區SR。此時，在具有上述構成的功率MOSFET中，藉由n型半導體層即磊晶層EPI、及p型半導體區即通道區CH，而寄生形成pn接合二極體。將此寄生形成之pn接合二極體，稱作內接二極體。
而後，於圖12的功率MOSFET形成區域A1中，以覆蓋功率MOSFET之方式，例如，形成由氧化矽膜構成的層間絕緣層IL1，於此層間絕緣層IL1，形成貫通層間絕緣層IL1的插栓PLG1。插栓PLG1，與源極區SR及主體接觸區BC雙方電性連接。
因此，在圖12的功率MOSFET形成區域A1所示之功率MOSFET中，將源極區SR與主體接觸區BC電性連接。換而言之，源極區SR，經由主體接觸區BC，而與通道區CH電性連接。此處，主體接觸區BC，具有確保與插栓PLG1之歐姆接觸的功能，藉由此主體接觸區BC之存在，而使源極區SR與通道區CH，成為以相同電位電性連接。
因此，可抑制使源極區SR作為射極區，使通道區CH作為基極區，並使磊晶層EPI作為集極區之寄生npn雙極性電晶體的導通運作。亦即，源極區SR與通道區CH以相同電位電性連接，係指在寄生npn雙極性電晶體的射極區與基極區之間並未產生電位差，藉此，可抑制寄生npn雙極性電晶體的導通運作。
接著，如圖12的功率MOSFET形成區域A1所示，於形成有插栓PLG1之層間絕緣層IL1上，例如，形成由氧化矽膜構成的層間絕緣層IL2。此時，於此層間絕緣層IL2，貫通形成層間絕緣層IL2並與插栓PLG1連接的插栓PLG2，且形成緩衝電容器的電容電極（第2電容電極）CE2。其後，於層間絕緣層IL2上，例如，形成由氧化矽膜構成的層間絕緣層IL3。於此層間絕緣層IL3，形成貫通層間絕緣層IL3並與插栓PLG2連接的插栓PLG3。進一步，於形成有插栓PLG3之層間絕緣層IL3上，形成源極墊（源極電極）SP。因此，源極區SR與源極墊SP，成為經由插栓PLG1、插栓PLG2、插栓PLG3而電性連接。
此處，如圖12所示，緩衝電容器，主要由下述元件構成：形成在層間絕緣層IL2的電容電極CE2、電容電極CE2與相對向的插栓PLG2之間的電容、以及電容電極CE2與源極墊SP之間的電容。亦即，緩衝電容器，由下述元件構成：成為第2電容電極的電容電極CE2、作為第1電容電極而作用的「插栓PLG2＋源極墊SP」、及第1電容電極與第2電容電極所包夾之由「層間絕緣層IL2的一部分＋層間絕緣層IL3的一部分」構成的電容絕緣膜。
尤其是，圖12的功率MOSFET形成區域A1所示之裝置構造中，有效活用形成在閘極電極GE的上方之空間，形成緩衝電容器的電容電極CE2。由此，可在形成有功率MOSFET之半導體晶片混載緩衝電容器，而不招致半導體晶片的尺寸之增大。
接著，針對汲極墊形成區域A2之剖面構造予以說明。圖12的汲極墊形成區域A2中，於半導體基板（n型基板）SUB上，形成磊晶層（n型半導體層）EPI。其後，於磊晶層EPI上，例如，形成由氧化矽膜構成的層間絕緣層IL1。於此層間絕緣層IL1，形成貫通層間絕緣層IL1的插栓PLG1。此時，於與插栓PLG1接觸的磊晶層EPI之表面，形成雜質濃度較磊晶層EPI更高的高濃度n型半導體區。此高濃度n型半導體區，具有在插栓PLG1與磊晶層EPI之間確保歐姆接觸的功能。
接著，如圖12的汲極墊形成區域A2所示，於形成有插栓PLG1之層間絕緣層IL1上，例如，形成由氧化矽膜構成的層間絕緣層IL2。此時，於此層間絕緣層IL2，形成貫通層間絕緣層IL2，並與插栓PLG1連接的插栓PLG2。其後，於層間絕緣層IL2上，例如，形成由氧化矽膜構成的層間絕緣層IL3。於此層間絕緣層IL3，形成貫通層間絕緣層IL3，並與插栓PLG2連接的插栓PLG3。進一步，於形成有插栓PLG3之層間絕緣層IL3上，形成汲極墊DP。因此，磊晶層EPI與汲極墊DP，成為經由插栓PLG1、插栓PLG2、插栓PLG3而電性連接。此處，半導體基板SUB及磊晶層EPI，成為功率MOSFET的汲極區，因而形成在半導體晶片之表面的汲極墊DP，成為與功率MOSFET的汲極區電性連接。
接著，針對形成與緩衝電容墊連接之配線WL1的配線形成區域A3之剖面構造予以說明。圖12的配線形成區域A3中，於半導體基板（n型基板）SUB上，形成磊晶層（n型半導體層）EPI。其後，於磊晶層EPI上，例如，形成由氧化矽膜構成的層間絕緣層IL1。其後，如圖12的配線形成區域A3所示，於層間絕緣層IL1上，例如，形成由氧化矽膜構成的層間絕緣層IL2。此時，於此層間絕緣層IL2，形成貫通層間絕緣層IL2的電容電極CE2。其後，於層間絕緣層IL2上，例如，形成由氧化矽膜構成的層間絕緣層IL3。於此層間絕緣層IL3，形成貫通層間絕緣層IL3，並與電容電極CE2連接的插栓PLG。進一步，於形成有插栓PLG之層間絕緣層IL3上，形成配線WL1。此時，例如，如圖11所示，配線WL1，與緩衝電容墊SNP電性連接。因此，圖12的配線形成區域A3所示之電容電極CE2，經由插栓PLG及配線WL1，而成為與緩衝電容墊SNP電性連接。其後，如圖10所示，在本實施形態之半導體裝置SA1，將緩衝電容墊SNP與汲極墊DP以引線W連接。其後，如圖12的汲極墊形成區域A2所示，汲極墊DP，與功率MOSFET的汲極區（「磊晶層EPI＋半導體基板SUB」）電性連接，因而電容電極CE2，成為與功率MOSFET的汲極區電性連接。另一方面，如圖12的功率MOSFET形成區域A1所示，將與電容電極（第2電容電極）CE2相對向之作為第1電容電極作用的「插栓PLG2＋源極墊SP」，與功率MOSFET的源極區SR電性連接。因此，由電容電極（第2電容電極）CE2與第1電容電極（「插栓PLG2＋源極墊SP」）構成的緩衝電容器，成為在功率MOSFET的源極區SR與汲極區之間並聯連接。
＜半導體裝置之製造方法＞ 本實施形態之半導體裝置SA1，如同上述地構成，以下，針對其製造方法，參考附圖並予以說明。
首先，圖13為，半導體晶圓WF的示意圖，亦顯示半導體晶圓WF之區域RA的放大圖。如圖13之區域RA的放大圖所示，於半導體晶圓WF，形成複數晶片區域CR。
於各複數晶片區域CR，分別形成功率電晶體、及與功率電晶體電性連接之緩衝電容器。此處，功率電晶體具備源極區（第1區域）、汲極區（第2區域）、及控制流通在源極區與汲極區之間的電流之閘極電極。此外，緩衝電容器，具備：第1電容電極，與源極區電性連接；以及第2電容電極，與第1電容電極分離而對向配置。此時，於各複數晶片區域之表面，分別形成：緩衝電容墊，與緩衝電容器的第2電容電極電性連接；源極墊，與源極區電性連接；汲極墊，與汲極區電性連接；以及閘極墊，與閘極電極電性連接。
準備好如此地構成之半導體晶圓後，對分別形成在複數晶片區域CR的緩衝電容器，檢測第1電容電極與第2電容電極所包夾之電容絕緣膜的耐絕緣性（篩選測試）。
圖14為，顯示篩選測試之流程的流程圖。圖14中，首先，使探針接觸源極墊，並使探針接觸緩衝電容墊（S101）。接著，對源極墊與緩衝電容墊之間施加電壓（S102）。而後，測定在源極墊與緩衝電容墊之間流通的電流（S103）。其後，依據測定出的電流，判定緩衝電容器之良否（S104）。圖15為，顯示篩選測試之具體例的流程圖。圖15中，首先，使探針接觸緩衝電容墊後，確認探針是否接觸緩衝電容墊。具體而言，緩衝電容器為電容器，因而在直流上為開路，故藉由「克耳文檢查（Kelvin check）」，檢查探針是否接觸緩衝電容墊（S201）。接著，對功率MOSFET的源極與緩衝電容墊之間施加脈衝電壓（S202）。而後，測定在功率MOSFET的源極與緩衝電容墊之間流通的電流，測定出的電流為規定值（例如1μA）以上之情況，判斷為緩衝電容器的耐絕緣性不良（S203）。另一方面，測定出的電流未滿規定值之情況，判斷為緩衝電容器的耐絕緣性良好（S203）。其後，實施特性保證項目的檢測，即主動特性檢測（S204）。如同上述，實施緩衝電容器的篩選測試。
接著，切割半導體晶圓WF，藉以將複數晶片區域CR單片化，取得半導體晶片。此時，將通過篩選測試的形成有緩衝電容器之半導體晶片，作為良品抽出。
而後，如圖16所示，準備導線架LF，其具備：晶片搭載部TAB，具有邊S1；以及複數導線，與晶片搭載部TAB的邊S1分離而對向配置。此處，複數導線，包含閘極導線GL、源極導線SL、及與晶片搭載部TAB一體地形成之導線L。此外，於閘極導線GL之柱狀部及源極導線SL之柱狀部，形成由鎳構成的鍍膜（參考圖16的網點區域）。
其後，如圖17所示，往晶片搭載部TAB上供給銲料SD。而後，如圖18所示，使往晶片搭載部TAB上供給的銲料SD擴展。
接著，如圖19所示，隔著銲料SD，將通過篩選測試的形成有緩衝電容器之半導體晶片CHP，搭載於晶片搭載部TAB上。此時，於半導體晶片CHP之表面，形成緩衝電容墊SNP、源極墊SP、汲極墊DP、及閘極墊GP。
而後，如圖20所示，將形成在半導體晶片CHP之表面的源極墊SP，與形成有由鎳構成的鍍膜之源極導線SL之柱狀部，以源極引線SW連接。其後，如圖21所示，將形成在半導體晶片CHP之表面的緩衝電容墊SNP，與形成在半導體晶片CHP之表面的汲極墊DP，以引線W連接。其後，如圖22所示，將形成在半導體晶片CHP之表面的閘極墊GP，與形成有由鎳構成的鍍膜之閘極導線GL之柱狀部，以閘極引線GW連接。
接著，如圖23所示，例如，藉由以樹脂構成的密封體MR，將搭載有半導體晶片（CHP）之晶片搭載部（TAB）、源極引線（SW）、閘極引線（GW）、及引線（W）密封。此時，閘極導線GL的一部分、源極導線SL的一部分、及導線L的一部分，從密封體露出。其後，在從密封體MR露出的導線（閘極導線GL、導線L、源極導線SL）之表面形成鍍膜後，使導線成形（導線成形步驟）。其後，在將半導體裝置單片化後（單片化步驟），實施標示步驟及特性分類步驟。如同上述，可製造本實施形態之半導體裝置。
＜實施形態之特徵＞ 而後，針對本實施形態之特徵點予以說明。本實施形態之第1特徵點，例如在於下述點：如圖10所示，於形成有功率MOSFET與緩衝電容器之半導體晶片CHP的表面，形成緩衝電容墊SNP與汲極墊DP，並將緩衝電容墊SNP與汲極墊DP以連接構件（引線W）連接。藉此，在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之篩選測試的階段中，並未將緩衝電容墊SNP與汲極墊DP以連接構件（引線W）連接，而可構成為功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP並未電性連接（參考圖13～圖15）。另一方面，在實施篩選測試後的階段中，藉由將緩衝電容墊SNP與汲極墊DP以連接構件（引線W）連接，而可將汲極墊DP與緩衝電容墊SNP電性連接（參考圖22）。
此一結果，依本實施形態，可確實地檢測構成緩衝電容器之電容絕緣膜的耐絕緣性，且在篩選測試之結束後的階段，可將功率MOSFET與緩衝電容器SC並聯連接。此一結果，能夠追求由於篩選測試之可實施所帶來的包含功率MOSFET與緩衝電容器之半導體裝置的良率改善，並於半導體裝置中，能夠抑制巨大的反電動勢（突波電壓）之產生，且相較於將緩衝電容器外接之構成，能夠追求用於安裝半導體裝置之安裝基板的零件安裝面積之減少、零件件數之減少。
接著，本實施形態之第2特徵點，例如在於下述點：如圖10所示，閘極墊GP，靠近半導體晶片CHP的晶片邊CS1與晶片邊CS3之交點而配置，另一方面，緩衝電容墊SNP，靠近半導體晶片CHP的晶片邊CS2與晶片邊CS4之交點而配置。藉此，於半導體晶片CHP的遠離中央部之角部附近，配置緩衝電容墊SNP，故可將緩衝電容墊SNP配置於半導體晶片CHP之表面，而不犧牲半導體晶片CHP的中央部之空間。亦即，依本實施形態之第2特徵點，可將緩衝電容墊SNP配置於半導體晶片CHP之表面，而不犧牲配置源極墊SP之半導體晶片CHP的中央部之空間。亦即，源極墊SP，作為功率MOSFET的源極而作用，流通巨大電流。因此，從追求功率MOSFET之性能改善的觀點來看，重要處在於將半導體晶片CHP之表面的複數源極墊SP之占有面積盡可能增大，降低導通電阻。關於此點，依本實施形態之第2特徵點，避開配置複數源極墊SP之半導體晶片CHP的中央部，於半導體晶片CHP的角部附近配置緩衝電容墊SNP。因此，依本實施形態之第2特徵點，可將緩衝電容墊SNP配置於半導體晶片CHP之表面，並盡可能加大半導體晶片CHP之表面的複數源極墊SP之占有面積。藉此，可追求功率MOSFET之導通電阻的降低，並實施使用緩衝電容墊SNP之緩衝電容器的篩選測試。因此，依本實施形態之第2特徵點，可追求功率MOSFET之導通電阻的降低所帶來的半導體裝置之性能改善，並追求可進行使用緩衝電容墊SNP之緩衝電容器的篩選測試所帶來之半導體裝置的良率改善。
進一步，依本實施形態之第2特徵點，閘極墊GP與緩衝電容墊SNP，配置於半導體晶片CHP的不同之角部。亦即，依本實施形態之第2特徵點，閘極墊GP與緩衝電容墊SNP成為分散配置。藉此，可有效活用無法配置複數源極墊SP之無效空間，而無須伴隨複數源極墊SP的配置變更，藉此，可使半導體晶片CHP之佈置的設計變更為最低限度。亦即，依本實施形態之第2特徵點，可抑制半導體晶片CHP之佈置的設計變更所伴隨之製造成本的上升，並追求可進行使用緩衝電容墊SNP之緩衝電容器的篩選測試所帶來之半導體裝置的良率改善。
而後，本實施形態之第3特徵點，例如在於下述點：如圖10所示，將汲極墊DP靠近緩衝電容墊SNP而配置。藉此，可縮短連接緩衝電容墊SNP與汲極墊DP之引線W的長度。此一情形，係指可降低引線W的寄生電感，藉此，可抑制在功率MOSFET之導通時或關斷時產生的突波電壓之大小。例如，緩衝電容墊SNP，在篩選測試的階段，必須與功率MOSFET的汲極電性分離，但在最終製品（半導體裝置）的階段，必須將功率MOSFET與緩衝電容器並聯連接，因而必須將緩衝電容墊SNP與功率MOSFET的汲極電性連接。關於此點，例如，如圖12所示，半導體基板SUB及磊晶層EPI，作為功率MOSFET的汲極區而作用。因此，為了將緩衝電容墊SNP與功率MOSFET的汲極電性連接，而將緩衝電容墊SNP與半導體基板SUB（磊晶層EPI）電性連接即可。然則，在物理方面，難以將形成在半導體晶片CHP之表面的緩衝電容墊SNP，與在半導體晶片CHP之背面露出的半導體基板SUB電性連接。此處，例如，如圖10所示，將半導體晶片CHP，隔著銲料SD搭載於晶片搭載部TAB上，因而晶片搭載部TAB，成為與半導體基板SUB電性連接。亦即，晶片搭載部TAB，亦與功率MOSFET的汲極成為相同電位。由此，例如，圖10中，為了將功率MOSFET與緩衝電容器並聯連接，而考慮將形成在半導體晶片CHP之表面的緩衝電容墊SNP，與並未搭載半導體晶片CHP的晶片搭載部TAB上之一部分，以引線連接。然則，此一情況，由於晶片搭載部TAB上並未形成鍍膜，故晶片搭載部TAB與引線的連接變得困難。亦即，例如，如圖16所示，在與引線連接的部分，形成鍍膜（參考圖16的網點區域）。因此，為了將緩衝電容墊SNP與晶片搭載部TAB以引線連接，必須於晶片搭載部TAB之表面亦形成鍍膜。然而，若於具有大面積的晶片搭載部之表面全體形成鍍膜，則半導體裝置之製造成本大幅上升。因而，在本實施形態中，例如，如圖12的汲極墊形成區域A2所示，於半導體晶片CHP之表面形成汲極墊DP，將此汲極墊DP，與成為功率MOSFET的汲極區之磊晶層EPI，藉由插栓PLG1～PLG3而電性連接。此一結果，藉由將形成在半導體晶片CHP之表面的汲極墊DP與緩衝電容墊SNP連接，而實現功率MOSFET與緩衝電容器之並聯連接。如此地，作為本實施形態之第3特徵點的前提，於半導體晶片CHP之表面設置汲極墊DP的技術意義，係簡單地將緩衝電容墊SNP與功率MOSFET的汲極電性連接，而不招致製造成本的大幅上升。此外，以此構成為前提，依將汲極墊DP靠近緩衝電容墊SNP而配置的本實施形態之第3特徵點，可縮短連接緩衝電容墊SNP與汲極墊DP之引線W的長度。此一結果，依本實施形態之第3特徵點。藉由將緩衝電容墊SNP與汲極墊DP以引線W連接，而可將功率MOSFET與緩衝電容器並聯連接，並將源自於引線W之寄生電感的增加抑制在最低限度。
接著，本實施形態之第4特徵點，例如在於下述點：如圖10所示，緩衝電容墊SNP的平面尺寸，較汲極墊DP的平面尺寸更大。藉此，可實施使用緩衝電容墊SNP的篩選測試，並改善連接緩衝電容墊SNP與汲極墊DP之引線的連接強度。以下，茲就此點予以說明。例如，於緩衝電容器的篩選測試中，使探針接觸緩衝電容墊SNP並實施測試。此一結果，於緩衝電容墊SNP，形成因探針接觸所產生的探針痕跡。而若於緩衝電容墊SNP之表面形成探針痕跡，則緩衝電容墊之表面的凹凸變大。在此等凹凸大的探針痕跡上連接引線W之情況，由於源自於探針痕跡的凹凸，而使緩衝電容墊SNP與引線W之連接可靠度降低。因而，在本實施形態中，增大緩衝電容墊SNP的平面尺寸，構成為分別設置使探針與緩衝電容墊SNP接觸的探針接觸部、及與引線W連接的引線連接部。藉此，於緩衝電容墊SNP之表面，確保探針接觸部與引線連接部之各自的區域，因而即便在與探針接觸之探針接觸部形成探針痕跡，於引線連接部，仍確保表面的平坦性而不形成探針痕跡。此一結果，依本實施形態之緩衝電容墊SNP，可確保使用緩衝電容墊SNP的篩選測試之實施，並改善緩衝電容墊SNP與引線的連接強度。另一方面，汲極墊DP，在緩衝電容器的篩選測試中並未使用，因而亦未進行探針之接觸。由此，於汲極墊DP中，確保與引線的連接區域即可，無須確保與探針接觸的區域。因此，本實施形態之汲極墊DP的平面尺寸，較本實施形態之緩衝電容墊SNP的平面尺寸更小。如此地，依本實施形態之第4特徵點，可考慮到使用緩衝電容墊SNP的篩選測試之實施，並使緩衝電容墊SNP與汲極墊DP合計之占有面積（平面尺寸）為最低限度。
而後，本實施形態之第5特徵點，例如在於下述點：如圖13～圖15所示，在半導體晶圓WF之狀態下，實施形成在各晶片區域CR之緩衝電容器的篩選測試。此一情況，作為一例，藉由使用探針卡，而可在半導體晶圓WF之狀態下，一併實施形成在各個晶片區域CR之緩衝電容器的篩選測試。另一方面，對切割半導體晶圓WF而單片化的各個半導體晶片CHP，實施篩選測試之情況，耗費大量時間。亦即，依本實施形態之第5特徵點，可追求篩選測試之效率化，結果可大幅縮短TAT（Turn Around Time, 處理時間）。
接著，本實施形態之第6特徵點，例如在於下述點：如圖20～圖22所示，將源極墊SP與源極導線SL（源極導線SL之柱狀部），以源極引線SW連接後，將緩衝電容墊SNP與汲極墊DP，以引線W連接。藉此，可抑制連接緩衝電容墊SNP與汲極墊DP之引線W的切斷。以下，茲就此點予以說明。例如，在連接源極墊SP與源極導線SL（源極導線SL之柱狀部）之源極引線SW，流通巨大電流，故源極引線SW的直徑變大。另一方面，在連接緩衝電容墊SNP與汲極墊DP之引線W，並未流通如同在源極引線SW流通的電流般之巨大電流。由此，引線W的直徑，成為較源極引線SW的直徑更小。
而後，施加超音波，並實施藉由源極引線SW將源極墊SP與源極導線SL（源極導線SL之柱狀部）連接之引線接合步驟。此時，源極引線SW的直徑大，因而超音波的強度亦變大。因此，若先在藉由引線W將緩衝電容墊SNP與汲極墊DP連接之狀態下，實施將源極墊SP與源極導線SL（源極導線SL之柱狀部）連接之引線接合步驟，則強度大的超音波之振動往引線W傳遞，而有徑小之引線W切斷的可能。由此，本實施形態中，在將源極墊SP與源極導線SL（源極導線SL之柱狀部）以源極引線SW連接後，將緩衝電容墊SNP與汲極墊DP以引線W連接。藉此，依本實施形態之第6特徵點，可有效地防止連接緩衝電容墊SNP與汲極墊DP之引線W的切斷。
而後，本實施形態之第7特徵點，例如在於下述點：如圖21～圖22所示，連接緩衝電容墊SNP及汲極墊DP之引線W的直徑，與連接閘極墊GP及閘極導線GL（閘極導線GL之柱狀部）之閘極引線GW的直徑相等。藉此，可將在藉由閘極引線W連接閘極墊GP與閘極導線GL（閘極導線GL之柱狀部）之引線接合步驟使用的引線接合裝置，亦使用在藉由引線W連接緩衝電容墊SNP與汲極墊DP之引線接合步驟。此一結果，依本實施形態之第7特徵點，可抑制半導體裝置之製程的複雜化，藉此，可抑制半導體裝置之製造成本的上升。
接著，本實施形態之第8特徵點，例如在於下述點：如圖12的功率MOSFET形成區域A1所示，有效活用存在於閘極電極GE的上方之空間，設置緩衝電容器。藉此，可在形成有功率MOSFET之半導體晶片CHP的內部混載緩衝電容器，而不招致半導體晶片CHP的尺寸之增大。
此處，在超級接面構造的功率MOSFET，相較於非超級接面構造的一般功率MOSFET，有在特定頻率下之雜訊（EMI雜訊、電磁波雜訊）的位準變大之傾向。發明人認為其理由係因裝置構造之相異，而使寄生電容有所不同，故在切換時（導通時或關斷時）在雜訊位準產生差之緣故。亦即，發明人認為，由於裝置構造之相異，相較於一般功率MOSFET，超級接面構造的功率MOSFET的寄生電容變小，寄生電容所產生之振鈴峰值電壓（源自於反電動勢之突波電壓）的緩和效果小。此一結果，相較於一般功率MOSFET，超級接面構造的功率MOSFET在半導體晶片的內部追加緩衝電容器之必要性變高。
然則，若在半導體晶片的內部追加緩衝電容器，則必然招致晶片尺寸之增大。關於此點，尤其是在超級接面構造的功率MOSFET中，例如，如圖12的功率MOSFET形成區域A1所示，有效活用存在於閘極電極GE的上方之空間而設置緩衝電容器的實用性增高。此係因，在超級接面構造的功率MOSFET中，相較於一般功率MOSFET，寄生電容所產生之振鈴峰值電壓（源自於反電動勢之突波電壓）的緩和效果小，故緩衝電容器的追加所產生之振鈴峰值電壓（源自於反電動勢之突波電壓）的緩和效果之必要性增高的緣故。因此，尤其是在超級接面構造的功率MOSFET中，於半導體晶片的內部設置緩衝電容器之必要性大，因而採用在半導體晶片的內部設置緩衝電容器而不招致晶片尺寸之增大的思考方式，即本實施形態之第8特徵點的實用性變高。然則，本實施形態之第8特徵點，不僅應用在混載超級接面構造的功率MOSFET與緩衝電容器之構成，亦可廣泛應用在混載一般功率MOSFET與緩衝電容器之構成。
＜變形例1＞ 圖24為，顯示實施形態的變形例1之半導體裝置SA1的示意構成之圖。圖24中，於本變形例1，將閘極墊GP、緩衝電容墊SNP、汲極墊DP，於半導體晶片CHP沿著晶片邊CS1而配置。如此地，亦可佈置配置緩衝電容墊SNP與汲極墊DP。此一情況中，亦可實現如下基本思想：在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接。
＜變形例2＞ 圖25為，顯示實施形態的變形例2之半導體裝置SA1的示意構成之圖。圖25中，於本變形例2，將閘極墊GP，靠近晶片邊CS1與晶片邊CS3之交點而配置。換而言之，閘極墊GP，配置於晶片邊CS1與晶片邊CS3之交叉的角部。此外，閘極墊GP與緩衝電容墊SNP，沿著晶片邊CS1而配置，且閘極墊GP與汲極墊DP，沿著晶片邊CS3而配置。此外，相反地，亦可將閘極墊GP與緩衝電容墊SNP，沿著晶片邊CS3而配置，且將閘極墊GP與汲極墊DP，沿著晶片邊CS1而配置。如此地，亦可佈置配置緩衝電容墊SNP與汲極墊DP。此一情況中，亦可實現如下基本思想：在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接。
＜變形例3＞ 圖26為，顯示實施形態的變形例3之半導體裝置SA1的示意構成之圖。圖26中，於本變形例3，閘極墊GP、緩衝電容墊SNP、汲極墊DP，沿著晶片邊CS3而配置。如此地，亦可佈置配置緩衝電容墊SNP與汲極墊DP。此一情況中，亦可實現如下基本思想：在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接。
＜變形例4＞ 圖27為，顯示實施形態的變形例4之半導體裝置SA1的示意構成之圖。圖27中，於本變形例4，將形成在半導體晶片CHP之表面的源極墊SP與源極導線SL（源極導線SL之柱狀部），例如，以由銅構成的扣件CLP1連接。同樣地，於本變形例4，緩衝電容墊SNP與汲極墊DP，係以扣件CLP2連接。
此一情況中，亦可實現如下基本思想：在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接。
＜變形例5＞ 圖28為，顯示實施形態的變形例5之半導體裝置SA1的示意構成之圖。圖28中，於本變形例5，將緩衝電容墊SNP與汲極墊DP，以導電性黏接材ADH連接。
此一情況中，亦可實現如下基本思想：在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接。
＜變形例6＞ 圖29為，顯示實施形態的變形例6之半導體裝置SA1的示意構成之圖。例如，如圖29所示，半導體晶片CHP，隔著銲料SD，搭載於晶片搭載部TAB上，因而晶片搭載部TAB，成為與半導體基板電性連接。亦即，晶片搭載部TAB亦與功率MOSFET的汲極成為相同電位。由此，例如，圖29中，於本變形例6，為了將功率MOSFET與緩衝電容器並聯連接，而將形成在半導體晶片CHP之表面的緩衝電容墊SNP，與並未搭載半導體晶片CHP的晶片搭載部TAB上之一部分，以引線W連接。此一情況，無須於半導體晶片CHP之表面設置汲極墊（DP）。
然則，於晶片搭載部TAB上，並未形成鍍膜，故晶片搭載部TAB與引線W的連接變得困難。亦即，例如，如圖16所示，在與引線連接的部分，形成鍍膜（參考圖16的網點區域）。因此，為了將緩衝電容墊SNP與晶片搭載部TAB以引線連接，而必須於晶片搭載部TAB之表面亦形成鍍膜。然而，若於具有大面積的晶片搭載部之表面全體形成鍍膜，則半導體裝置之製造成本大幅上升。因此，從引線W的連接可靠度及抑制製造成本之觀點來看，例如，較宜為如圖10所示之實施形態般地，將緩衝電容墊SNP與汲極墊DP以引線W連接的構成。
＜變形例7＞ 圖30為，顯示實施形態的變形例7之半導體裝置SA1的示意構成之圖。圖30中，於本變形例7，在半導體晶片CHP的中央部，設置緩衝電容墊SNP與汲極墊DP，將此緩衝電容墊SNP與汲極墊DP以引線W連接。
此一情況中，亦可實現如下基本思想：在檢測構成緩衝電容器之電容絕緣膜的耐絕緣性之階段中，並未將功率MOSFET的汲極墊DP與緩衝電容器的緩衝電容墊SNP電性連接，另一方面，在實施篩選測試後的階段中，將汲極墊DP與緩衝電容墊SNP電性連接。
然則，於本變形例7的構成，半導體晶片CHP所占的單元區域（形成構成功率MOSFET之單元的區域）之面積變小。由此，從增大半導體晶片CHP所占的單元區域，降低功率MOSFET之導通電阻的觀點來看，例如，較宜為如圖10所示之實施形態般地，將緩衝電容墊SNP與汲極墊DP配置於半導體晶片CHP的角部之構成。
＜變形例8＞ 於實施形態中，作為功率電晶體之一例，雖列舉功率MOSFET為例而予以說明，但實施形態之技術思想，並不限於此一形態，例如，作為功率電晶體，亦可應用在採用IGBT的情況。此時，作為包含功率MOSFET之半導體裝置SA1，與包含IGBT之半導體裝置的對應關係，如同以下。亦即，源極導線SL成為射極導線，且源極區成為射極區，且汲極區成為集極區，且汲極墊DP成為集極墊。
以上，依據上述實施形態具體地說明本案發明人所提出之發明，但本發明並未限定於上述實施形態，自然可在不脫離其要旨之範圍進行各種變更。
100‧‧‧功率MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor, 金屬氧化物半導體場效應電晶體） 200‧‧‧IGBT（Insulated Gate Bipolar Transistor, 絕緣閘雙極電晶體） A1‧‧‧功率MOSFET形成區域 A2‧‧‧汲極墊形成區域 A3‧‧‧配線形成區域 ADH‧‧‧導電性黏接材 BC‧‧‧主體接觸區（p型半導體區） BD‧‧‧內接二極體 C‧‧‧集極 CE2‧‧‧電容電極 CH‧‧‧通道區（p型半導體區） CHP‧‧‧半導體晶片 CLP1、CLP2‧‧‧扣件 CR‧‧‧晶片區域 CS1、CS2、CS3、CS4‧‧‧晶片邊 D‧‧‧汲極 DP‧‧‧汲極墊 E‧‧‧射極 ECM‧‧‧外部連接構件 EPI‧‧‧磊晶層（n型半導體層） G‧‧‧閘極電極 GE‧‧‧閘極電極 GL‧‧‧閘極導線 GOX‧‧‧閘極絕緣膜 GP‧‧‧閘極墊 GW‧‧‧閘極引線 IL1～IL3‧‧‧層間絕緣層 L‧‧‧導線 LF‧‧‧導線架 MR‧‧‧密封體 PCR‧‧‧p型柱 PLG、PLG1～PLG3‧‧‧插栓 RA‧‧‧區域 S‧‧‧源極 S1‧‧‧邊 SA1‧‧‧半導體裝置 SC‧‧‧緩衝電容器 SD‧‧‧銲料 SL‧‧‧源極導線 SNP‧‧‧緩衝電容墊 SP‧‧‧源極墊（源極電極） SR‧‧‧源極區 SUB‧‧‧半導體基板 SW‧‧‧源極引線 TAB‧‧‧晶片搭載部 W‧‧‧引線 WF‧‧‧半導體晶圓 WL1、WL2‧‧‧配線
圖1係顯示抑制突波電壓之電路構成例的電路圖。 圖2係顯示包含功率MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor, 金屬氧化物半導體場效應電晶體）與緩衝電容器之半導體裝置的裝置構造之示意構成例的剖面圖。 圖3係說明在混載功率MOSFET與緩衝電容器之半導體裝置中，若未加以思考，則無法實施篩選測試的圖。 圖4係顯示對緩衝電容器的電容電極間施加之脈衝電壓的圖。 圖5係說明在混載IGBT（Insulated Gate Bipolar Transistor, 絕緣閘雙極電晶體）與緩衝電容器之半導體裝置中，若未加以思考，則亦無法實施篩選測試的圖。 圖6係顯示對緩衝電容器的電容電極間施加之脈衝電壓的圖。 圖7係示意實施篩選測試的篩選步驟中之半導體裝置的電路構成之電路圖。 圖8係示意篩選測試實施後的組裝步驟中之半導體裝置的電路構成之電路圖。 圖9係顯示實施形態之半導體裝置的外觀構成之圖。 圖10係顯示實施形態之半導體裝置的內部構造之圖。 圖11係顯示在實施形態之半導體晶片中，將緩衝電容器的構成要素即第2電容電極與緩衝電容墊連接之示意佈置構成的圖。 圖12係實施形態之半導體晶片的剖面圖。 圖13係半導體晶圓的示意圖。 圖14係顯示篩選測試之流程的流程圖。 圖15係顯示篩選測試之具體例的流程圖。 圖16係顯示實施形態之半導體裝置的製程之剖面圖。 圖17係顯示接續圖16之半導體裝置的製程之剖面圖。 圖18係顯示接續圖17之半導體裝置的製程之剖面圖。 圖19係顯示接續圖18之半導體裝置的製程之剖面圖。 圖20係顯示接續圖19之半導體裝置的製程之剖面圖。 圖21係顯示接續圖20之半導體裝置的製程之剖面圖。 圖22係顯示接續圖21之半導體裝置的製程之剖面圖。 圖23係顯示接續圖22之半導體裝置的製程之剖面圖。 圖24係顯示變形例1之半導體裝置的示意構成之圖。 圖25係顯示變形例2之半導體裝置的示意構成之圖。 圖26係顯示變形例3之半導體裝置的示意構成之圖。 圖27係顯示變形例4之半導體裝置的示意構成之圖。 圖28係顯示變形例5之半導體裝置的示意構成之圖。 圖29係顯示變形例6之半導體裝置的示意構成之圖。 圖30係顯示變形例7之半導體裝置的示意構成之圖。
CHP‧‧‧半導體晶片
CS1、CS2、CS3、CS4‧‧‧晶片邊
DP‧‧‧汲極墊
GL‧‧‧閘極導線
GP‧‧‧閘極墊
GW‧‧‧閘極引線
L‧‧‧導線
S1‧‧‧邊
SA1‧‧‧半導體裝置
SD‧‧‧銲料
SL‧‧‧源極導線
SNP‧‧‧緩衝電容墊
SP‧‧‧源極墊(源極電極)
SW‧‧‧源極引線
TAB‧‧‧晶片搭載部
W‧‧‧引線

Claims (18)

  1. 一種半導體裝置，包含：晶片搭載部，具有第1邊；半導體晶片，搭載於該晶片搭載部上；以及複數導線，從該晶片搭載部分離，且沿著該晶片搭載部的該第1邊配置；該複數導線，包括：閘極導線、以及第1導線；該半導體晶片，包含：功率電晶體；以及緩衝電容器，與該功率電晶體並聯連接；該功率電晶體，包含：閘極電極，與該閘極導線電性連接；第1區域，與該第1導線電性連接；以及第2區域，與該晶片搭載部電性連接；該緩衝電容器，包含：第1電容電極，與該第1區域電性連接；以及第2電容電極，從該第1電容電極分離，且配置成與該第1電容電極對向；於該半導體晶片之表面，形成與該緩衝電容器的該第2電容電極電性連接之緩衝電容墊；於該半導體晶片之表面，形成未經由該晶片搭載部而與該功率電晶體的該第2區域電性連接之第2墊；該緩衝電容墊與該第2墊，係經由連接構件而相互地電性連接。
  2. 如申請專利範圍第1項之半導體裝置，其中，該連接構件係引線。
  3. 如申請專利範圍第1項之半導體裝置，其中， 該連接構件係扣件。
  4. 如申請專利範圍第1項之半導體裝置，其中，該連接構件係導電性黏接材。
  5. 如申請專利範圍第1項之半導體裝置，其中，該緩衝電容墊與該晶片搭載部係以引線連接。
  6. 如申請專利範圍第1項之半導體裝置，其中，該半導體晶片，具備：第1晶片邊，沿著該晶片搭載部的該第1邊配置；第2晶片邊，位於該第1晶片邊之相反側；第3晶片邊，與該第1晶片邊及該第2晶片邊交叉；以及第4晶片邊，與該第1晶片邊及該第2晶片邊交叉，且位於該第3晶片邊之相反側。
  7. 如申請專利範圍第6項之半導體裝置，其中，於該半導體晶片之表面，形成與該功率電晶體的該閘極電極電性連接之閘極墊；該閘極墊、該緩衝電容墊、該第2墊，係沿著該第1晶片邊而配置。
  8. 如申請專利範圍第6項之半導體裝置，其中，於該半導體晶片之表面，形成與該功率電晶體的該閘極電極電性連接之閘極墊；該閘極墊、該緩衝電容墊、及該第2墊，係沿著該第3晶片邊配置。
  9. 如申請專利範圍第6項之半導體裝置，其中，於該半導體晶片之表面，形成與該功率電晶體的該閘極電極電性連接之閘極墊；該閘極墊，係靠近該第1晶片邊與該第3晶片邊之交點而配置；該閘極墊與該緩衝電容墊，係沿著該第1晶片邊而配置；該閘極墊與該第2墊，係沿著該第3晶片邊而配置。
  10. 如申請專利範圍第6項之半導體裝置，其中，於該半導體晶片之表面，形成與該功率電晶體的該閘極電極電性連接之閘極墊；該閘極墊，係靠近該第1晶片邊與該第3晶片邊之交點而配置；該閘極墊與該緩衝電容墊，係沿著該第3晶片邊而配置；該閘極墊與該第2墊，係沿著該第1晶片邊而配置。
  11. s如申請專利範圍第6項之半導體裝置，其中，於該半導體晶片之表面，形成與該功率電晶體的該閘極電極電性連接之閘極墊；該閘極墊，係靠近該第1晶片邊與該第3晶片邊之交點而配置；該緩衝電容墊，係靠近該第2晶片邊與該第4晶片邊之交點而配置。
  12. 如申請專利範圍第2項之半導體裝置，其中，於該半導體晶片之表面，形成：第1墊，與該功率電晶體的該第1區域電性連接；以及閘極墊，與該功率電晶體的該閘極電極電性連接； 該第1墊與該第1導線係以第1引線連接；該閘極墊與該閘極導線係以閘極引線連接；該閘極引線的直徑，小於該第1引線的直徑；該引線的直徑，小於該第1引線的直徑。
  13. 如申請專利範圍第12項之半導體裝置，其中，該引線的直徑，與該閘極引線的直徑相等。
  14. 如申請專利範圍第1項之半導體裝置，其中，該功率電晶體係功率MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬氧化物半導體場效應電晶體)；該第1導線係源極導線；該第1區域係源極區；該第2區域係汲極區；該第2墊係汲極墊。
  15. 如申請專利範圍第1項之半導體裝置，其中，該功率電晶體係IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極電晶體)；該第1導線係射極導線；該第1區域係射極區；該第2區域係集極區；該第2墊係集極墊。
  16. 一種半導體裝置之製造方法，包含如下步驟：(a)準備半導體晶圓，其包含形成有功率電晶體、及與該功率電晶體電性連接之緩衝電容器的晶片區域；該功率電晶體，包括：第1區域；第2區域；以及閘極電極，控制流通在該第1區域與該第2區域之間的電流；該緩衝電容器，包括：第1電容電極，與該第1區域電性連接；以及第2電容電極，從該第1電容電極分離，且配置成與該第1電容電極對向；於該晶片區域之表面，形成：緩衝電容墊，與該緩衝電容器的該第2電容電極電性連接；第1墊，與該第1區域電性連接；第2墊，與該第2區域電性連接；以及閘極墊，與該閘極電極電性連接；(b)使探針接觸該緩衝電容墊；(c)對該第1區域與該緩衝電容墊之間施加電壓；(d)測定在該第1區域與該緩衝電容墊之間流通的電流；(e)依據在該(d)步驟測定出的該電流，判定該緩衝電容器之良否；(f)於該(e)步驟後，切割該半導體晶圓，藉以將該晶片區域單片化，而取得半導體晶片；(g)準備導線架，其包括：晶片搭載部，具有第1邊；以及複數之導線，從該晶片搭載部分離，且沿著該晶片搭載部的該第1邊配置；該複數導線，包含：閘極導線、及第1導線；(h)將該半導體晶片搭載於該晶片搭載部上； (i)將該第1墊與該第1導線以第1引線連接；以及(j)於該(i)步驟後，將該閘極墊與該閘極導線以閘極引線連接，並將該緩衝電容墊與該第2墊以引線連接。
  17. 如申請專利範圍第16項之半導體裝置之製造方法，其中，在該(j)步驟，使用相同的引線接合裝置。
  18. 如申請專利範圍第16項之半導體裝置之製造方法，其中，在該(a)步驟準備之該半導體晶圓的該晶片區域所形成之該緩衝電容器，係藉由電漿CVD法形成，且包含設置在該第1電容電極與該第2電容電極之間的電容絕緣膜。
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