TWI786986B - 內連線結構的製造方法 - Google Patents
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
一種內連線結構的製造方法,包括以下步驟。提供基底。在基底上形成多個犧牲層。在相鄰兩個犧牲層之間形成介電層。在介電層中具有氣隙。移除多個犧牲層,而形成多個第一開口。在第一開口中形成導電層。
Description
本發明是有關於一種半導體結構的製造方法,且特別是有關於一種內連線結構的製造方法。
隨著半導體元件的積集度不斷地提升,導電層之間的間隔也越來越小。如此一來,將會提高導電層之間的寄生電容,進而使得電阻電容延遲(resistance-capacitance(RC)delay)的問題更加嚴重。由於電阻電容延遲會降低訊號傳輸的速度,因此如何有效地降低電阻電容延遲為目前持續努力的目標。
本發明提供一種內連線結構的製造方法,其可有效地降低電阻電容延遲。
本發明提出一種內連線結構的製造方法,包括以下步驟。提供基底。在基底上形成多個犧牲層。在相鄰兩個犧牲層之間形成介電層。在介電層中具有氣隙(air gap)。移除多個犧牲層,而形
成多個第一開口。在第一開口中形成導電層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,犧牲層的形成方法可包括以下步驟。在基底上形成犧牲材料層。在犧牲材料層上形成硬罩幕材料層。對硬罩幕材料層與犧牲材料層進行圖案化,而形成多個硬罩幕層與多個犧牲層,且在相鄰兩個硬罩幕層之間以及相鄰兩個犧牲層之間形成第二開口。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,更可包括以下步驟。對犧牲層進行等向性蝕刻製程,以加寬位在相鄰兩個犧牲層之間的第二開口的寬度。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,位在相鄰兩個犧牲層之間的第二開口的寬度可大於位在相鄰兩個硬罩幕層之間的第二開口的寬度。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,介電層的形成方法可包括以下步驟。在第二開口中形成介電材料層。在介電材料層中可具有氣隙。氣隙可位在相鄰兩個犧牲層之間。利用犧牲層作為終止層,移除部分介電材料層與硬罩幕層,而形成介電層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,導電層的材料例如是銅。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,更可包括以下步驟。在形成犧牲層之前,在基底上形成
終止層。介電層可形成在終止層上。共形地在介電層與終止層上形成間隙壁材料層。對間隙壁材料層進行回蝕刻製程,而在介電層的側壁上形成間隙壁。回蝕刻製程可移除由間隙壁所暴露出的部分終止層,而暴露出部分基底。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,更可包括以下步驟。在第一開口中形成阻障層。阻障層位在導電層與介電層之間以及導電層與基底之間。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,導電層與阻障層的形成方法可包括以下步驟。共形地在第一開口中形成阻障材料層。在阻障材料層上形成填入第一開口的導電材料層。移除位在第一開口的外部的導電材料層與阻障材料層,而形成導電層與阻障層。
依照本發明的一實施例所述,在上述內連線結構的製造方法中,位在第一開口的外部的導電材料層與阻障材料層的移除方法例如是化學機械研磨法。
基於上述,在本發明所提出的內連線結構的製造方法中,由於介電層中具有氣隙,且氣隙具有較低的介電常數,因此可降低導電層之間的寄生電容,進而可有效地降低電阻電容延遲。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
100:基底
102:終止層
104:犧牲材料層
104a:犧牲層
106:硬罩幕材料層
106a:硬罩幕層
108:介電材料層
108a:介電層
110:間隙壁材料層
110a:間隙壁
112:阻障材料層
112a:阻障層
114:導電材料層
114a:導電層
116:內連線結構
AG:氣隙
OP1,OP2:開口
TS1,TS2:頂面
W1,W2:寬度
圖1A至圖1K為根據本發明一實施例的內連線結構的製造流程剖面圖。
圖1A至圖1K為根據本發明一實施例的內連線結構的製造流程剖面圖。
請參照圖1A,提供基底100。基底100可為半導體基底,如矽基底。此外,在圖1A中雖未示出,但在基底100中可具有摻雜區及/或隔離結構等所需的構件,且在基底100上可具有半導體元件(如,電晶體等主動元件)、介電層及/或內連線結構等所需的構件,於此省略其說明。
接著,可在基底100上形成終止層102。終止層102的材料例如是氧化矽。終止層102的形成方法例如是化學氣相沉積法。
然後,可在基底100上形成犧牲材料層104。在本實施例中,犧牲材料層104可形成在終止層102上。犧牲材料層104的材料例如是氮化矽。犧牲材料層104的形成方法例如是化學氣相沉積法。
接下來,可在犧牲材料層104上形成硬罩幕材料層106。硬罩幕材料層106的材料例如是氧化矽,如四乙氧基矽烷(tetraethyl orthosilicate,TEOS)氧化矽,但本發明並不以此為限。硬罩幕材料層106的形成方法例如是化學氣相沉積法。
請參照圖1B,可對硬罩幕材料層106與犧牲材料層104進行圖案化,而形成多個硬罩幕層106a與多個犧牲層104a,且在相鄰兩個硬罩幕層106a之間以及相鄰兩個犧牲層104a之間形成開口OP1。藉此,可在基底100上形成多個犧牲層104a。在本實施例中,犧牲層104a可形成在終止層102上。此外,硬罩幕層106a可形成在犧牲層104a上。舉例來說,可藉由微影製程與蝕刻製程(如,乾式蝕刻製程)對硬罩幕材料層106與犧牲材料層104進行圖案化。
請參照圖1C,可對犧牲層104a進行等向性蝕刻製程,以加寬位在相鄰兩個犧牲層104a之間的開口OP1的寬度。上述等向性蝕刻製程例如是濕式蝕刻製程或乾式蝕刻製程。在一些實施例中,位在相鄰兩個犧牲層104a之間的開口OP1的寬度W1可大於位在相鄰兩個硬罩幕層106a之間的開口OP1的寬度W2。
請參照圖1D,可在開口OP1中形成介電材料層108。在介電材料層108中可具有氣隙AG。氣隙AG可位在相鄰兩個犧牲層104a之間。介電材料層108的材料例如是氧化矽(如,TEOS氧化矽)或低介電常數(low dielectric constant(low-k))材料。介電材料層108的形成方法例如是化學氣相沉積法。
請參照圖1E,可利用犧牲層104a作為終止層,移除部分介電材料層108與硬罩幕層106a,而形成介電層108a。藉此,可在相鄰兩個犧牲層104a之間形成介電層108a。在一些實施例中,介電層108a可形成在終止層102上。在介電層108a中具有氣隙
AG。在一些實施例中,氣隙AG可位在介電層108a的內部,亦即氣隙AG可被介電層108a所圍繞。舉例來說,可利用犧牲層104a作為研磨終止層,對介電材料層108與硬罩幕層106a進行化學機械研磨製程,以移除部分介電材料層108與硬罩幕層106a,藉此形成介電層108a。
請參照圖1F,移除多個犧牲層104a,而形成多個開口OP2。犧牲層104a的移除方法例如是濕式蝕刻法。此外,在用以移除犧牲層104a的蝕刻製程中,終止層102可用以保護位在終止層102下方的構件(如,內連線結構或電極等)(未示出)。
請參照圖1G,可共形地在介電層108a與終止層102上形成間隙壁材料層110。間隙壁材料層110的材料可為與介電層108a具有高蝕刻選擇比的材料。舉例來說,介電層108a的材料可為TEOS氧化矽,且間隙壁材料層110的材料可為氮化矽。間隙壁材料層110的形成方法例如是化學氣相沉積法。
請參照圖1H,可對間隙壁材料層110進行回蝕刻製程,而在介電層108a的側壁上形成間隙壁110a。此外,上述回蝕刻製程可移除由間隙壁110a所暴露出的部分終止層102,而暴露出部分基底100。藉此,開口OP2可延伸至終止層102中且暴露出部分基底100。上述回蝕刻製程例如是乾式蝕刻製程。
請參照圖1I,可共形地在開口OP2中形成阻障材料層112。阻障材料層112的材料例如是鉭(Ta)、氮化鉭(TaN)或其組合,但本發明並不以此為限。阻障材料層112的形成方法例如是物理氣
相沉積法,但本發明並不以此為限。
請參照圖1J,可在阻障材料層112上形成填入開口OP2的導電材料層114。導電材料層114的材料例如是銅。導電材料層114的形成方法例如是電化學鍍覆法(electrochemical plating,ECP)、物理氣相沉積法、化學氣相沉積法或其組合,但本發明並不以此為限。
請參照圖1K,可移除位在開口OP2的外部的導電材料層114與阻障材料層112,而形成導電層114a與阻障層112a。藉此,可在開口OP2中形成導電層114a與阻障層112a。在一些實施例中,導電層114a的剖面形狀可為倒梯形。阻障層112a位在導電層114a與介電層108a之間以及導電層114a與基底100之間。在本實施例中,阻障層112a可位在導電層114a與間隙壁110a之間。此外,位在開口OP2的外部的導電材料層114與阻障材料層112的移除方法例如是化學機械研磨法。
藉由上述方法(如,鑲嵌法(damascene method)),可在開口OP2中形成內連線結構116。內連線結構116可為導線、接觸窗(contact)或通孔(via)。內連線結構116可包括導電層114a。導電層114a的材料例如是銅。在一些實施例中,內連線結構116更可包括阻障層112a。導電層114a可位在阻障層112a上。阻障層112a的材料例如是鉭(Ta)、氮化鉭(TaN)或其組合,但本發明並不以此為限。在一些實施例中,內連線結構116可電性連接至位在基底100上或基底100中的導電構件(如,內連線結構或電極等)(未示出)。
此外,當基底100具有空曠區(open area)(未示出)時,在形成導電層114a的製程中,會同時在空曠區中形成虛擬導電圖案(dummy conductive pattern)。在一些實施例中,空曠區可定義為面積為100平方微米(μm2)以上且不具有導電層114a的區域。
基於上述實施例可知,在內連線結構116的製造方法中,由於介電層108a中具有氣隙AG,且氣隙AG具有較低的介電常數,因此可降低導電層114a之間的寄生電容,進而可有效地降低電阻電容延遲。
綜上所述,在上述實施例的內連線結構的製造方法中,由於介電層中具有氣隙,因此可有效地降低電阻電容延遲。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:基底
102:終止層
108a:介電層
110a:間隙壁
112a:阻障層
114a:導電層
116:內連線結構
AG:氣隙
OP2:開口
Claims (9)
- 一種內連線結構的製造方法,包括:提供基底;在所述基底上形成多個犧牲層;在相鄰兩個所述犧牲層之間形成介電層,其中在所述介電層中具有氣隙;移除多個所述犧牲層,而形成多個第一開口;以及在所述第一開口中形成導電層,其中所述內連線結構的製造方法更包括:在形成所述犧牲層與所述介電層之前,在所述基底上形成終止層,其中所述介電層形成在所述終止層上;共形地在所述介電層與所述終止層上形成間隙壁材料層;以及對所述間隙壁材料層進行回蝕刻製程,而在所述介電層的側壁上形成間隙壁,其中所述回蝕刻製程移除由所述間隙壁所暴露出的部分所述終止層,而暴露出部分所述基底。
- 如請求項1所述的內連線結構的製造方法,其中所述犧牲層的形成方法包括:在所述基底上形成犧牲材料層;在所述犧牲材料層上形成硬罩幕材料層;以及 對所述硬罩幕材料層與所述犧牲材料層進行圖案化,而形成多個硬罩幕層與多個所述犧牲層,且在相鄰兩個所述硬罩幕層之間以及相鄰兩個所述犧牲層之間形成第二開口。
- 如請求項2所述的內連線結構的製造方法,更包括:對所述犧牲層進行等向性蝕刻製程,以加寬位在相鄰兩個所述犧牲層之間的所述第二開口的寬度。
- 如請求項3所述的內連線結構的製造方法,其中位在相鄰兩個所述犧牲層之間的所述第二開口的寬度大於位在相鄰兩個所述硬罩幕層之間的所述第二開口的寬度。
- 如請求項2所述的內連線結構的製造方法,其中所述介電層的形成方法包括:在所述第二開口中形成介電材料層,其中在所述介電材料層中具有所述氣隙,且所述氣隙位在相鄰兩個所述犧牲層之間;以及利用所述犧牲層作為終止層,移除部分所述介電材料層與所述硬罩幕層,而形成所述介電層。
- 如請求項1所述的內連線結構的製造方法,其中所述導電層的材料包括銅。
- 如請求項1所述的內連線結構的製造方法,更包括:在所述第一開口中形成阻障層,其中所述阻障層位在所述導電層與所述介電層之間以及所述導電層與所述基底之間。
- 如請求項7所述的內連線結構的製造方法,其中所述導電層與所述阻障層的形成方法包括:共形地在所述第一開口中形成阻障材料層;在所述阻障材料層上形成填入所述第一開口的導電材料層;以及移除位在所述第一開口的外部的所述導電材料層與所述阻障材料層,而形成所述導電層與所述阻障層。
- 如請求項8所述的內連線結構的製造方法,其中位在所述第一開口的外部的所述導電材料層與所述阻障材料層的移除方法包括化學機械研磨法。
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