TWI769473B - 包括內埋式半導體裝置之基板結構 - Google Patents

包括內埋式半導體裝置之基板結構 Download PDF

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TWI769473B
TWI769473B TW109122718A TW109122718A TWI769473B TW I769473 B TWI769473 B TW I769473B TW 109122718 A TW109122718 A TW 109122718A TW 109122718 A TW109122718 A TW 109122718A TW I769473 B TWI769473 B TW I769473B
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dielectric layer
conductive
core layer
patterned
layer
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TW109122718A
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TW202135271A (zh
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陳建汎
廖玉茹
楊楚杰
施昇宏
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日月光半導體製造股份有限公司
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Abstract

揭示一種基板結構。該基板結構包括一載體、該載體上之一介電層、該介電層中之一經圖案化有機核心層及一導電通孔。該經圖案化有機核心層界定在該介電層中朝向該載體延伸之一通道。該導電通孔通過該通道朝向該載體延伸，而未接觸該經圖案化有機核心層。

Description

包括內埋式半導體裝置之基板結構
本發明大體上係關於基板，且特定而言，係關於其中內埋有半導體裝置之基板。
內埋式基板技術將至少一個主動或被動電組件包括於基板之導電層內。導電層有助於內埋式電組件之電互連或信號傳輸。內埋式基板被認為減小了封裝大小、增大了功率密度且改良了裝置效能，且因此變得愈來愈流行。
本發明之實施例提供一種基板結構。該基板結構包括一載體、該載體上之一介電層、該介電層中之一經圖案化有機核心層及一導電通孔。該經圖案化有機核心層界定在該介電層中朝向該載體延伸之一通道。另外，該導電通孔通過該通道朝向該載體延伸，而未接觸該經圖案化有機核心層。
本發明之一些實施例提供一種基板結構。該基板結構包括：包括一第一表面及與該第一表面相對之一第二表面的一介電層、該介 電層中之一半導體裝置、在該介電層中並環繞該半導體裝置之一經圖案化有機核心層，及一導電通孔。該經圖案化有機核心層界定在該第一表面與該第二表面之間的一通道。就一脈衝能量而言，該介電層具有比該經圖案化有機核心層高的一移除速率。另外，該導電通孔在該介電層之該第一表面與該第二表面之間的該通道中延伸。
本發明之實施例提供一種製造一基板結構的方法。該方法包括提供一第一載體；將一經圖案化核心層附接在該第一載體上方，該經圖案化核心層包括玻璃纖維且具備界定朝向該第一載體延伸之一通道的一第一開口；在該經圖案化核心層上形成一介電層，該介電層填充該第一開口；及對該介電層進行圖案化，從而產生通過該通道朝向該第一載體延伸而未接觸該經圖案化核心層之一通孔。
10:第一載體
11:介電層
11a:第一表面
11b:第二表面
12:介電層
12a:表面
12b:表面
21:第一導電薄膜
21h:第一開口
21p:導電襯墊
21t:導電跡線
21v:第一導電通孔
21vs:晶種層
22:第二導電薄膜
22h:第四開口
22v:第四導電通孔
23:第一導電箔片
23h:第三開口
23v:第三導電通孔
24:第二導電箔片
30:介電層
31:第一介電層
32:第二介電層
32a:表面
40:半導體裝置
40h:第二開口/腔室
40p:導電襯墊
40w:壁
41h:第二開口
41v:第二導電通孔
50:未經圖案化核心層
50f:填料，殘餘玻璃光纖
50h:第一開口
50w:壁
58:單元
60:保護塗層
71:第一連接結構
72:第二連接結構
80:電接點
81:電子組件
82:囊封層
100:基板結構
101:載體單元
p21:經圖案化第一導電薄膜
p22:經圖案化第二導電薄膜
p23:經圖案化第一導電箔片
p24:經圖案化第二導電箔片
p50:經圖案化核心層
psg:通道
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本發明之一些實施例的態樣。應注意，各種結構可能未按比例繪製，且各種結構之尺寸可出於論述清晰起見任意增大或減小。
圖1為根據本發明之實施例的基板結構之橫截面圖。
圖2A為根據本發明之實施例的未經圖案化核心層之示意性俯視圖。
圖2B為沿著線KK'截取的圖2A中說明之未經圖案化核心層的橫截面圖。
圖2C為根據本發明之實施例的經圖案化核心層之示意性俯視圖。
圖2D為沿著線MM，截取的圖2C中說明之經圖案化核心層的橫截面圖。
圖2E為示出圖2D中說明之經圖案化核心層的壁之表面狀況的放大 圖。
圖3A至圖3M說明根據本發明之實施例的基板結構之製造方法的一或多個階段中之橫截面圖。
貫穿圖式及詳細描述使用共同附圖標記以指示相同或類似組件。自結合隨附圖式獲取之以下詳細描述將容易理解本發明之實施例。
以下揭示內容提供用於實施所提供標的物之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以解釋本發明之特定態樣。當然，此等組件及配置僅為實例且不意欲為限制性的。例如，在以下描述中，第一特徵在第二特徵上方或上之形成可包括第一特徵及第二特徵直接接觸地形成或安置之實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成或安置，使得第一特徵及第二特徵可不直接接觸之實施例。另外，本發明可在各種實例中重複附圖標記及/或字母。此重複係出於簡單及清晰之目的，且本身並不規定所論述之各種實施例及/或組態之間的關係。
圖1為根據本發明之實施例的基板結構100之橫截面圖。
參考圖1，基板結構100包括介電層30、介電層30中之經圖案化核心層p50，及內埋於介電層30中且由經圖案化核心層p50環繞之半導體裝置40。半導體裝置40可包括主動電組件或被動電組件或此兩者。基板結構100進一步包括用以提供半導體裝置40之電互連或信號傳輸的第一連接結構71及第二連接結構72。第一連接結構71進一步包括介電層11、介電層11之第一表面11a上的經圖案化第一導電薄膜p21，及介電層11之第二表面11b上的經圖案化第二導電薄膜p22。此外，第二連接結構 72進一步包括介電層12、介電層12之表面12b上的經圖案化第一導電箔片p23，及介電層12之表面12a上的經圖案化第二導電箔片p24。
經圖案化核心層p50界定標記為「psg」之通道，其允許第一導電通孔21v在經圖案化第一導電箔片p23與經圖案化第一導電薄膜p21之間延伸穿過該通道。界定於經圖案化核心層p50中之通道psg具有大於第一導電通孔21v之直徑的直徑。結果，第一導電通孔21v在通道psg中之延伸並未接觸經圖案化核心層p50。第一導電通孔21v可經由經圖案化第一導電箔片p23電連接至半導體裝置40之導電襯墊40p，或電連接至第一連接結構71中之第三導電通孔23v，或此兩者。在一些實施例中，第一導電通孔21v安置於經圖案化第一導電箔片p23上方。例如，第一導電通孔21v覆蓋經圖案化第一導電箔片p23之表面。
在經圖案化第二導電箔片p24處曝露之第三導電通孔23v可電連接至諸如焊球之電連接件，該等連接件可繼而電連接至外部半導體裝置。另外，第一導電通孔21v可經由經圖案化第一導電薄膜p21電連接至第二連接結構72中之第四導電通孔22v。在經圖案化第二導電薄膜p22處曝露之第四導電通孔22v可電連接至諸如焊球之電連接件，該等連接件可繼而電連接至印刷電路板(PCB)。除了例如曝露第三導電通孔23v及第四導電通孔22v處的箔片及薄膜之外的經圖案化第二導電箔片p24及經圖案化第二導電薄膜p22由諸如焊料遮罩之保護塗層60覆蓋。
在一些實施例中，晶種層21vs可安置於介電層30與第一導電通孔21v之間。在一些實施例中，晶種層21vs可安置於經圖案化第一導電箔片p23與第一導電通孔21v之間。在一些實施例中，晶種層21vs可連同第一導電通孔21v一起在通道psg中延伸。出於簡單及明晰之目的，在其 他圖式中省略晶種層。
圖2A為根據本發明之實施例的未經圖案化核心層50之示意性俯視圖。圖2B為沿著線KK'截取的圖2A中說明之未經圖案化核心層50的橫截面圖。
參考圖2A，未經圖案化核心層50具備填料50f。在一實施例中，填料50f包括玻璃纖維。用於未經圖案化核心層50之合適材料包括有機材料。在一實施例中，未經圖案化核心層50具有範圍介於大約50μm至大約150μm之厚度。
圖2C為根據本發明之實施例的經圖案化核心層p50之示意性俯視圖。
參考圖2C，經圖案化核心層p50包括複數個單元58，每一單元具備第一開口50h及第二開口或腔室40h。在本實施例中，如例示性單元58中所示，第二開口40h中之每一者大體上由複數個第一開口50h以預定圖案環繞。第二開口40h經大小設定以容納半導體裝置40，而第一開口50h設計成使導電通孔穿過以實現半導體裝置40之電互連。因此，與對應第二開口40h相關聯之第一開口50h之數目及其部署圖案可取決於所要應用。經圖案化核心層p50可藉由製備如圖2A中所說明之未經圖案化核心層50，且接著藉由諸如雷射鑽孔、機械鑽孔、衝壓或噴砂製程中之一者的合適製程形成第一開口50h及第二開口40h來形成。
圖2D為沿著線MM'截取的圖2C中說明之經圖案化核心層p50的橫截面圖。
參考圖2D，第一開口50h界定允許稍後形成之導電通孔延伸穿過其中，以便提供半導體裝置40之電連接的通道。通道具有大於導電 通孔之直徑的直徑。在藉由使用雷射鑽孔形成第一開口50h及第二開口40h時，在經圖案化核心層p50的分別界定第一開口50h及第二開口40h之壁50w及40w中可能出現殘餘材料。關注稍後將在其中形成導電通孔之第一開口50h。圖2E為示出圖2D中說明之經圖案化核心層p50的壁50w之表面狀況的放大圖。參考圖2E，殘餘玻璃纖維50f可能自壁50w曝露出來。由於在本發明中，第一開口50h係藉由鑽通相同的材料，亦即未經圖案化核心層之有機材料形成的，因此殘餘玻璃纖維(若存在)並不顯著。然而，在一些現有方法中，為形成導電通孔，在鑽孔製程中對不同材料進行鑽孔，且因此可能在核心層中產生大量殘餘玻璃纖維。如稍後將詳細論述，此殘餘玻璃纖維很可能使之後形成之導電通孔電斷開(electric disconnection)。相比之下，根據本發明之經圖案化核心層p50可解決現有方法之問題。
圖3A至圖3L說明根據本發明之實施例的基板結構之製造方法的一或多個階段中之橫截面圖。
參考圖3A，提供具有第一表面11a及與第一表面11a相對之第二表面11b的第一載體10。第一載體10包括第一表面11a上之第一導電薄膜21、第二表面11b上之第二導電薄膜22，及在第一導電薄膜21與第二導電薄膜22之間的介電層11。介電層11可包括進一步包括諸如玻璃纖維之填料的有機材料。第一導電薄膜21及第二導電薄膜22可各自包括銅(Cu)。在一實施例中，介電層11具有範圍介於大約三十五(35)微米(μm)至大約四百(400)μm之厚度。另外，第一導電薄膜21及第二導電薄膜22可各自具有範圍介於大約5μm至大約18μm之厚度。
在本實施例中，第一載體10包括敷銅層壓(CCL)基板，其 包括可藉由切割道(未示出)彼此分離之若干載體單元101。由於載體單元101中之每一者在製造方法中經受類似或相同的製程，因此為方便起見，僅在以下描述中說明及描述例示性載體單元101。
參考圖3B，例如以微影製程，接著以蝕刻製程圖案化第一導電薄膜21，從而產生經圖案化第一導電薄膜p21。亦參考圖1，經圖案化第一導電薄膜p21可包括導電襯墊21p或導電跡線21t或此兩者，以有助於電互連或信號傳輸。
接下來，參考圖3C，在第一載體10之第一表面11a上形成第一介電層31，從而覆蓋經圖案化第一導電薄膜p21。用於第一介電層31之合適材料可係選自具有所要黏著性之彼等材料，以有助於附接例如半導體裝置。在一些實施例中，第一介電層31包括樹脂。此外，第一介電層31可不含諸如玻璃纖維之填料。在一實施例中，第一介電層31之厚度大約為35μm。
隨後，參考圖3D，將半導體裝置40附接至第一介電層31上。半導體裝置40定向成「面朝上」，其中其導電襯墊40p背對第一介電層31。半導體裝置40可包括主動裝置或被動裝置。
參考圖3E，將經圖案化核心層p50附接於第一介電層31上。可以如參考圖2C所描述及說明之類似方式形成的經圖案化核心層p50包括進一步包括諸如玻璃纖維之填料的有機材料。另外，亦參考圖2C及圖2D，經圖案化核心層p50具備第一開口50h及第二開口或腔室40h。在附接經圖案化核心層p50之後，第一開口50h之位置可各自對應於經圖案化第一導電薄膜p21中之導電襯墊21p，而第二開口40h容納半導體裝置40。第一開口50h中之每一者界定朝向對應導電襯墊21p延伸穿過經圖案化核 心層p50之通道。在一實施例中，經圖案化核心層p50具有範圍介於大約50μm至大約150μm之厚度。另外，經圖案化核心層p50可比半導體裝置40低大約10μm。
在本實施例中，在附接經圖案化核心層p50之前對半導體裝置40進行附接。然而，在另一實施例中，可在附接經圖案化核心層p50之後對半導體裝置40進行附接。因此，半導體裝置40及經圖案化核心層p50之附接次序係可互換的。
現參考圖3F，在第一介電層31及經圖案化核心層p50上形成第二介電層32，從而覆蓋半導體裝置40並填充所界定通道。第二介電層32及第一介電層31一起構成如參考圖1所描述及說明之介電層30。用於第二介電層32之合適材料與用於第一介電層31之彼等材料類似或相同。特定而言，如第一介電層31，第二介電層32可包括不含玻璃纖維之樹脂。在一實施例中，第二介電層32具有範圍介於大約35μm至大約75μm之厚度。
參考圖3G，以例如層壓製程將第一導電箔片23形成於第二介電層32之表面32a上。用於第一導電箔片23之合適材料可包括Cu。在一實施例中，第一導電箔片23具有大約5μm之厚度。
隨後，參考圖3H，對第一導電箔片23進行圖案化，從而產生經圖案化第一導電箔片p23。經圖案化第一導電箔片p23曝露第二介電層32之第一部分(未編號)，該等部分安置於由第一開口50h界定之通道上方且位置對應於經圖案化第一導電薄膜p21中之導電襯墊21p。另外，經圖案化第一導電箔片p23曝露第二介電層32之第二部分(未編號)，該等部分之位置對應於半導體裝置40之導電襯墊40p。
接著，以例如可使用二氧化碳(CO2)雷射之雷射鑽孔製程將第一開口21h形成至經曝露第一部分中，從而曝露經圖案化第一導電薄膜p21中之導電襯墊21p。第一開口21h朝向導電襯墊21p延伸穿過第二介電層32、所界定通道及第一介電層31。第一開口21h中之每一者具有小於對應通道之直徑的直徑。另外，藉由使用例如噴砂製程將第二開口41h形成至經曝露第二部分中，從而曝露半導體裝置40之導電襯墊40p。
接下來，參考圖3I，以例如電鍍製程將第一導電層形成於經圖案化第一導電箔片p23上。第一導電層填充第一開口21h及第二開口41h，從而分別產生第一導電通孔21v及第二導電通孔41v。在本實施例中，第一導電通孔21v朝向經圖案化第一導電薄膜p21逐漸變窄。第一導電層亦安置於經圖案化第一導電箔片p23上。經圖案化第一導電箔片p23經受圖案化製程，以對此等導電通孔21v及41v中的一些進行電隔離並界定用於電互連之導電跡線。
在本實施例中，穿過第二介電層32及第一介電層31以第一脈衝能量施加雷射，該兩介電層可包括不含任何玻璃纖維之類似或相同介電材料。如此一來，雷射穿過具有類似或相同材料(亦即，介電材料)的層，且因此以大體上相同的速率移除第二介電層32及第一介電層31。此外，由於第一開口21h具有小於對應的通道之直徑的直徑，因此藉由用導電材料填充第一開口21h而形成之第一導電通孔21v當然具有小於對應的通道之直徑的直徑。因此，第一導電通孔21v並不實體地(physically)接觸經圖案化核心層p50。特定而言，亦參考圖2D及圖2E，即使玻璃纖維50f的一部分(然而可能並不顯著)在形成經圖案化核心層p50期間可能自經圖案化核心層p50之壁50w凸入所界定之通道中，此等玻璃纖維50f在之後仍會 被第二介電層32覆蓋並與隨後形成之第一導電通孔21v間隔開。
在一些現有方法中，不同於根據本發明之經圖案化核心層p50，填充有玻璃纖維之核心層並不具備此等第一開口50h，且因此未界定通道。如此一來，在以雷射鑽孔製程形成第一開口21h期間，雷射穿過不同的材料(亦即，不含玻璃纖維之介電層及填充有玻璃纖維之核心層)，並以不同速率移除介電層及核心層。具體而言，在施加相同脈衝能量之情況下，不含玻璃纖維之介電層具有比具備玻璃纖維之核心層高的移除速率。因此，自核心層之壁曝露大量殘餘玻璃纖維。此等玻璃纖維不利地影響稍後形成之導電通孔的可靠性及品質。具體而言，經曝露玻璃纖維在導電通孔中產生環狀不連續區，且結果會導致導電通孔之電斷開。因此，現有方法可不符合如IPC-A-600H標準中指定之要求。
藉由比較，在本發明中，核心層預先經圖案化有開口，該開口用以界定允許稍後形成之導電通孔延伸穿過其中的通道。通道具有比待形成之導電通孔大的直徑，從而使得殘餘玻璃纖維(若存在)與導電通孔間隔開且並不妨礙導電通孔之形成。如此一來，在經圖案化核心層p50之情況下，導電通孔中之電斷開問題明顯得到緩解或解決。
參考圖3J，例如以層壓製程將具備第二導電箔片24之介電層12形成於經圖案化第一導電箔片p23、第一導電通孔21v及第二導電通孔41v上。用於介電層12及第二導電箔片24之合適材料與分別用於介電層11及第一導電箔片23之彼等材料類似或相同。特定而言，介電層12亦包括諸如玻璃纖維之填料。在一實施例中，介電層12具有大約35μm之厚度，且第二導電箔片24具有大約5μm之厚度。
參考圖3K，對第二導電箔片24進行圖案化，從而產生經圖 案化第二導電箔片p24。經圖案化第二導電箔片p24曝露介電層12的在半導體裝置40上方的部分。隨後，藉由使用例如雷射鑽孔將第三開口23h自介電層12之經曝露部分形成至該介電層中，從而曝露第二導電通孔41v之部分及經圖案化第一導電箔片p23之部分。
另外，對第二導電薄膜22進行圖案化，從而產生經圖案化第二導電薄膜p22，其曝露介電層11之部分。接著，藉由使用例如雷射鑽孔將第四開口22h自介電層11之經曝露部分形成至該介電層中，從而曝露經圖案化第一導電薄膜p21中之導電襯墊21p或導電跡線21t的部分。
在一些實施例中，圖3H中說明之第一開口21h以及圖3K中說明之第三開口23h及第四開口22h係藉由使用雷射鑽孔而形成。在形成延伸穿過不含玻璃纖維之介電層的第一開口21h時，以第一脈衝能量施加雷射，如先前論述。藉由比較，在形成延伸穿過填充有玻璃纖維之介電層的第三開口23h或第四開口22h時，以第二脈衝能量施加雷射。第二脈衝能量高於第一脈衝能量。
隨後，參考圖3L，以例如電鍍製程將第二導電層形成於經圖案化第二導電箔片p24上。第二導電層填充第三開口23h，從而產生第三導電通孔23v。第二導電層亦安置於經圖案化第二導電箔片p24上。經圖案化第二導電箔片p24接著經受圖案化製程，以對第三導電通孔23v中的一些進行電隔離並界定用於電連接之導電跡線。同樣，以例如電鍍製程將第三導電層形成於經圖案化第二導電薄膜p22上。第三導電層填充第四開口22h，從而產生第四導電通孔22v。在本實施例中，第四導電通孔22v朝向經圖案化第一導電薄膜p21逐漸變窄。第三導電層亦安置於經圖案化第二導電薄膜p22上。經圖案化第二導電薄膜p22接著經受圖案化製程， 以對第四導電通孔22v中的一些進行電隔離並界定用於電連接之導電跡線。
接下來，返回參考圖1，諸如焊料遮罩之保護塗層60經施加於經圖案化第二導電箔片p24及經圖案化第二導電薄膜p22上，從而曝露第三導電通孔23v及第四導電通孔24v。保護層60有助於控制待在焊接期間形成於經曝露第三導電通孔23v及第四導電通孔24v上的焊球(未示出)之移動。
參考圖3M，將電子組件81安置於介電層12上，並使其通過一或多個電接點80、經圖案化第二導電箔片p24、第三導電通孔23v、第二導電通孔41v及導電襯墊40p與半導體裝置40電連接。將囊封層82形成於介電層12上以覆蓋或囊封電子組件81。在一些實施例中，可藉由諸如轉移模製或壓縮模製之模製技術來形成囊封層82。在一些實施例中，可將一或多個電接點80提供於介電層11上，並電連接至經圖案化第二導電薄膜p22及第四導電通孔22v。
除非另外指定，否則諸如「上方」、「下方」、「向上」、「左邊」、「右邊」、「向下」、「頂部」、「底部」、「豎直」、「水平」、「側」、「較高」、「下部」、「上部」、「上方」、「下面」等空間描述係相對於圖式中所示之定向加以指示。應理解，本文中所使用之空間描述僅出於說明之目的，且本文中所描述之結構的實際實施可以任何定向或方式在空間上配置，其限制條件為本發明之實施例的優點不因此配置而有偏差。
如本文中所使用，術語「大約」、「大體上」、「大體」及「約」用以描述及考慮小的變化。當與事件或情形結合使用時，術語可指事件或情形明確發生之情況以及事件或情形極近似於發生之情況。例如， 當結合數值使用時，該等術語可指小於或等於彼數值之±10%的變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%之變化範圍。例如，若兩個數值之間的差小於或等於該等值之平均值的±10%，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%，則可認為該兩個數值「大體上」相同。
若兩個表面之間的移位不大於5μm、不大於2μm、不大於1μm或不大於0.5μm，則可認為兩個表面共面或大體上共面。
除非上下文另外明確規定，否則如本文中所使用，單數術語「一」及「該」可包括複數個指示物。
如本文中所使用，術語「導電(conductive)」、「導電(electrically conductive)」及「導電率」係指運輸電流之能力。導電材料通常指示展現對於電流流動之極小或零阻力之彼等材料。導電率之一個量度為西門子/公尺(S/m)。通常，導電材料為具有大於大約104S/m(諸如至少105S/m或至少106S/m)之導電率的一種材料。材料之導電率有時可隨溫度變化。除非另外指定，否則材料之導電率係在室溫下量測。
另外，本文中有時以範圍格式呈現量、比率及其他數值。應理解，此類範圍格式係為方便及簡潔起見而使用，且應靈活地理解為不僅包括明確指定為範圍限制之數值，且亦包括涵蓋於彼範圍內之所有個別數值或子範圍，如同明確指定每一數值及子範圍一般。
雖然本發明已參考其特定實施例進行描述及說明，但此等 描述及說明並不為限制性的。熟習此項技術者應理解，在不脫離如由所附申請專利範圍限定的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效物。圖示可不必按比例繪製。歸因於製造製程及公差，在本發明中之藝術再現與實際設備之間可能存在區別。可存在並未具體說明的本發明之其他實施例。說明書及圖式應被視為說明性，而非限制性。可作出修改，以使特定情況、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此類修改意欲在此隨附之申請專利範圍之範疇內。雖然已參考按特定次序執行的特定操作描述本文中所解釋的方法，但應理解，在不脫離本發明的教示的情況下，可組合、再細分，或重新定序此等操作以形成等效方法。因此，除非本文中具體指示，否則操作之次序及分組並非本發明之限制。
11:介電層
11a:第一表面
11b:第二表面
12:介電層
12a:表面
12b:表面
21p:導電襯墊
21t:導電跡線
21v:第一導電通孔
22v:第四導電通孔
23v:第三導電通孔
30:介電層
31:第一介電層
40:半導體裝置
40p:導電襯墊
41v:第二導電通孔
60:保護塗層
71:第一連接結構
72:第二連接結構
100:基板結構
p21:經圖案化第一導電薄膜
p22:經圖案化第二導電薄膜
p23:經圖案化第一導電箔片
p24:經圖案化第二導電箔片
p50:經圖案化核心層
psg:通道

Claims (14)

  1. 一種基板結構，其包含：一載體；一介電層，其在該載體上；一經圖案化有機核心層，其在該介電層中，該經圖案化有機核心層界定在該介電層中朝向該載體延伸之一通道；及一導電通孔，其通過該通道朝向該載體延伸，而未接觸該經圖案化有機核心層；其中該介電層包括安置於該載體上的一第一介電層及安置於該第一介電層上的一第二介電層；其中該經圖案化有機核心層內埋於該第一介電層及該第二介電層中；其中該經圖案化有機核心層包括玻璃纖維；及其中該通道由該經圖案化有機核心層之一壁界定，且該等玻璃纖維之部分自該壁曝露出來，被密封在該介電層中且與該導電通孔間隔開。
  2. 如請求項1之基板結構，其中該經圖案化有機核心層界定用於容納一半導體裝置之一腔室。
  3. 如請求項2之基板結構，其中該半導體裝置之一主動面背對該載板。
  4. 如請求項2之基板結構，其中該腔室與該通道間隔開。
  5. 如請求項1之基板結構，其中該通道具有一第一直徑，且該導電通孔具有小於該第一直徑之一第二直徑。
  6. 如請求項1之基板結構，其中就一脈衝能量而言，該介電層具有比該經圖案化有機核心層高之一移除速率。
  7. 如請求項1之基板結構，其中該介電層包括不含玻璃纖維之樹脂。
  8. 如請求項1之基板結構，其進一步包含安置於該介電層與該導電通孔之間的一晶種層。
  9. 如請求項1之基板結構，其進一步包含安置於該介電層上並與該導電通孔電連接的一導電箔片。
  10. 一種基板結構，其包含：一介電層，其包括一第一表面及與該第一表面相對之一第二表面；一半導體裝置，其在該介電層中；一經圖案化有機核心層，其在該介電層中並環繞該半導體裝置，該經圖案化有機核心層界定在該第一表面與該第二表面之間的一通道，就一脈衝能量而言，該介電層具有比該經圖案化有機核心層高之一移除速率；及一導電通孔，其在該介電層之該第一表面與該第二表面之間的該通 道中延伸；其中該經圖案化有機核心層包括玻璃纖維；及其中該通道由該經圖案化有機核心層之一壁界定，且該等玻璃纖維之部分自該壁曝露出來，被密封在該介電層中且與該導電通孔間隔開。
  11. 如請求項10之基板結構，其中該經圖案化有機核心層界定用於容納該半導體裝置之一腔室。
  12. 如請求項10之基板結構，其中該通道具有一第一直徑，且該導電通孔具有小於該第一直徑之一第二直徑。
  13. 如請求項10之基板結構，其中該介電層包括不含玻璃纖維之樹脂。
  14. 如請求項10之基板結構，其進一步包含界定於該經圖案化有機核心層中且安置於該半導體裝置周圍的額外通道。
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