TWI761037B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes an emitting unit, a first transistor, a driving circuit, a pulse-width determining circuit, a driving-amplitude determining circuit and a reset circuit. The first transistor is coupled to the emitting unit, configured to conduct in response of voltage of a first node. The driving circuit is configured to provide a driving current corresponding to voltage of a second node to the first transistor. The pulse-width determining circuit is configured to selectively provide a first driving signal to the first node to conduct the first transistor, and determine a pulse-width of the driving current. The driving-amplitude determining circuit is coupled to the second node, configured to determine amplitude of the driving current. The reset circuit is configured to reset the voltage of the first node and the second node when voltage of a reset signal is varied.

Description

pixel circuit

The present disclosure is related to a pixel circuit, especially a normally black (Normally black, NB for short) pixel circuit.

In a display panel generally adopting normally white (NW) type, in order to generate a low grayscale display image, it is necessary to increase the voltage of the control terminal of the driving transistor coupled to the light-emitting unit to turn it off, thereby reducing the light-emitting unit. Lighting time to reduce grayscale.

However, in a large-sized display panel, there may be a large voltage drop and signal delay between the pixel circuit and the input point of the power signal, causing the display panel to leak light and the screen cannot be completely black.

The present disclosure provides a pixel circuit including a light emitting unit, a first transistor, a driving circuit, a pulse width determination circuit, a driving amplitude determination circuit, and a reset circuit. The first transistor is coupled to the light emitting unit and is turned on in response to the voltage of the first node. The driving circuit is used for providing a driving current corresponding to the voltage of the second node to the first transistor. The pulse width determination circuit is used for selectively transmitting the first driving signal to the first node to turn on the first transistor to determine the pulse width of the driving current. The driving amplitude determining circuit is coupled to the second node and is used for determining the amplitude of the driving current according to the first data signal in response to the first gate signal. The reset circuit is used for resetting the voltage of the first node and the voltage of the second node when the voltage of the reset signal changes.

One of the advantages of the above-mentioned pixel circuit is that the normally black pixel circuit can solve the problem that the display panel cannot be completely black due to light leakage when the display panel is in a low gray scale condition.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the specific embodiments described are only used to explain the present invention, not to limit the present invention, and the description of the structure and operation is not used to limit the order of its execution, any The structure of recombining the components to produce a device with equal efficacy is within the scope of the disclosure of the present invention.

Unless otherwise specified, the terms used throughout the specification and the scope of the patent application generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content. Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the present disclosure.

FIG. 1 is a functional block diagram of a pixel circuit 100 according to some embodiments of this disclosure. As shown in FIG. 1 , the pixel circuit 100 includes a light emitting unit EU, a first transistor T1 , a driving circuit 110 , a pulse width determination circuit 120 , a driving amplitude determination circuit 130 and a reset circuit 140 .

Structurally, the first transistor T1 is coupled between the light emitting unit EU and the driving circuit 110 . The control terminal of the first transistor T1 is coupled to the first node N1. The pulse width determination circuit 120 is coupled to the control terminal of the first transistor T1 through the first node N1. The reset circuit 140 is respectively coupled to the control terminal of the first transistor T1 and the driving circuit 110 at the first node N1 and the second node N2. The driving amplitude determination circuit 130 is coupled to the driving circuit 110 through the second node N2.

In operation, the driving circuit 110 is used to provide the driving current I corresponding to the voltage of the second node N2 to the first transistor T1 , and the first transistor T1 is used to turn on in response to the voltage of the first node N1 . In the embodiments of the present disclosure, the first transistor T1 is an N-type metal-oxide-semiconductor (NMOS).

The pulse width determination circuit 120 is used for selectively transmitting the driving signal VDD to the first node N1 to turn on the first transistor T1 to determine the pulse width of the driving current I. More specifically, the pulse width determination circuit 120 determines whether to enable or not according to the data signal Sdata1 and the pulse signal SWEEP. When the pulse width determination circuit 120 is enabled, the first node N1 will receive the driving signal VDD, thereby turning on the first transistor T1. That is, the pulse width determination circuit 120 can control the on-time of the first transistor T1 to determine the pulse width of the driving current I.

The driving amplitude determination circuit 130 is used for transmitting the data signal Sdata2 to the second node N2 in response to the gate signal GS. In this way, the driving circuit 110 can generate the driving current I corresponding to the data signal Sdata2.

The reset circuit 140 is used for resetting the voltage of the first node N1 and the voltage of the second node N2 when the voltage of the reset signal Vini changes.

FIG. 2 is a schematic diagram of the pixel circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 2 , the driving circuit 110 includes a second transistor T2 and a third transistor T3 , each of which includes a first terminal, a second terminal and a control terminal, and the driving circuit 110 further includes a first capacitor C1 . The first end of the second transistor T2 is used to receive the driving signal VDD, the second end of the second transistor T2 is coupled to the first end of the first transistor T1, and the control end of the second transistor T2 is coupled to the second node N2. The first end of the third transistor T3 is coupled to the second node N2, the second end of the third transistor T3 is coupled to the first end of the first transistor T1, and the control end of the third transistor T3 is used for receiving the compensation signal Comp. In some embodiments, the first capacitor C1 of the driving circuit 110 may be omitted.

The pulse width determination circuit 120 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, each of which includes a first terminal, a second terminal and a control terminal, and the pulse width determines The circuit 120 further includes a second capacitor C2 and a third capacitor C3. The first end of the fourth transistor T4 is coupled to the third node N3, the second end of the fourth transistor T4 is coupled to the first node N1, and the control end of the fourth transistor T4 is used for receiving the light-emitting signal EM. The first end of the fifth transistor T5 is used for receiving the driving signal VDD, the control end of the fifth transistor T5 is coupled to the fourth node N4, and the second end of the fifth transistor T5 is coupled to the third node N3. The first end of the sixth transistor T6 is coupled to the fourth node N4, the second end of the sixth transistor T6 is coupled to the third node N3, and the control end of the sixth transistor T6 is used for receiving the compensation signal Comp. The first end of the seventh transistor T7 is used for receiving the data signal Sdata1, the second end of the seventh transistor T7 is coupled to the fifth node N5, and the control end of the seventh transistor T7 is used for receiving the gate signal GS. The second capacitor C2 includes a first terminal and a second terminal. The first end of the second capacitor C2 is used for receiving the pulse signal SWEEP, and the second end of the second capacitor C2 is coupled to the fifth node N5. The third capacitor C3 is coupled between the fourth node N4 and the fifth node N5.

The driving amplitude determination circuit 130 includes an eighth transistor T8 and a fourth capacitor C4. The eighth transistor T8 includes a first terminal, a second terminal and a control terminal. The first end of the eighth transistor T8 is used for receiving the data signal Sdata2, and the control end of the eighth transistor T8 is used for receiving the gate signal GS. The fourth capacitor C4 includes a first terminal and a second terminal. The first end of the fourth capacitor C4 is coupled to the second end of the eighth transistor T8, and the second end of the fourth capacitor C4 is coupled to the second node N2.

The reset circuit 140 includes a ninth transistor T9, a tenth transistor T10 including an eleventh transistor T11, each of which includes a first terminal, a second terminal and a control terminal, and the reset circuit 140 further includes a fifth capacitor C5. The first terminal of the ninth transistor T9 is coupled to the first node N1, the second terminal of the ninth transistor T9 is used for receiving the driving signal VSS, and the control terminal of the ninth transistor T9 is used for receiving the reset signal Vini. The fourth capacitor C4 includes a first terminal and a second terminal. The first end of the fourth capacitor C4 is coupled to the first node N1, and the second end of the fourth capacitor C4 is used for receiving the driving signal VSS. The first end of the tenth transistor T10 is used for receiving the reset signal Vini, the second end of the tenth transistor T10 is coupled to the second node N2, and the control end and the first end of the tenth transistor T10 are coupled to the sixth Node N6. The first end of the eleventh transistor T11 is coupled to the fourth node N4, and the second end of the eleventh transistor T11 and the control end of the eleventh transistor T11 are coupled to the sixth node N6.

In the embodiment of FIG. 2 , the driving circuit 110 and the pulse width determining circuit 120 are coupled to the same signal source to receive the same driving signal VDD together. However, in some other embodiments, the driving circuit 110 and the pulse width determining circuit 120 can be respectively coupled to different signal sources to receive different driving signals respectively. By separating the signal sources of the driving circuit 110 and the pulse width determining circuit 120, the voltage drop (IR-drop) of the driving signal VDD can be prevented from being coupled to the first end of the fifth transistor T5 of the pulse width determining circuit 120, In order to avoid the voltage drop provided by the pulse width determination circuit 120 to the first node N1.

FIG. 3 is a signal timing waveform diagram of the pixel circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 3 , the signal timing of the pixel circuit 100 can be divided into four stages, namely, a reset stage, a compensation stage, a writing stage, and a light-emitting stage. The driving signal VDD has a first voltage level V1, and the driving signal VSS has a second voltage level V2 lower than the first voltage level V1. The data signals Sdata1 and Sdata2 respectively have a data voltage Vs1 and a data voltage Vs2.

In some embodiments, the data voltage Vs1 and the data voltage Vs2 are between the first voltage level V1 and the second voltage level V2, and the data voltage Vs1 and the data voltage Vs2 may be equal voltage levels.

FIGS. 4A to 4D are schematic diagrams of operations of the pixel circuit 100 according to an embodiment of the present disclosure. The operation flow of the pixel circuit 100 will be described in more detail below with reference to FIGS. 4A to 4D in conjunction with FIG. 3 .

As shown in FIG. 4A, in the reset stage, the reset signal Vini will provide a logic high level (Logic High level, such as the second voltage level V2 that can turn on the P-type transistor), so that the corresponding ninth voltage The crystal T9, the tenth transistor T10 and the eleventh transistor T11 are turned on. The light-emitting signal EM, the compensation signal Comp, and the gate signal GS provide a logic low level (for example, a first voltage level V1 that can turn off the P-type transistor), so that the corresponding third transistor T3 , the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

At this time, the first node N1 receives the driving signal VSS through the ninth transistor T9, so that the voltage of the first node N1 is reset to the second voltage level V2. The second node N2, the fourth node N4 and the sixth node N6 will receive the reset signal Vini, so that the voltages of the second node N2, the fourth node N4 and the sixth node N6 are also reset to the second voltage level V2 .

In this way, the first transistor T1 is turned off due to the second voltage level V2 of the first node N1. The second transistor T2 and the fifth transistor T5 are turned on respectively due to the second voltage level V2 of the second node N2 and the fourth node N4, so that the driving signal VDD can be transmitted to the second voltage level of the second transistor T2, respectively. terminal and the third node N3.

As shown in FIG. 4B, in the compensation stage, the reset signal Vini changes from the second voltage level V2 to the first voltage level V1, so that the corresponding ninth transistor T9, tenth transistor T10 and eleventh transistor Transistor T11 is turned off. The compensation signal Comp and the gate signal GS will change from the first voltage level V1 to the second voltage level V2, so that the corresponding third transistor T3, sixth transistor T6, seventh transistor T7 and eighth transistor are enabled Transistor T8. The light-emitting signal EM will continue to provide a logic low level, so that the fourth transistor T4 is kept off.

At this time, a charging path is formed between the second node N2 and the second terminal of the second transistor T2, so that the high voltage of the second terminal of the second transistor T2 (ie, the first voltage level V1 of the driving signal VDD ) will continue to charge the second node N2 through the third transistor T3 until the difference between the voltage of the second node N2 and the voltage of the first end of the second transistor T2 reaches the threshold voltage of the second transistor T2, The data signal Sdata2 having the second voltage level V2 is used to stabilize the first end of the fourth capacitor C4.

On the other hand, a charging path is also formed between the fourth node N4 and the second end of the fifth transistor T5, so that the high voltage of the second end of the fifth transistor T5 (that is, the first voltage of the driving signal VDD The level V1) will continue to charge the fourth node N4 through the sixth transistor T6 until the difference between the voltage of the fourth node N4 and the voltage of the first end of the fifth transistor T5 reaches the threshold voltage of the fifth transistor T5 So far, the data signal Sdata1 with the second voltage level V2 is used to stabilize the fifth node N5.

As shown in FIG. 4C , in the writing stage, the compensation signal Comp changes from the second voltage level V2 to the first voltage level, so that the corresponding third transistor T3 and sixth transistor T6 are turned off. The light-emitting signal EM and the reset signal Vini continue to provide a logic low level, so that the corresponding fourth transistor T4 , the ninth transistor T9 , the tenth transistor T10 and the eleventh transistor T11 are kept off. The gate signal GS will provide a logic high level pulse during the writing phase to enable the corresponding seventh transistor T7 and the eighth transistor T8, so that the data voltage Vs1 of the data signal Sdata1 and the data voltage Vs2 of the data signal Sdata2 , which can be coupled to the fourth node N4 and the second node N2 through the third capacitor C3 and the fourth capacitor C4, respectively.

As shown in FIG. 4D, in the light-emitting stage, the gate signal GS, the compensation signal Comp and the reset signal Vini will provide a logic low level, so that the corresponding third transistor T3, sixth transistor T6, and seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned off. The light-emitting signal EM changes from the first voltage level V1 to the second voltage level V2, so as to enable the fourth transistor T4.

At this time, the pulse signal SWEEP will drop from the first voltage level V1 to the second voltage level V2, and the above-mentioned voltage will be changed (that is, the first voltage level V1 and the second voltage level) by the third capacitor C3. difference between bits V2) is coupled to the fourth node N4.

In this way, the voltage of the fourth node N4 will start to decrease with the change of the voltage level of the pulse signal SWEEP, until the difference between the voltage of the fourth node N4 and the voltage of the first end of the fifth transistor T5 is less than the first The threshold voltage of the five transistors T5 makes the fifth transistor T5 turn on.

Therefore, in the light-emitting stage, the driving circuit 110 provides the driving current I to the first transistor T1 according to the voltage of the second node N2. The pulse width determination circuit 120 transmits the driving signal VDD to the first node N1 through the fourth transistor T4 and the fifth transistor T5, so as to set the voltage of the first node N1 to the first voltage level V1, and then turns on The first transistor T1. The driving current I can drive the light-emitting unit EU to emit light through the first transistor T1.

FIG. 5 is a schematic diagram of a pixel circuit 500 according to another embodiment of the present disclosure. The pixel circuit 500 includes a light-emitting unit EU, a first transistor T1 , a driving circuit 510 , a pulse width determination circuit 520 , a driving amplitude determination circuit 530 and a reset circuit 540 . The driving circuit 510 and the reset circuit 540 can be implemented by the driving circuit 110 and the reset circuit 140 shown in FIG. 2 , respectively.

Structurally, the connection relationship of the light-emitting unit EU, the first transistor T1, the driving circuit 110, the pulse width determination circuit 120, the driving amplitude determination circuit 130 and the reset circuit 140 in the above-mentioned FIG. 2 is also applicable to the light-emitting in FIG. 5. The unit EU, the first transistor T1 , the driving circuit 510 , the pulse width determination circuit 520 , the driving amplitude determination circuit 530 and the reset circuit 540 are not repeated here.

The pulse width determination circuit 520 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second capacitor C2 and a third capacitor C3. The connection relationship of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the second capacitor C2 and the third capacitor C3 in the pulse width determination circuit 120 in FIG. The pulse width determination circuit 520 .

It is worth noting that the first terminal and the control terminal of the seventh transistor T7 of the pulse width determining circuit 520 are respectively used for receiving the data signal Sdata and the gate signal GS1.

The driving amplitude determination circuit 530 includes an eighth transistor T8 and a fourth capacitor C4. The first terminal and the control terminal of the eighth transistor T8 of the driving amplitude determination circuit 530 are respectively used for receiving the data signal Sdata and the gate signal GS2. The fourth capacitor C4 of the driving amplitude determination circuit 530 is coupled between the eighth transistor T8 of the driving amplitude determination circuit 530 and the second node N2.

FIG. 6 is a signal timing waveform diagram according to the pixel circuit 500 of FIG. 5 . The pixel circuit 500 operates according to the signal timing waveform diagram of FIG. 6 . The difference between the operation of the pixel circuit 500 and the operation of the pixel circuit 100 is that the pixel circuit 100 jointly controls the turn-on and turn-off of the seventh transistor T7 and the eighth transistor T8 through the gate signal GS. 500 controls the turn-on and turn-off of the seventh transistor T7 and the eighth transistor T8 respectively through the gate signal GS1 and the gate signal GS2.

That is, in the writing stage, the driving amplitude determination circuit 530 is enabled in response to a pulse of the gate signal GS2 in the first sub-period to transmit the data voltage Vs of the data signal Sdata to the second node N2. Then, the pulse width determination circuit 520 is enabled in response to a pulse of the gate signal GS1 in the second sub-period, so as to transmit the data Vs of the data signal Sdata to the fourth node N4.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the appended patent application.

100: pixel circuit 500: pixel circuit EU: light-emitting unit T1~T11: Transistor 110,510: Driver circuit 120,520: Pulse width determination circuit 130,530: Drive amplitude determination circuit 140,540: Reset Circuit VDD: drive signal VSS: drive signal Vini: reset signal Comp: Compensation signal Sdata, Sdata1, Sdata2: data signal SWEEP: Pulse signal GS, GS1, GS2: gate signal EM: luminous signal V1: The first voltage level V2: The second voltage level Vs, Vs1, Vs2: Data voltage N1~N7: Node I: drive current

FIG. 1 is a functional block diagram of a pixel circuit according to some embodiments of this disclosure. FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. FIG. 3 is a signal timing waveform diagram of a pixel circuit according to an embodiment of the present disclosure. FIGS. 4A to 4D are schematic diagrams of operations of a pixel circuit according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure. FIG. 6 is a signal timing waveform diagram according to the pixel circuit of FIG. 5 .

100: pixel circuit

EU: light-emitting unit

T1: Transistor

110: Drive circuit

120: Pulse width determination circuit

130: Drive amplitude determination circuit

140: reset circuit

VDD: drive signal

VSS: drive signal

Vini: reset signal

Sdata1, Sdata2: data signal

SWEEP: Pulse signal

GS: gate signal

EM: luminous signal

N1,N2: Nodes

I: drive current

Claims (10)

A pixel circuit, comprising: a light-emitting unit; a first transistor coupled to the light-emitting unit to be turned on in response to a voltage of a first node; a drive circuit to provide a voltage corresponding to a second node a driving current to the first transistor; a pulse width determining circuit for selectively transmitting a first driving signal to the first node to turn on the first transistor to determine a pulse of the driving current wave width; a driving amplitude determination circuit, coupled to the second node, for determining the amplitude of the driving current; and a reset circuit for resetting the voltage of the first node when the voltage of a reset signal changes voltage and the voltage of the second node. The pixel circuit of claim 1, wherein the driving circuit comprises: a second transistor including a first terminal, a second terminal and a control terminal, and the second terminal of the second transistor is coupled to A first end of the first transistor, the control end of the second transistor is coupled to the second node; and a third transistor includes a first end, a second end and a control end, the The first end of the third transistor is coupled to the second node, the second end of the third transistor is coupled to the first end of the first transistor, and the control end of the third transistor is used for A compensation signal is received. The pixel circuit of claim 2, wherein the driving circuit further comprises: a first capacitor including a first terminal and a second terminal, the first terminal of the first capacitor is coupled to the second transistor The first end of the first capacitor is coupled to the second node. The pixel circuit of claim 2, wherein the first end of the second transistor is coupled to the pulse width determination circuit and used for receiving the first driving signal. The pixel circuit of claim 2, wherein the first end of the second transistor is used for receiving a second driving signal. The pixel circuit of claim 1, wherein the pulse width determination circuit comprises: a fourth transistor including a first terminal, a second terminal and a control terminal, the first terminal of the fourth transistor The terminal is coupled to a third node, the second terminal of the fourth transistor is coupled to the first node, the control terminal of the fourth transistor is used for receiving a light-emitting signal; a fifth transistor includes a first one end, a second end and a control end, the first end of the fifth transistor is used for receiving the first driving signal, the control end of the fifth transistor is coupled to a fourth node, the fifth the second end of the transistor is coupled to the third node; a sixth transistor including a first terminal, a second terminal and a control terminal, the first terminal of the sixth transistor is coupled to the fourth node, and the second terminal of the sixth transistor is coupled to the third node, the control end of the sixth transistor is used for receiving a compensation signal; a seventh transistor includes a first end, a second end and a control end, the first end of the seventh transistor One end is used for receiving a first data signal, the second end of the seventh transistor is coupled to the fifth node, the control end of the seventh transistor is used for receiving a first gate signal; a second The capacitor includes a first end and a second end, the first end of the second capacitor is used for receiving a pulse signal, the second end of the second capacitor is coupled to a fifth node; and a third capacitor , coupled between the fourth node and the fifth node. The pixel circuit of claim 6, wherein the driving amplitude determination circuit comprises: an eighth transistor including a first end, a second end and a control end; and a fourth capacitor including a first terminal and a second terminal, the first terminal of the fourth capacitor is coupled to the second terminal of the eighth transistor, and the second terminal of the fourth capacitor is coupled to the second node. The pixel circuit of claim 7, wherein when the control end of the eighth transistor is used to receive the first gate signal, the first end of the eighth transistor is used to receive a second data signal. The pixel circuit of claim 7, wherein when the control end of the eighth transistor is used to receive a second gate signal, the first end of the eighth transistor is used to receive the first data signal. The pixel circuit of claim 1, wherein the reset circuit comprises: a ninth transistor including a first terminal, a second terminal and a control terminal, and the first terminal of the eighth transistor is coupled to connected to the first node, the second end of the ninth transistor is used for receiving a third driving signal, the control end of the ninth transistor is used for receiving the reset signal; a fifth capacitor includes a first one end and a second end, the first end of the fifth capacitor is coupled to the first node, the second end of the fifth capacitor is used for receiving the third driving signal; a tenth transistor includes a a first end, a second end and a control end, the first end of the tenth transistor is used for receiving the reset signal, the second end of the tenth transistor is coupled to the second node, the first The control terminal of the tenth transistor and the first terminal of the tenth transistor are coupled to a sixth node; and an eleventh transistor includes a first terminal, a second terminal and a control terminal, the The first end of the eleventh transistor is coupled to a fourth node, and the second end of the eighth transistor and the control end of the eleventh transistor are coupled to the sixth node.

Images