CN113808543A

CN113808543A - Pixel circuit

Info

Publication number: CN113808543A
Application number: CN202111114135.7A
Authority: CN
Inventors: 林信安; 张哲嘉; 吴尚杰; 郭豫杰
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-01-14
Filing date: 2021-09-23
Publication date: 2021-12-17
Anticipated expiration: 2041-09-23
Also published as: TWI761037B; TW202228110A; CN113808543B

Abstract

A pixel circuit includes a light emitting unit, a first transistor, a driving circuit, a pulse width determination circuit, a driving amplitude determination circuit, and a reset circuit. The first transistor is coupled to the light emitting unit and is turned on in response to a voltage of the first node. The driving circuit is used for providing a driving current corresponding to the voltage of the second node to the first transistor. The pulse width determination circuit is used for selectively transmitting the first driving signal to the first node to turn on the first transistor so as to determine the pulse width of the driving current. The driving amplitude determining circuit is coupled to the second node for determining the amplitude of the driving current. The reset circuit is used for resetting the voltage of the first node and the voltage of the second node when the voltage of the reset signal changes.

Description

Pixel circuit

Technical Field

The present disclosure relates to a pixel circuit, and more particularly, to a pixel circuit of Normally Black (NB) type.

Background

In a Normally White (NW) display panel, to generate a low gray level display image, the voltage of the control terminal of the driving transistor coupled to the light emitting unit needs to be increased to turn off the driving transistor, so as to reduce the light emitting time of the light emitting unit and reduce the gray level.

However, in a large-sized display panel, a large voltage drop and a signal delay may occur between the pixel circuit and the power signal input point, which causes a problem that the display panel leaks light and cannot completely black the display.

Disclosure of Invention

The present disclosure provides a pixel circuit including a light emitting unit, a first transistor, a driving circuit, a pulse width determination circuit, a driving amplitude determination circuit, and a reset circuit. The first transistor is coupled to the light emitting unit and is turned on in response to a voltage of the first node. The driving circuit is used for providing a driving current corresponding to the voltage of the second node to the first transistor. The pulse width determination circuit is used for selectively transmitting the first driving signal to the first node to turn on the first transistor so as to determine the pulse width of the driving current. The driving amplitude determining circuit is coupled to the second node and is used for responding to the first grid signal so as to determine the amplitude of the driving current according to the first data signal. The reset circuit is used for resetting the voltage of the first node and the voltage of the second node when the voltage of the reset signal changes.

One of the advantages of the pixel circuit is that the normally black pixel circuit solves the problem that the display panel cannot be completely black due to light leakage in the low gray scale condition.

Drawings

Fig. 1 is a functional block diagram of a pixel circuit according to some embodiments of the present disclosure.

Fig. 2 is a schematic diagram of a pixel circuit according to an embodiment of the disclosure.

Fig. 3 is a waveform diagram illustrating signal timing of a pixel circuit according to an embodiment of the disclosure.

Fig. 4A to 4D are schematic diagrams illustrating an operation of a pixel circuit according to an embodiment of the disclosure.

Fig. 5 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

Fig. 6 is a signal timing waveform diagram illustrating the pixel circuit according to fig. 5.

Description of reference numerals:

100: pixel circuit

500: pixel circuit

EU: light emitting unit

T1-T11: transistor with a metal gate electrode

110,510: driving circuit

120,520: pulse width determination circuit

130,530: drive amplitude determination circuit

140,540: reset circuit

VDD: drive signal

VSS: drive signal

And (3) Vini: reset signal

Comp: compensating signal

Sdata, Sdata1, Sdata 2: data signal

Sweet: pulse signal

GS, GS1, GS 2: grid signal

EM: luminous signal

V1: first voltage level

V2: second voltage level

Vs, Vs1, Vs 2: data voltage

N1-N7: node point

I: drive current

Detailed Description

The following embodiments are described in detail with reference to the drawings, but the embodiments are only for explaining the present invention and not for limiting the present invention, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure with equivalent technical effects produced by the recombination of elements is within the scope of the present disclosure.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each term used in the art, in the disclosure herein, and in the specific context, unless otherwise indicated. Certain words used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the disclosure.

Fig. 1 is a functional block diagram of a pixel circuit 100 according to some embodiments of the present disclosure. As shown in fig. 1, the pixel circuit 100 includes a light emitting unit EU, a first transistor T1, a driving circuit 110, a pulse width determination circuit 120, a driving amplitude determination circuit 130, and a reset circuit 140.

Structurally, the first transistor T1 is coupled between the light emitting unit EU and the driving circuit 110. The control terminal of the first transistor T1 is coupled to the first node N1. The pulse width determining circuit 120 is coupled to the control terminal of the first transistor T1 through the first node N1. The reset circuit 140 is coupled to the control terminal of the first transistor T1 and the driving circuit 110 at the first node N1 and the second node N2, respectively. The driving amplitude determining circuit 130 is coupled to the driving circuit 110 through the second node N2.

In operation, the driving circuit 110 is configured to provide the driving current I corresponding to the voltage of the second node N2 to the first transistor T1, and the first transistor T1 is configured to turn on in response to the voltage of the first node N1. In the embodiment of the present disclosure, the first transistor T1 is an N-type metal oxide semiconductor conductor (NMOS).

The pulse width determining circuit 120 is used for selectively transmitting the driving signal VDD to the first node N1 to turn on the first transistor T1, thereby determining the pulse width of the driving current I. More specifically, the pulse width determining circuit 120 determines whether to enable the data signal Sdata1 and the pulse signal SWEEP. When the pulse width determining circuit 120 is enabled, the first node N1 receives the driving signal VDD, thereby turning on the first transistor T1. That is, the pulse width determining circuit 120 can control the on-time of the first transistor T1 to determine the pulse width of the driving current I.

The driving amplitude determining circuit 130 is configured to respond to the gate signal GS to transmit the data signal Sdata2 to the second node N2. Thus, the driving circuit 110 can generate the driving current I corresponding to the data signal Sdata 2.

The reset circuit 140 is configured to reset the voltage of the first node N1 and the voltage of the second node N2 when the voltage of the reset signal Vini changes.

Fig. 2 is a schematic diagram of a pixel circuit 100 according to an embodiment of the disclosure. As shown in fig. 2, the driving circuit 110 includes a second transistor T2, a third transistor T3 each including a first terminal, a second terminal and a control terminal, and the driving circuit 110 further includes a first capacitor C1. The first terminal of the second transistor T2 is for receiving the driving signal VDD, the second terminal of the second transistor T2 is coupled to the first terminal of the first transistor T1, and the control terminal of the second transistor T2 is coupled to the second node N2. The first terminal of the third transistor T3 is coupled to the second node N2, the second terminal of the third transistor T3 is coupled to the first terminal of the first transistor T1, and the control terminal of the third transistor T3 is used for receiving the compensation signal Comp. In some embodiments, the first capacitor C1 of the driving circuit 110 may be omitted.

The pulse width determination circuit 120 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, each of which includes a first terminal, a second terminal, and a control terminal, and the pulse width determination circuit 120 further includes a second capacitor C2 and a third capacitor C3. The first terminal of the fourth transistor T4 is coupled to the third node N3, the second terminal of the fourth transistor T4 is coupled to the first node N1, and the control terminal of the fourth transistor T4 is configured to receive the light emitting signal EM. The first terminal of the fifth transistor T5 is for receiving the driving signal VDD, the control terminal of the fifth transistor T5 is coupled to the fourth node N4, and the second terminal of the fifth transistor T5 is coupled to the third node N3. The first terminal of the sixth transistor T6 is coupled to the fourth node N4, the second terminal of the sixth transistor T6 is coupled to the third node N3, and the control terminal of the sixth transistor T6 is used for receiving the compensation signal Comp. A first terminal of the seventh transistor T7 is coupled to receive the data signal Sdata1, a second terminal of the seventh transistor T7 is coupled to the fifth node N5, and a control terminal of the seventh transistor T7 is coupled to receive the gate signal GS. The second capacitor C2 includes a first terminal and a second terminal. The first terminal of the second capacitor C2 is coupled to receive the pulse signal SWEEP, and the second terminal of the second capacitor C2 is coupled to the fifth node N5. The third capacitor C3 is coupled between the fourth node N4 and the fifth node N5.

The driving amplitude decision circuit 130 includes an eighth transistor T8 and a fourth capacitor C4. The eighth transistor T8 includes a first terminal, a second terminal, and a control terminal. The first terminal of the eighth transistor T8 is for receiving the data signal Sdata2, and the control terminal of the eighth transistor T8 is for receiving the gate signal GS. The fourth capacitor C4 includes a first terminal and a second terminal. A first terminal of the fourth capacitor C4 is coupled to the second terminal of the eighth transistor T8, and a second terminal of the fourth capacitor C4 is coupled to the second node N2.

The reset circuit 140 includes a ninth transistor T9, a tenth transistor T10 including an eleventh transistor T11 each including a first terminal, a second terminal, and a control terminal, and the reset circuit 140 further includes a fifth capacitor C5. A first terminal of the ninth transistor T9 is coupled to the first node N1, a second terminal of the ninth transistor T9 is for receiving the driving signal VSS, and a control terminal of the ninth transistor T9 is for receiving the reset signal Vini. The fourth capacitor C4 includes a first terminal and a second terminal. The first terminal of the fourth capacitor C4 is coupled to the first node N1, and the second terminal of the fourth capacitor C4 is for receiving the driving signal VSS. A first terminal of the tenth transistor T10 is coupled to receive the reset signal Vini, a second terminal of the tenth transistor T10 is coupled to the second node N2, and a control terminal and a first terminal of the tenth transistor T10 are coupled to the sixth node N6. A first terminal of the eleventh transistor T11 is coupled to the fourth node N4, and a second terminal of the eleventh transistor T11 and a control terminal of the eleventh transistor T11 are coupled to the sixth node N6.

In the embodiment of fig. 2, the driving circuit 110 and the pulse width determining circuit 120 are coupled to the same signal source to commonly receive the same driving signal VDD. However, in some other embodiments, the driving circuit 110 and the pulse width determining circuit 120 may be respectively coupled to different signal sources to respectively receive different driving signals. By making the signal sources of the driving circuit 110 and the pulse width determination circuit 120 independent, it is possible to prevent the voltage drop (IR-drop) of the driving signal VDD from being coupled to the first terminal of the fifth transistor T5 of the pulse width determination circuit 120 to prevent the voltage supplied to the first node N1 by the pulse width determination circuit 120 from dropping.

Fig. 3 is a signal timing waveform diagram of the pixel circuit 100 according to an embodiment of the disclosure. As shown in fig. 3, the signal timing of the pixel circuit 100 can be divided into four stages, namely, a reset stage, a compensation stage, a write stage and a light-emitting stage. The driving signal VDD has a first voltage level V1, and the driving signal VSS has a second voltage level V2 lower than the first voltage level V1. The data signals Sdata1 and Sdata2 respectively have a data voltage Vs1 and a data voltage Vs 2.

In some embodiments, the data voltages Vs1 and Vs2 are between the first voltage level V1 and the second voltage level V2, and the data voltages Vs1 and Vs2 may be equal voltage levels.

Fig. 4A to 4D are schematic diagrams illustrating an operation of the pixel circuit 100 according to an embodiment of the disclosure. The operation flow of the pixel circuit 100 will be described in more detail below with reference to fig. 4A to 4D in conjunction with fig. 3.

As shown in fig. 4A, in the reset phase, the reset signal Vini provides a Logic High level (e.g., the second voltage level V2 for turning on the P-type transistor), so that the corresponding ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned on. The emission signal EM, the compensation signal Comp, and the gate signal GS provide a Logic Low level (e.g., the first voltage level V1 for turning off the P-type transistor), so that the corresponding third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

At this time, the first node N1 receives the driving signal VSS through the ninth transistor T9, such that the voltage of the first node N1 is reset to the second voltage level V2. The second node N2, the fourth node N4 and the sixth node N6 receive the reset signal Vini, such that the voltages of the second node N2, the fourth node N4 and the sixth node N6 are also reset to the second voltage level V2.

In this way, the first transistor T1 is turned off by the second voltage level V2 of the first node N1. The second transistor T2 and the fifth transistor T5 are turned on by the second voltage level V2 of the second node N2 and the fourth node N4, respectively, so that the driving signal VDD can be transmitted to the second terminal of the second transistor T2 and the third node N3, respectively.

As shown in fig. 4B, in the compensation phase, the reset signal Vini changes from the second voltage level V2 to the first voltage level V1, such that the corresponding ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned off. The compensation signal Comp and the gate signal GS are changed from the first voltage level V1 to the second voltage level V2 to enable the corresponding third transistor T3, sixth transistor T6, seventh transistor T7 and eighth transistor T8. The emission signal EM continuously provides a logic low level, so that the fourth transistor T4 is kept turned off.

At this time, a charging path is formed between the second node N2 and the second terminal of the second transistor T2, such that the high voltage at the second terminal of the second transistor T2 (i.e., the first voltage level V1 of the driving signal VDD) continuously charges the second node N2 through the third transistor T3 until the difference between the voltage at the second node N2 and the voltage at the first terminal of the second transistor T2 reaches the threshold voltage of the second transistor T2, wherein the data signal Sdata2 having the second voltage level V2 is used to stabilize the first terminal of the fourth capacitor C4.

On the other hand, a charging path is also formed between the fourth node N4 and the second terminal of the fifth transistor T5, such that the high voltage at the second terminal of the fifth transistor T5 (i.e., the first voltage level V1 of the driving signal VDD) continuously charges the fourth node N4 through the sixth transistor T6 until the difference between the voltage at the fourth node N4 and the voltage at the first terminal of the fifth transistor T5 reaches the threshold voltage of the fifth transistor T5, wherein the data signal Sdata1 having the second voltage level V2 is used to stabilize the fifth node N5.

As shown in fig. 4C, in the write phase, the compensation signal Comp is changed from the second voltage level V2 to the first voltage level, such that the corresponding third transistor T3 and the sixth transistor T6 are turned off. The emission signal EM and the reset signal Vini continuously provide a logic low level, so that the corresponding fourth transistor T4, ninth transistor T9, tenth transistor T10 and eleventh transistor T11 remain turned off. The gate signal GS provides a logic high level pulse to enable the corresponding seventh transistor T7 and eighth transistor T8 during the write phase, such that the data voltage Vs1 of the data signal Sdata1 and the data voltage Vs2 of the data signal Sdata2 are coupled to the fourth node N4 and the second node N2 through the third capacitor C3 and the fourth capacitor C4, respectively.

As shown in fig. 4D, in the light emitting period, the gate signal GS, the compensation signal Comp and the reset signal Vini provide logic low levels, such that the corresponding third transistor T3, sixth transistor T6, seventh transistor T7, eighth transistor T8, ninth transistor T9, tenth transistor T10 and eleventh transistor T11 are turned off. The emission signal EM changes from the first voltage level V1 to the second voltage level V2 to enable the fourth transistor T4.

At this time, the pulse signal sweet falls from the first voltage level V1 to the second voltage level V2, and the voltage variation (i.e., the difference between the first voltage level V1 and the second voltage level V2) is coupled to the fourth node N4 through the third capacitor C3.

In this way, the voltage of the fourth node N4 starts to decrease with the change of the voltage level of the pulse signal sweet until the difference between the voltage of the fourth node N4 and the voltage of the first terminal of the fifth transistor T5 is less than the threshold voltage of the fifth transistor T5, such that the fifth transistor T5 is turned on.

Therefore, in the light emitting period, the driving circuit 110 provides the driving current I to the first transistor T1 according to the voltage of the second node N2. The pulse width determining circuit 120 transmits the driving signal VDD to the first node N1 through the fourth transistor T4 and the fifth transistor T5 to set the voltage of the first node N1 to the first voltage level V1, thereby turning on the first transistor T1. The driving current I drives the light emitting unit EU to emit light through the first transistor T1.

Fig. 5 is a schematic diagram of a pixel circuit 500 according to another embodiment of the disclosure. The pixel circuit 500 includes a light emitting unit EU, a first transistor T1, a driving circuit 510, a pulse width determination circuit 520, a driving amplitude determination circuit 530, and a reset circuit 540. The driving circuit 510 and the reset circuit 540 can be implemented by the driving circuit 110 and the reset circuit 140 of fig. 2, respectively.

Structurally, the connection relationship among the light emitting unit EU, the first transistor T1, the driving circuit 110, the pulse width determining circuit 120, the driving amplitude determining circuit 130 and the reset circuit 140 in fig. 2 is also applicable to the light emitting unit EU, the first transistor T1, the driving circuit 510, the pulse width determining circuit 520, the driving amplitude determining circuit 530 and the reset circuit 540 in fig. 5, and is not repeated herein.

The pulse width determination circuit 520 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second capacitor C2, and a third capacitor C3. The connection relationship among the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the second capacitor C2 and the third capacitor C3 of the pulse width determination circuit 120 of fig. 2 is also applicable to the pulse width determination circuit 520 of fig. 5.

It is noted that the first terminal and the control terminal of the seventh transistor T7 of the pulse width determining circuit 520 are respectively configured to receive the data signal Sdata and the gate signal GS 1.

The driving amplitude decision circuit 530 includes an eighth transistor T8 and a fourth capacitor C4. The first terminal and the control terminal of the eighth transistor T8 of the driving amplitude determining circuit 530 are respectively configured to receive the data signal Sdata and the gate signal GS 2. The fourth capacitor C4 of the driving amplitude determination circuit 530 is coupled between the eighth transistor T8 of the driving amplitude determination circuit 530 and the second node N2.

Fig. 6 is a timing waveform diagram of signals shown in the pixel circuit 500 according to fig. 5. The pixel circuit 500 operates according to the signal timing waveform diagram of fig. 6. The operation of the pixel circuit 500 is different from that of the pixel circuit 100 in that the pixel circuit 100 controls the seventh transistor T7 and the eighth transistor T8 to be turned on and off together by the gate signal GS, and the pixel circuit 500 controls the seventh transistor T7 and the eighth transistor T8 to be turned on and off respectively by the gate signal GS1 and the gate signal GS 2.

That is, in the write phase, the driving amplitude determination circuit 530 is enabled in response to a pulse of the gate signal GS2 in the first sub-period to transmit the data voltage Vs of the data signal Sdata to the second node N2. Then, the pulse width determination circuit 520 is enabled in response to a pulse of the gate signal GS1 in the second sub-period to transmit the data Vs of the data signal Sdata to the fourth node N4.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the present disclosure, and therefore, the scope of the present disclosure should be determined by that of the appended claims.

Claims

1. A pixel circuit, comprising:

a light emitting unit;

a first transistor coupled to the light emitting unit and turned on in response to a voltage of a first node;

a driving circuit for providing a driving current corresponding to a voltage of a second node to the first transistor;

a pulse width decision circuit for selectively transmitting a first driving signal to the first node to turn on the first transistor to determine a pulse width of the driving current;

a driving amplitude determining circuit coupled to the second node for determining the amplitude of the driving current; and

a reset circuit for resetting the voltage of the first node and the voltage of the second node when the voltage of a reset signal changes.

2. A pixel circuit as claimed in claim 1, wherein the driving circuit comprises:

a second transistor including a first terminal, a second terminal and a control terminal, wherein the second terminal of the second transistor is coupled to a first terminal of the first transistor, and the control terminal of the second transistor is coupled to the second node; and

a third transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second node, the second terminal of the third transistor is coupled to the first terminal of the first transistor, and the control terminal of the third transistor is configured to receive a compensation signal.

3. A pixel circuit as claimed in claim 2, wherein the driving circuit further comprises:

a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the first terminal of the second transistor, and the second terminal of the first capacitor is coupled to the second node.

4. The pixel circuit of claim 2, wherein the first terminal of the second transistor is coupled to the pulse width determining circuit and configured to receive the first driving signal.

5. The pixel circuit of claim 2, wherein the first terminal of the second transistor is configured to receive a second driving signal.

6. A pixel circuit as claimed in claim 1, wherein said pulse width determining circuit comprises:

a fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to a third node, the second terminal of the fourth transistor is coupled to the first node, and the control terminal of the fourth transistor is configured to receive a light emitting signal;

a fifth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is configured to receive the first driving signal, the control terminal of the fifth transistor is coupled to a fourth node, and the second terminal of the fifth transistor is coupled to the third node;

a sixth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor is coupled to the fourth node, the second terminal of the sixth transistor is coupled to the third node, and the control terminal of the sixth transistor is configured to receive a compensation signal;

a seventh transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is configured to receive a first data signal, the second terminal of the seventh transistor is coupled to the fifth node, and the control terminal of the seventh transistor is configured to receive a first gate signal;

a second capacitor having a first end and a second end, the first end of the second capacitor being configured to receive a pulse signal, the second end of the second capacitor being coupled to a fifth node; and

a third capacitor coupled between the fourth node and the fifth node.

7. A pixel circuit as claimed in claim 6, wherein the drive amplitude decision circuit comprises:

an eighth transistor including a first terminal, a second terminal, and a control terminal; and

a fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is coupled to the second end of the eighth transistor, and the second end of the fourth capacitor is coupled to the second node.

8. The pixel circuit of claim 7, wherein the first terminal of the eighth transistor is configured to receive a second data signal when the control terminal of the eighth transistor is configured to receive the first gate signal.

9. The pixel circuit of claim 7, wherein the first terminal of the eighth transistor is configured to receive the first data signal when the control terminal of the eighth transistor is configured to receive a second gate signal.

10. The pixel circuit of claim 1, wherein the reset circuit comprises:

a ninth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the eighth transistor is coupled to the first node, the second terminal of the ninth transistor is configured to receive a third driving signal, and the control terminal of the ninth transistor is configured to receive the reset signal;

a fifth capacitor having a first end and a second end, wherein the first end of the fifth capacitor is coupled to the first node, and the second end of the fifth capacitor is used for receiving the third driving signal;

a tenth transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the tenth transistor being configured to receive the reset signal, the second terminal of the tenth transistor being coupled to the second node, the control terminal of the tenth transistor and the first terminal of the tenth transistor being coupled to a sixth node; and

an eleventh transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the eleventh transistor is coupled to the fourth node, and the second terminal of the eighth transistor and the control terminal of the eleventh transistor are coupled to the sixth node.