TWI742895B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a light unit, a first transistor, a second transistor, a control circuit, a compensation unit, a reset unit, a storage capacitor and a write unit. The first transistor is configured to pass a first driving signal to a first node according to a first emitting signal. The second transistor is coupled between the first node and a second node, and a control terminal of the second transistor is coupled to a third node. The control circuit is configured to conduct the light unit, the second node and a fourth node according to a second emitting signal. The compensation unit is configured to record a threshold voltage of the second transistor at the third node. The reset unit is configured to pass a reference voltage to the second node according to a second scan signal. The storage capacitor is coupled between the third node and the fourth node. The write unit is configured to pass a data voltage to the fourth node, in which the first emitting signal and the second emitting signal have a first pulse width and a first fixed phase shift, and the first scan signal and the second scan signal have a second pulse width and a second fixed phase shift.

Description

Pixel circuit

The present disclosure relates to a pixel circuit, especially to a pixel circuit including a compensation unit.

The pixel circuit of Active-Matrix Organic Light-Emitting Diode (AMOLED) displays uses thin-film transistors as driving and switching elements. However, under different semiconductor manufacturing processes, thin-film transistors will be affected by the process. The error or long-term operation may cause the degradation of component characteristics, such as the variation or drift of the threshold voltage, which causes the uniformity of the panel brightness to decrease, which in turn affects the picture quality.

In addition, for high-resolution or high-frequency displays, the limited compensation time will cause insufficient charge and discharge of the capacitor used to record the threshold voltage, resulting in poor compensation effects and degraded picture quality.

The present disclosure provides a pixel circuit, which includes a light-emitting unit, a first transistor, a second transistor, a control circuit, a compensation unit, a reset unit, a storage capacitor, and a writing unit. The first transistor is used for transmitting the first driving signal to the first node according to the first light-emitting signal. The second transistor is coupled between the first node and the second node, wherein the control terminal of the second transistor is coupled to the third node. The control circuit is coupled to the light-emitting unit, the second node and the fourth node, and is used for turning on the light-emitting unit, the second node and the fourth node according to the second light-emitting signal. The compensation unit is used for selectively turning on the first node and the third node according to the first scan signal, so as to record the threshold voltage of the second transistor at the third node. The reset unit is used for selectively transmitting the reference voltage to the second node according to the second scan signal. The storage capacitor is coupled between the third node and the fourth node. The writing unit is used to selectively provide the data voltage to the fourth node, wherein the first light-emitting signal and the second light-emitting signal have a first pulse width and a first fixed phase difference, and the first scan signal and the second scan signal It has a second pulse width and a second fixed phase difference.

The present disclosure provides a pixel circuit, which includes a light-emitting unit, a first transistor, a second transistor, a control circuit, a compensation unit, a reset unit, a storage capacitor, and a writing unit. The first transistor is used for transmitting the first driving signal to the first node according to the first light-emitting signal. The second transistor is coupled between the first node and the second node, wherein the control terminal of the second transistor is coupled to the third node. The control circuit is coupled to the light-emitting unit, the second node and the fourth node, and is used for turning on the light-emitting unit, the second node and the fourth node according to the second light-emitting signal. The reset unit is used for selectively transmitting the reference voltage to the second node according to the first scan signal. The compensation unit is used for selectively turning on the first node and the third node according to the second scan signal, so as to record the threshold voltage of the second transistor at the third node. The storage capacitor is coupled between the third node and the fourth node. The writing unit is used to selectively provide a data voltage to the fourth node, wherein the first light-emitting signal and the second light-emitting signal have the same pulse width and a fixed phase difference, and the period of the second scan signal is greater than that of the first The period of the scan signal.

One of the advantages of the above-mentioned pixel circuit is that when it is applied to a high-resolution or high-frequency display, it can still obtain sufficient time for compensation and writing, so as to increase the uniformity of the panel brightness.

Another advantage of the above-mentioned pixel circuit is that it can reduce the layout area of the gate drive array to be applied to a display with a narrow frame.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only used to explain the present invention and are not used to limit the present invention. The description of structural operations is not used to limit the order of its execution. The recombined structure of the components produces devices with equal effects, which are all covered by the disclosure of the present invention.

Unless otherwise specified, the terms used in the entire specification and the scope of the patent application usually have the usual meaning of each term used in this field, in the content disclosed here, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the present disclosure.

In this text, when an element is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used to describe different elements in this document, the terms are only used to distinguish elements or operations described in the same technical terms.

In addition, the terms "include", "include", "have", "contain", etc. used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one or more of the related listed items and all combinations thereof.

FIG. 1 is a schematic diagram of a pixel circuit 100 according to an embodiment of the present disclosure. In some embodiments, the pixel circuit 100 can be used in an Active-Matrix Organic Light-Emitting Diode (AMOLED) display.

As shown in FIG. 1, the pixel circuit 100 includes a light-emitting unit EU, a first transistor T1, a second transistor T2, a control circuit 110, a compensation unit 120, a reset unit 130, a storage capacitor Cs, and a writing unit 140.

Structurally, the control terminal of the first transistor T1 receives the first light-emitting signal EM[N+1], the first terminal of the first transistor T1 receives the first driving signal OVDD, and the second terminal of the first transistor T1 is coupled The first node N1. The second transistor T2 is coupled between the first node N1 and the second node N2, and the control terminal of the second transistor T2 is coupled to the third node N3. The control circuit 110 is coupled to the light emitting unit EU, the second node N2 and the fourth node N4. The second end of the light emitting unit EU is coupled to the second driving signal OVSS. The compensation unit 120 is coupled between the first node N1 and the third node N3. The reset unit 130 is coupled to the control circuit 110 at the second node N2. The storage capacitor Cs is coupled between the third node N3 and the fourth node N4. The writing unit 140 is coupled to the fourth node N4.

In some embodiments, the control circuit 110 includes a third transistor T3 and a fourth transistor T4. The third transistor T3 includes a first terminal, a second terminal and a control terminal. The first terminal of the third transistor T3 is coupled to the second node N2, and the second terminal of the third transistor T3 is coupled to the light emitting unit EU. The fourth transistor T4 includes a first terminal, a second terminal and a control terminal. The first terminal of the fourth transistor T4 is coupled to the second node N2, and the second terminal of the fourth transistor T4 is coupled to the fourth node N4, The control terminal of the fourth transistor T4 is coupled to the control terminal of the third transistor T3 and is used for receiving the second light-emitting signal EM[N].

In some embodiments, the compensation unit 120 includes a fifth transistor T5. The fifth transistor T5 includes a first terminal, a second terminal, and a control terminal. The first terminal of the fifth transistor T5 is coupled to the third node N3, and the second terminal of the fifth transistor T5 is coupled to the first node N1, the control terminal of the fifth transistor T5 is used to receive the scan signal S1[N].

In some embodiments, the reset unit 130 includes a sixth transistor T6. The sixth transistor T6 includes a first terminal, a second terminal and a control terminal. The first terminal of the sixth transistor T6 is coupled to the second node N2, and the second terminal of the sixth transistor T6 is used to receive the reference voltage Vref , The control terminal of the sixth transistor T6 is used to receive the scan signal S1[N+1].

In some embodiments, the writing unit 140 includes a seventh transistor T7, the first terminal of the seventh transistor T7 receives the data voltage Vdata, the second terminal of the seventh transistor T7 is coupled to the fourth node N4, and the seventh transistor T7 is coupled to the fourth node N4. The control terminal of the transistor T7 is used to receive the scan signal S1[N].

In operation, the first transistor T1 is used to transmit the first driving signal OVDD to the first node N1 according to the first light-emitting signal EM[N+1]. The control circuit 110 is used for turning on the light emitting unit EU, the second node N2 and the fourth node N4 according to the second light emitting signal EM[N]. The compensation unit 120 is used for selectively turning on the first node N1 and the third node N3 according to the scan signal S1[N], so as to record the threshold voltage of the second transistor T2 at the third node N3. The reset unit 130 is used for selectively transmitting the reference voltage Vref to the second node N2 according to the scan signal S1[N+1]. The writing unit 140 is used for selectively providing the data voltage Vdata to the fourth node N4 according to the scan signal S1[N].

That is, in the embodiment of the first picture element circuit 100, the control terminal of the seventh transistor T7 and the control terminal of the fifth transistor T5 are coupled to each other to jointly receive the scan signal S1[N]. For the convenience of description, the specific operations of each element in the pixel circuit 100 will be described in more detail in the following paragraphs with drawings.

FIG. 2 is a signal timing waveform diagram drawn according to the pixel circuit 100 in FIG. 1. As shown in FIG. 2, in the signal timing of the pixel circuit 100, one cycle includes four phases, which are an initial phase, a compensation/write phase, a reset phase, and a light-emitting phase. In some embodiments, the first light-emitting signal EM[N+1] and the second light-emitting signal EM[N] have the same pulse width L1 and a fixed phase difference P1, and the scan signal S1[N] and the scan signal S1[ N+1] also have the same pulse width L2 and fixed phase difference P2.

In some embodiments, the pulse width L1 can be the same as the pulse width L2, and the phase difference P1 can also be the same as the phase difference P2. In some embodiments, the second light-emitting signal EM[N] can be input into a shift register (not shown) to generate the first light-emitting signal EM[N+1], and the scan signal S1[N] The input shift register (not shown) generates the scan signal S1[N+1].

Hereinafter, the operation flow of the pixel circuit 100 will be described in more detail by using FIGS. 3A to 3D in conjunction with FIG. 2. FIG. 3A is a schematic diagram of the operation of the pixel circuit 100 in the initial stage according to some embodiments of the present disclosure. FIG. 3B is a schematic diagram of the operation of the pixel circuit 100 in the compensation/write phase according to some embodiments of the present disclosure. FIG. 3C is a schematic diagram of the operation of the pixel circuit 100 in the reset stage according to some embodiments of the present disclosure. FIG. 3D is a schematic diagram of the operation of the pixel circuit 100 in the light-emitting stage according to some embodiments of the present disclosure.

As shown in FIG. 3A, in the initial stage, the first light emitting signal EM[N+1] provides the enabling voltage level V1 to turn on the first transistor T1, so as to transmit the first driving signal OVDD to the first node N1. The scan signal S1[N] provides the enable voltage level V2 to turn on the fifth transistor T5 to transmit the first driving signal OVDD to the third node N3, and turn on the seventh transistor T7 to turn on the voltage level of the fourth node N4 Set to the data voltage Vdata. The second light-emitting signal EM[N] and the scanning signal S1[N+1] provide the disable voltage level V0 to turn off the third transistor T3, the fourth transistor T4, and the sixth transistor T6.

As shown in Figure 3B, during the compensation/write phase, the voltage of the first light-emitting signal EM[N+1] changes from the enable voltage level V1 to the disable voltage level V0, so that the first transistor T1 is turned off Off. The second light-emitting signal EM[N] continuously provides the disable voltage level V0, turning off the third transistor T3 and the fourth transistor T4 (ie, the control circuit 110). The scan signal S1[N] maintains the enabling voltage level V2, and continuously turns on the fifth transistor T5 and the seventh transistor T7. The voltage of the scan signal S1[N+1] changes from the disable voltage level V0 to the enable voltage level V2, so that the sixth transistor T6 is turned on, so as to pass the threshold voltage of the second transistor T2 through the fifth transistor T5 (that is, the compensation unit 120) is stored to the third node N3.

Specifically, when the sixth transistor T6 is turned on, the control terminal of the second transistor T2 (that is, the third node N3) starts to discharge the second terminal (that is, the second node N2), so that the third node The voltage level of N3 changes to Vref-Vth2, where the symbol "Vth2" is the threshold voltage of the second transistor T2.

As shown in FIG. 3C, in the reset stage, the first light-emitting signal EM[N+1] maintains the disable voltage level V0 to continuously turn off the first transistor T1. The voltage of the second light emitting signal EM[N] changes from the disable voltage level V0 to the enable voltage level V1, so that the third transistor T3 and the fourth transistor T4 (ie, the control circuit 110) are turned on. The scan signal S1[N] changes from the enable voltage level V2 to the disable voltage level V0 to turn off the fifth transistor T5 and the seventh transistor T7. The scan signal S1[N+1] maintains the enable voltage level V2, and continues to turn on the sixth transistor T6 to reset the voltage levels of the second node N2 and the fourth node N4 to the reference voltage Vref.

As shown in FIG. 3D, during the light-emitting phase, the voltage of the first light-emitting signal EM[N+1] changes from the disable voltage level V0 to the enable voltage level V1 to turn on the first transistor T1. The second light emitting signal EM[N] maintains the enabling voltage level V1, so that the third transistor T3 and the fourth transistor T4 (ie, the control circuit 110) are continuously turned on. The scan signal S1[N] maintains the disable voltage level V0, and keeps the fifth transistor T5 and the seventh transistor T7 off. The scan signal S1[N+1] changes from the enable voltage level V2 to the disable voltage level V0, so that the sixth transistor T6 is turned off. At this time, the second transistor T2 generates a driving current I according to the voltage difference between the third node N3 and the second node N2, and outputs the driving current I to the light-emitting unit EU so that the pixel circuit 100 emits light during the light-emitting phase.

In summary, the advantage of the pixel circuit 100 is that it can use the signals generated by the next-stage shift register (for example, the first light-emitting signal EM[N+1] and the scanning signal S1[N+1]). The layout area of the gate drive array is reduced to be applied to a display with a narrow bezel.

FIG. 4 is a schematic diagram of a pixel circuit 400 according to another embodiment of the present disclosure. The pixel circuit 400 includes a light-emitting unit EU, a first transistor T1, a second transistor T2, a control circuit 410, a compensation unit 420, a reset unit 430, a storage capacitor Cs, and a writing unit 440, wherein the control circuit 410, the compensation unit The 420 and the reset unit 430 can be implemented by the control circuit 110, the compensation unit 120, and the reset unit 130 in FIG. 1, respectively.

It is worth noting that, in the embodiment of FIG. 4, the writing unit 440 determines whether to turn on to transfer the data voltage Vdata according to the scan signal S2[N]. That is, the control terminal of the seventh transistor T7 receives the scan signal S2[N] and selectively provides the data voltage Vdata to the fourth node N4, wherein the scan signal S2[N] is different from the scan signal S1[N] The pulse width and period of the pulse. In some embodiments, the scan signal S1[N] and the scan signal S2[N] can be provided to the display through different scan lines. The connection relationship of the remaining components in the pixel circuit 400 is similar to the operation of the pixel circuit 100, and will not be repeated here.

FIG. 5 is a signal timing waveform diagram drawn according to the pixel circuit 400 in FIG. 4. As shown in FIG. 5, in the signal timing of the pixel circuit 400, one cycle includes five phases, which are an initial phase, a compensation phase, a writing phase, a reset phase, and a light-emitting phase. The waveforms of the first light-emitting signal EM[N+1], the second light-emitting signal EM[N], the scan signal S1[N], and the scan signal S1[N+1] are similar to those of the embodiment in FIG. 2, and are not here. Go into details again.

Therefore, the turn-on and turn-off of the writing unit 440 are independently controlled by the scan signal S2[N], and will not be delayed by the compensation time of the pixel circuit 400, so that the pixel circuit 400 is used for high resolution or high operating frequency. When the display is displayed, sufficient time can still be obtained for compensation and writing to increase the uniformity of the displayed picture.

FIG. 6 is a schematic diagram of a pixel circuit 600 according to another embodiment of the present disclosure. The pixel circuit 600 includes a light emitting unit EU, a first transistor T1, a second transistor T2, a control circuit 610, a compensation unit 620, a reset unit 630, a storage capacitor Cs, and a writing unit 640. The control circuit 610 can be implemented by the control circuit 110 in FIG. 1. The connection relationship of the various elements in the pixel circuit 600 is also similar to the pixel circuit 100 in FIG. 1, and will not be repeated here.

It is worth noting that in the embodiment of FIG. 6, the compensation unit 620 selectively turns on the first node N1 and the third node N3 according to the scan signal S2[N] to record the threshold voltage of the second transistor T2 At the third node N3. The reset unit 630 selectively transmits the reference voltage Vref to the second node N2 according to the scan signal S1[N]. The writing unit 640 selectively provides the data voltage Vdata to the fourth node N4 according to the scan signal S2[N].

FIG. 7 is a signal timing waveform diagram drawn according to the pixel circuit 600 in FIG. 6. As shown in FIG. 7, the pixel circuit 600 can be operated in two working modes, a normal mode and an energy-saving mode. In the normal mode, the signal timing of the pixel circuit 600 is similar to that of Fig. 2. A cycle includes four stages, namely the initial stage, the compensation/write stage, the reset stage, and the light-emitting stage.

In the energy-saving mode, the signal timing of the pixel circuit 600 includes two phases in one cycle, namely the reset phase and the light-emitting phase. The waveforms of the first light-emitting signal EM[N+1], the second light-emitting signal EM[N], and the scanning signal S1[N] in the energy-saving mode are similar to those in the general mode, and will not be repeated here. The scanning signal S2[N] has a pulse wave per cycle in the normal mode, and maintains the disabled voltage level in the energy-saving mode. In other words, in the energy-saving mode, the period of the scan signal S2[N] will be greater than the period of the scan signal S1[N].

In some embodiments, the scanning signal S2[N] has a lower frequency (for example, 1 Hz). For example, the pixel circuit 600 can execute the normal mode once and the power-saving mode 59 times in one second.

In some embodiments, when the display displays a low-frame image, the signal waveform of the pixel circuit 600 will switch from the normal mode to the energy-saving mode. For example, when the display displays a static picture, the pixel circuit 600 generates the above-mentioned static picture display before the normal mode, and in the energy-saving mode, performs a reset phase and a light-emitting phase to maintain the display of the previous frame .

Although the content of this disclosure has been disclosed in the above embodiments, it is not intended to limit the content of this disclosure. Anyone with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to those defined by the attached patent application scope.

100, 400, 600: pixel circuit EU: Light-emitting unit T1~T7: Transistor 110, 410, 610: control circuit 120,420,620: Compensation unit 130,430,630: reset unit Cs: storage capacitor 140,440,640: write unit OVDD: the first drive signal OVSS: second drive signal EM[N],EM[N+1]: Luminous signal S1[N],S1[N+1],S2[N]: Scan signal Vref: Reference voltage Vdata: data voltage N1~N4: Node Vth2: critical voltage L1, L2: pulse width P1, P2: phase difference V1, V2: enable voltage level V0: disable voltage level I: drive current

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. Fig. 2 is a signal timing waveform diagram drawn according to the pixel circuit in Fig. 1. FIG. 3A is a schematic diagram of the operation of the pixel circuit in the initial stage according to some embodiments of the present disclosure. FIG. 3B is a schematic diagram of the operation of the pixel circuit in the compensation/write stage according to some embodiments of the present disclosure. FIG. 3C is a schematic diagram of the operation of the pixel circuit in the reset stage according to some embodiments of the present disclosure. FIG. 3D is a schematic diagram of the operation of the pixel circuit in the light-emitting stage according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure. FIG. 5 is a signal timing waveform diagram drawn according to the pixel circuit in FIG. 4. FIG. FIG. 6 is a schematic diagram of a pixel circuit according to still another embodiment of the present disclosure. FIG. 7 is a timing waveform diagram of the signal drawn based on the pixel circuit in FIG. 6.

100: pixel circuit

EU: Light-emitting unit

T1~T7: Transistor

110: control circuit

120: Compensation unit

130: reset unit

Cs: storage capacitor

140: write unit

OVDD: the first drive signal

OVSS: second drive signal

EM[N],EM[N+1]: Luminous signal

S1[N],S1[N+1]: Scan signal

Vref: Reference voltage

Vdata: data voltage

N1~N4: Node

Claims (10)

A pixel circuit includes: a light-emitting unit; a first transistor for transmitting a first driving signal to a first node according to a first light-emitting signal; and a second transistor coupled to the first node Between the node and a second node, wherein a control terminal of the second transistor is coupled to a third node; a control circuit is coupled to the light-emitting unit, the second node and a fourth node for The light-emitting unit, the second node, and the fourth node are turned on according to a second light-emitting signal; a compensation unit is used to selectively turn on the first node and the third node according to a first scan signal to The threshold voltage of the second transistor is recorded at the third node; a reset unit for selectively transmitting a reference voltage to the second node according to a second scan signal; a storage capacitor coupled to the third node Between the node and the fourth node; and a writing unit for selectively providing a data voltage to the fourth node; wherein the first light-emitting signal and the second light-emitting signal have a first pulse width And a first fixed phase difference, and the first scan signal and the second scan signal have a second pulse width and a second fixed phase difference, wherein the writing unit includes a seventh transistor, the seventh A first end of the transistor is used to receive the data voltage, and a second end of the seventh transistor is coupled to Connected to the fourth node, a control terminal of the seventh transistor is used to receive the first scan signal. In a reset phase, the seventh transistor is turned off according to the first scan signal, and the control circuit The second node and the fourth node are turned on, and the reset unit resets the voltage levels of the second node and the fourth node to the reference voltage according to the second scan signal. The pixel circuit according to claim 1, wherein the control circuit includes: a third transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled Connected to the second node, the second end of the third transistor is coupled to the light-emitting unit; and a fourth transistor including a first end, a second end and a control end, wherein the fourth transistor The first end of the crystal is coupled to the second node, the second end of the fourth transistor is coupled to the fourth node, and the control end of the fourth transistor is coupled to the control end of the third transistor Connected and used to receive the second luminous signal. The pixel circuit of claim 1, wherein the compensation unit includes: a fifth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled Connected to the third node, the second end of the fifth transistor is coupled to the first node, and the control end of the fifth transistor is used for receiving the first scan signal. The pixel circuit according to claim 3, wherein the reset unit includes: a sixth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor Coupled to the second node, the second terminal of the sixth transistor is used for receiving the reference voltage, and the control terminal of the sixth transistor is used for receiving the second scan signal. A pixel circuit includes: a light-emitting unit; a first transistor for transmitting a first driving signal to a first node according to a first light-emitting signal; and a second transistor coupled to the first node Between the node and a second node, wherein a control terminal of the second transistor is coupled to a third node; a control circuit is coupled to the light-emitting unit, the second node and a fourth node for The light-emitting unit, the second node, and the fourth node are turned on according to a second light-emitting signal; a compensation unit is used to selectively turn on the first node and the third node according to a first scan signal to The threshold voltage of the second transistor is recorded at the third node; a reset unit for selectively transmitting a reference voltage to the second node according to a second scan signal; a storage capacitor coupled to the third node Between the node and the fourth node; and A writing unit for selectively providing a data voltage to the fourth node; wherein the first light-emitting signal and the second light-emitting signal have a first pulse width and a first fixed phase difference, and the The first scan signal and the second scan signal have a second pulse width and a second fixed phase difference, the writing unit includes a seventh transistor, and a control terminal of the seventh transistor is used to receive a The third scan signal selectively provides the data voltage to the fourth node, wherein the third scan signal is different from the first scan signal. A pixel circuit includes: a light-emitting unit; a first transistor for transmitting a first driving signal to a first node according to a first light-emitting signal; and a second transistor coupled to the first node Between the node and a second node, wherein a control terminal of the second transistor is coupled to a third node; a control circuit is coupled to the light-emitting unit, the second node and a fourth node for The light-emitting unit, the second node, and the fourth node are turned on according to a second light-emitting signal; a reset unit for selectively transmitting a reference voltage to the second node according to a first scan signal; a compensation unit , For selectively turning on the first node and the third node according to a second scan signal, so as to record the threshold voltage of the second transistor at the third node; A storage capacitor, coupled between the third node and the fourth node; and a writing unit, for selectively providing a data voltage to the fourth node; wherein the first light-emitting signal and the fourth node The two light-emitting signals have the same pulse width and a fixed phase difference, and the period of the second scan signal is greater than the period of the first scan signal. The pixel circuit of claim 6, wherein the control circuit includes: a third transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled Connected to the second node, the second end of the third transistor is coupled to the light-emitting unit; and a fourth transistor including a first end, a second end and a control end, wherein the fourth transistor The first end of the crystal is coupled to the second node, the second end of the fourth transistor is coupled to the fourth node, and the control end of the fourth transistor is coupled to the control end of the third transistor Connected and used to receive the second luminous signal. The pixel circuit according to claim 6, wherein the compensation unit includes: a fifth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled Connected to the third node, the second end of the fifth transistor is coupled to the first node, and the The control terminal is used for receiving the second scan signal. The pixel circuit according to claim 8, wherein the reset unit includes: a sixth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth transistor Coupled to the second node, the second terminal of the sixth transistor is used for receiving the reference voltage, and the control terminal of the sixth transistor is used for receiving the first scan signal. The pixel circuit according to claim 9, wherein the writing unit includes: a seventh transistor, a first end of the seventh transistor is used to receive the data voltage, and a second terminal of the seventh transistor The terminal is coupled to the fourth node, and a control terminal of the seventh transistor is coupled to the control terminal of the fifth transistor for receiving the second scan signal.

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