TWI681378B - Display panel - Google Patents

Abstract

A display panel includes a shift register circuit and a pixel circuit. The shift register circuit includes a first transistor coupled to the output terminal for the compensation signal. The pixel circuit includes a capacitor, second to fourth transistors, and a LED. One end of the capacitor receives the compensation signal and the other end is coupled to a first node. The second transistor receives a data signal according to a scan signal. The third transistor receives the compensation signal according to the scan signal. One end of the third transistor is coupled to the second node. One end of the fourth transistor is coupled to the second node, and the control end is coupled to one end of the capacitor. One end of the LED is coupled to the second node. The fourth transistor is the same as the first transistor.

Description

Display panel

The present disclosure relates to a display panel, in particular to a display panel capable of compensating for the threshold voltage variation of the transistors of the organic light-emitting diodes and the transistors of the shift register circuit.

Organic light-emitting diode (OLED) as a current-type light-emitting element has been increasingly used in high-performance displays. Compared with liquid crystal display (LCD), OLED has many advantages such as high contrast, ultra-thin, flexible and so on. However, brightness uniformity and afterimages are still the two main problems facing OLEDs at present, so these two problems need to be solved through compensation technology. Compensation methods can be divided into internal compensation and external compensation. Internal compensation refers to a method of compensating a sub-circuit built with transistors inside a pixel circuit. External compensation refers to a method of compensation through an external drive circuit.

Generally, the luminescence brightness of OLED is proportional to the current, and the current is provided by the transistor (TFT), in which factors such as the threshold voltage of the transistor changes with aging will affect the current size. The main purpose of the compensation technology is to eliminate the influence of these factors, so that the brightness of the pixel circuit reaches the desired value. However, the traditional compensation circuit has a large number of components, and it is difficult to achieve high resolution.

One aspect of this case is to provide a display panel. The display panel includes a first shift register circuit and a pixel circuit. The first shift register circuit includes a first transistor. The first transistor is coupled to the first output terminal. The first output terminal outputs a compensation signal. The pixel circuit includes a capacitor, a second transistor, a third transistor, a fourth transistor, and a light-emitting diode. The first end of the capacitor is used to receive the compensation signal, and the second end of the capacitor is coupled to the first node. The second transistor is used to receive the data signal according to the scan signal output by the first shift register circuit. The third transistor is used to receive the compensation signal according to the scanning signal. The first end of the third transistor is coupled to the second node. The control terminal of the fourth transistor is coupled to the second terminal of the capacitor, the first terminal of the fourth transistor is coupled to the second node, and the second terminal of the fourth transistor is used to receive the first power voltage. The first end of the light-emitting diode is coupled to the second node, and the second end of the light-emitting diode is used to receive the second power voltage. The fourth transistor is the same as the first transistor.

Therefore, according to the technical aspect of this case, the embodiment of this case provides a display panel to achieve combined compensation and dimming control functions. In addition, since in the embodiment of the present invention, the electrical proximity characteristics of adjacent transistors are utilized, and the transistors of the pixel circuit are compensated by shifting the temporary storage circuit, only three transistors and a capacitor are needed in the pixel circuit (3T1C) It can realize the functions of compensation and dimming control, and it has fewer components than the traditional compensation circuit.

100‧‧‧Display panel

110‧‧‧Gate driver

130‧‧‧ source driver

AA‧‧‧Display area

Pixel circuit from P11 to PMN‧‧‧

G1 to GM‧‧‧Gate line

S1 to SN‧‧‧ source line

115-1 to 115-M‧‧‧shift temporary storage circuit

200, 800, 1000‧‧‧shift temporary storage circuit

300, 500, 600, 700, 900 ‧‧‧ pixel circuits

400‧‧‧Signal waveform

OLED‧‧‧ LED

N1, N2‧‧‧ Node

EM[N], EM[N-1]‧‧‧Enable signal

EnB, EnA‧‧‧clock signal

VGL, VGH‧‧‧potential

Vcomp[N], Vcomp[N-1]‧‧‧Compensation signal

T1 to T12, Tc, Td

C1 to C3‧‧‧Capacitance

OT1, OT2‧‧‧ output

OVDD, OVSS‧‧‧Power supply voltage

Scan[N], Scan[N-1]‧‧‧Scan signal

Vdata‧‧‧Data signal

VH, VL, V1 to V3‧‧‧potential

TP1 to TP3 ‧‧‧ time interval

In order to make the above and other objects, features, advantages and embodiments of the disclosure document more obvious and understandable, the drawings are described as follows: Fig. 1 is a schematic diagram of a display panel according to some embodiments of the case; Fig. 2 is a schematic diagram of a shift temporary circuit according to some embodiments of the case; Fig. 3 is a schematic diagram according to the case A schematic diagram of a pixel circuit shown in some embodiments; FIG. 4 is a schematic diagram of a signal waveform diagram according to some embodiments of the case; FIG. 5 is a schematic diagram according to some embodiments of the case The operation schematic diagram of the pixel circuit operating in the reset time interval; FIG. 6 is an operation schematic diagram of a pixel circuit operating in the compensation time interval according to some embodiments of the case; FIG. 7 is an operation schematic diagram according to some embodiments of the case A schematic diagram of the operation of a pixel circuit operating in the light-emitting time interval; FIG. 8 is a schematic diagram of another shift register circuit according to some embodiments of the case; FIG. 9 is a schematic diagram of some embodiments according to the case A schematic diagram of another pixel circuit shown; and FIG. 10 is a schematic diagram of another shift register circuit according to some embodiments of the present case.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numbers indicate the same or similar elements or method flows Cheng.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a display panel 100 according to some embodiments of the present case. As shown in FIG. 1, the display panel 100 includes a gate driver 110, a source driver 130, and a display area AA. The display area AA includes a plurality of pixel circuits P11 to PMN, forming an M×N pixel array. The gate driver 110 includes a plurality of shift register circuits 115-1 to 115-M.

In terms of connection relationship, each of the plurality of shift register circuits 115-1 to 115-M is coupled to one of the plurality of gate lines G1 to GM. Each of the plurality of pixel circuits P11 to PMN is coupled to one of the plurality of gate lines G1 to GM and one of the plurality of source lines S1 to SN. In detail, the shift register circuit 115-1 is coupled to the gate line G1, the shift register circuit 115-2 is coupled to the gate line G2, and so on. The gate line G1 is coupled to the pixel circuits P11 to P1N, the gate line G2 is coupled to the pixel circuits P21 to P2N, and so on. The source line S1 is coupled to the pixel circuits P11 to PM1, the source line S2 is coupled to the pixel circuits P12 to PM2, and so on.

In addition, a plurality of shift register circuits 115-1 to 115-M are connected in series with each other to output scan signals to the plurality of pixel circuits P11 to PMN of the display area AA at regular intervals. Each of the shift register circuits 115-1 to 115-M delays the output of the input signal according to the clock signal to become the output signal. The shift register circuit of the next stage takes the output signal of the shift register circuit of the previous stage as the input signal, and then delays the output to become its own output signal, and passes through a plurality of coupled gate lines G1 to GM One of them will output the signal as For the scanning signal output, to update a part of the plurality of pixel circuits P11 to PMN coupled to one of the plurality of gate lines G1 to GM.

It should be noted that the display panel 100 shown in FIG. 1 is for illustrative purposes only, but the implementation of this case is not limited thereto.

The detailed structures of the shift register circuits 115-1 to 115-M and the pixel circuits P11 to PMN will be described below with reference to FIGS. 2 to 3.

Please refer to figure 2. FIG. 2 is a schematic diagram of a shift register circuit 200 according to some embodiments of the present case. The shift register circuit 200 shown in FIG. 2 can be used to represent one of the shift register circuits 115-1 to 115-M shown in FIG. As shown in FIG. 2, the shift register circuit 200 includes a plurality of transistors T1 to T9 and Tc and capacitors C1 and C2. The transistor Tc is coupled to the output terminal OT1, and the output terminal OT1 outputs the compensation signal Vcomp[N]. Vcomp[N] represents the compensation signal output by the shift register circuit 200 of the Nth stage.

Please refer to Figure 3. FIG. 3 is a schematic diagram of a pixel circuit 300 according to some embodiments of this case. The pixel circuit 300 shown in FIG. 3 can be used to represent one of the pixel circuits P11 to PMN shown in FIG. 1. As shown in FIG. 3, the pixel circuit 300 includes a plurality of transistors T10 to T12, a capacitor C3, and a light emitting diode OLED. It should be noted that in some embodiments, the pixel circuit 300 and the shift register circuit 200 are coupled to the same gate line.

In detail, the first end of the capacitor C3 is used to receive the compensation signal Vcomp[N], and the second end of the capacitor C3 is coupled to the node N1. Transistor T10 The control terminal of is used to receive the scan signal Scan[N] output from the shift register circuit 200, the first terminal of the transistor T10 is used to receive the data signal Vdata, and the second terminal of the transistor T10 is coupled to the node N1. The transistor T10 receives the data signal Vdata from one of the plurality of source lines S1 to SN according to the scan signal Scan[N].

The control terminal of the transistor T11 is used to receive the scan signal Scan[N] output from the shift register circuit 200, the first end of the transistor T11 is coupled to the node N2, and the second end of the transistor T11 is used to receive the compensation signal Vcomp[N]. The transistor T11 receives the compensation signal Vcomp[N] according to the scan signal Scan[N]. The control terminal of the transistor T12 is coupled to the node N1, the first terminal of the transistor T12 is coupled to the node N2, and the second terminal of the transistor T12 is used to receive the power supply voltage OVDD. The first end of the light emitting diode OLED is coupled to the node N2, and the second end of the light emitting diode OLED is used to receive the power supply voltage OVSS. In this embodiment, the output terminal OT1 of the shift register circuit 200 outputs the compensation signal Vcomp[N] to the first terminal of the capacitor C3 and the second terminal of the transistor T11.

It should be noted that in the embodiment of the present invention, the transistor T12 and the transistor Tc are transistors having the same specifications. For example, the parameters of the transistor mobility, threshold voltage, and channel width of the two are the same.

The detailed operation methods of the shift register circuits 115-1 to 115-M and the pixel circuits P11 to PMN will be described below with reference to FIGS. 4 to 7.

Please refer to Figure 4. FIG. 4 is a schematic diagram of a signal waveform diagram 400 according to some embodiments of this case. Please also refer to Figure 2. Scan[N] is the scan information output by the shift register 200 of the Nth stage In some embodiments, the scan signal is output from the output terminal OT2 of the shift register 200. Scam[N-1] is the scan signal output by the shift register 200 of the N-1th stage. Vcomp[N] is the compensation signal output by the shift register 200 of the Nth stage. In some embodiments, the compensation signal is output by the output terminal OT1 of the shift register 200. Vcomp[N-1] is the compensation signal output by the shift register 200 of the N-1th stage.

As shown in FIG. 4, the signal waveform diagram 400 includes a reset time interval TP1, a compensation time interval TP2, and a light emission time interval TP3. The detailed operations in each time interval will be described below with reference to Figures 5 to 7.

Please refer to Figure 4 and Figure 5 together. FIG. 5 is a schematic diagram illustrating an operation of a pixel circuit 300 operating in a reset time interval TP1 according to some embodiments of the present case.

As shown in FIG. 4, in the reset time interval TP1, the scan signal Scan[N] is at a high potential VH, and the compensation signal Vcomp[N] is at a potential V1.

As shown in FIG. 5, in the reset time interval TP1, the first end of the capacitor C3 is the potential V1 of the compensation signal Vcomp[N], and the potential V1 is a high potential. The capacitor C3 couples the high potential V1 from the first end of the capacitor C3 to the second end of the capacitor C3, that is, the voltage at the terminal N1 at this time is also the high potential V1. Since the voltage at the terminal N1 is the high potential V1 and the control terminal of the transistor T12 is the high potential V1, the transistor T12 is not turned on. In addition, since the scan signal Scan[N] is a high potential VH, both the control terminal of the transistor T10 and the control terminal of the transistor T11 receive the high potential VH, so neither the transistor T10 nor the transistor T11 conducts. through. However, since the transistors T11 and T12 are not turned on, the light-emitting diode OLED will not shine.

As can be seen from the above, in the embodiment of the present invention, in the reset time interval TP1, the transistor T12 and the light emitting diode OLED are turned off by means of capacitive coupling to achieve the function of electromagnetic dimming (EM dimming).

Please refer to Figure 4 and Figure 6 together. FIG. 6 is a schematic diagram illustrating an operation of a pixel circuit 300 operating in a compensation time interval TP2 according to some embodiments of the present case.

As shown in FIG. 4, during the compensation time interval TP2, the scan signal Scan[N] is at a low potential VL, and the compensation signal Vcomp[N] decreases from the potential V1 to the potential V2. It should be noted that the potential V2 is the potential V3 plus the voltage V _{TH_Tc of the} transistor Tc.

As shown in FIG. 6, in the compensation time interval TP2, the first end of the capacitor C3 drops from the potential V1 to the potential V2. Since the scan signal Scan[N] is a low potential VL, the control terminals of the transistors T10 and T11 receive the low potential VL of the scan signal Scan[N], so the transistors T10 and T11 are turned on. Since the transistor T10 is turned on, the data signal Vdata is transmitted to the node N1 through the transistor T10. Since the data voltage Vdata is a low voltage, the control terminal of the transistor T12 receives the low voltage data voltage Vdata, and the transistor T12 is turned on. Since both transistors T11 and T12 are on, current flows from OVDD to transistor T11 through transistor T12. At this time, the divided voltage of the node N2 is lower than the power supply voltage OVSS, so the light emitting diode OLED is not turned on.

As can be seen from the above, in the implementation of this case, during compensation In the interval TP2, the voltage of the anode (ie, node N2) of the light-emitting diode OLED is reset while writing the data signal Vdata, so that the anode of the light-emitting diode OLED is maintained at a lower voltage than the power supply voltage OVSS, To ensure that the light-emitting diode OLED will not shine.

In some embodiments, the voltage division of the node N2 is -5V, and the power supply voltage OVSS is -3.3V. However, the implementation of this case is not limited to this.

Please refer to Figure 4 and Figure 7 together. FIG. 7 is a schematic diagram illustrating an operation of a pixel circuit 300 operating in the light-emitting time interval TP3 according to some embodiments of the present case.

As shown in FIG. 4, during the light-emitting time interval TP3, the scan signal Scan[N] returns to the high potential VH, and the compensation signal Vcomp[N] decreases from the potential V2 to the potential V3. It should be noted that after the scan signal Scan[N] rises from the low potential VL to the high potential VH, the compensation signal Vcomp[N] decreases from the potential V2 to the potential V3, so as not to cause operation errors of the pixel circuit 300 .

As shown in FIG. 7, during the light-emitting time interval TP3, since the scan signal Scan[N] returns to the high potential VH, the control terminals of the transistors T10 and T11 receive the high potential VH of the scan signal Scan[N]. The crystals T10 and T11 are not conductive. At this time, the capacitor C3 is in a floating state. Since the potential of the first end of the capacitor C3 decreases from the potential V2 to the potential V3 (ie, V2-V _{TH_TC} ), due to capacitive coupling, when the potential of the first end of the capacitor C3 decreases across the voltage value of the voltage V _{TH_TC} , the capacitance of the capacitor C3 The potential at the second terminal will also decrease the voltage value across the voltage V _{TH_TC} . That is, the potential of the second end of the capacitor C3 will drop from the potential Vdata to Vdata-V _{TH_TC} . And because similar electrical characteristics of the transistor TC crystal T12, and therefore the threshold voltage of transistor T12 is _| V TH_T12 | the transistor Tc is the threshold voltage _| V TH_Tc | same, i.e., the potential _Vdata-V TH_TC = potential _Vdata-V TH_T12. In addition, since the potential Vdata-V _{TH_TC is} still low, the transistor T12 is turned on, and the current flows from the power supply voltage OVDD to the power supply voltage OVSS via the transistor T12 and the light emitting diode OLED. At this time, the light emitting diode OLED is illuminated.

The driving current I _OLED generated by the transistor T12 is known from "Formula 1". "Formula 1" is as follows:

As can be seen from the above, in the embodiment of the present invention, in the light-emitting time interval TP3, the driving transistor T12 can be compensated while controlling the light-emitting diode OLED to emit light.

In addition, please refer to Figure 1 as well. Since the transistors Tc of the shift temporary storage circuits 150A to 150M are similar to the transistors T12 of the pixel circuits P11 to PM1, in the embodiment of the present invention, the close proximity characteristics of the adjacent transistors are used. Therefore, through the above operation, The transistor T12 of the pixel circuits P11 to PM1 can be compensated by shifting the temporary storage circuits 150A to 150M.

As can be seen from the above, in the embodiment of the present invention, only three transistors and one capacitor (3T1C) are needed in the pixel circuit, which is less than the number of components in the conventional compensation circuit. In the implementation of this case, compensation and dimming control functions are combined. In detail, in the reset time interval TP1, the transistor T12 and the light-emitting diode OLED are turned off by means of capacitive coupling to achieve the function of electromagnetic dimming (EM dimming); During the time interval TP2, the voltage of the anode (ie, node N2) of the light-emitting diode OLED is reset while writing the data signal Vdata, so that the anode of the light-emitting diode OLED is maintained at a lower voltage than the power supply voltage OVSS, In order to ensure that the light-emitting diode OLED does not shine; in the light-emitting time interval TP3, the driving transistor T12 can be compensated while controlling the light-emitting diode OLED to emit light. In addition, the embodiment of the present invention also utilizes the close electrical characteristics of adjacent transistors to compensate the transistor Tc of the shift register circuits 150A to 150M while compensating the transistor T12 of the pixel circuits P11 to PM1.

Please refer back to Figure 2. As shown in FIG. 2, the shift register circuit 200 further includes transistors T9, T10, and T11. The transistor T9 is coupled to the output terminal OT1. Transistors T10 and T11 are coupled to the output terminal OT2. The output terminal OT2 is used to output the scan signal Scan[N] as shown in FIG. 4 to the pixel circuit 300 as shown in FIG. 3. It should be noted that, in the embodiment of the present invention, the signal output from the output terminal OT2 can be used as the enable signal EM[N] to be output to the shift register circuit of the next stage, and can also be used as the scan signal Scan[N ] Output to the pixel circuit 300.

The shift register circuit 200 as shown in FIG. 2 is for illustrative purposes only. Various forms of shift register circuit 200 cooperate with the signal waveform diagram 400 shown in FIG. 4 and shown in FIG. 3 The pixel circuit 300 can all realize the technical features of this case. The implementation of this case is not limited to the shift temporary storage circuit 200 of the type depicted in FIG. 2.

In addition, in practice, the transistors T1 to T12 and Tc can be implemented with P-type low-temperature polycrystalline silicon thin film transistors, but this embodiment is not limited thereto. For example, transistors T1 to T12, Tc can also use P-type amorphous silicon (amorphous silicon) thin film transistors. In some embodiments, N-type thin film transistors can also be used, and the invention does not limit the types of transistors used.

Please refer to figure 8. FIG. 8 is a schematic diagram of another shift register circuit 800 according to some embodiments of the present case. The difference between the shift register circuit 800 and the shift register circuit 200 in FIG. 2 is that the shift register circuit 800 further includes a transistor Td, and the remaining components and structures are the same as the shift register circuit 200. As shown in FIG. 8, the transistor Td and the transistor Tc are connected in parallel, and the transistor Td and the transistor Tc are the same. The number of transistors connected in parallel here can be adjusted according to the demand of the gate load, however, the number of transistors connected in parallel does not affect the compensation function in this case.

Please refer to Figure 9. FIG. 9 is a schematic diagram of another pixel circuit 900 according to some embodiments of the present case. The difference between the pixel circuit 900 and the pixel circuit 300 as shown in FIG. 3 is that the signal received at the second end of the transistor T11 is the compensation signal Vcomp[N-1], and the remaining components and structures and the shift pixel circuit 300 the same. That is, in the pixel circuit 900, the signal received by the second end of the transistor T11 is the compensation signal output by the shift register circuit of the previous stage. Please refer to FIG. 4 as well. During the compensation time interval TP2, the potential of the compensation signal Vcomp[N-1] drops to the potential V3, and the potential of the compensation signal Vcomp[N] at this time is the potential V2, which is the compensation signal Vcomp The potential of [N-1] is lower than that of the compensation signal Vcomp[N]. In this way, within the compensation time interval TP2, a lower voltage division can be produced at the anode end of the light-emitting diode OLED, and a better effect can be achieved when the voltage at the anode end of the light-emitting diode OLED is reset, and more Good control prevents the light-emitting diode OLED from glowing.

Please refer to Figure 10. FIG. 10 is a schematic diagram of another shift register circuit 1000 according to some embodiments of the present case. The difference between the shift register circuit 800 and the shift register circuit 200 in FIG. 2 is that the shift register circuit 800 does not include transistors T7 and T8, and the remaining components and structures are the same as the shift register circuit 200. That is, in the shift temporary storage circuit 1000, the circuits that output the compensation signal Vcomp[N] and the output scan signal Scan[N] or the enable signal EM[N] are separated and implemented by different circuits. In addition, the shift register circuit 1000 can also connect the transistor Td and the transistor Tc in parallel as shown in FIG. 8.

The shift register circuit 200 in FIG. 2, the pixel circuit 300 in FIG. 3, the pixel circuit 900 in FIG. 9, and the shift register circuit 1000 in FIG. 10 can be implemented in combination with each other. For example, the shift register circuit 200 in FIG. 2 can be used with the pixel circuit 300 in FIG. 3 or the pixel circuit 900 in FIG. 9, and the shift register circuit 1000 in FIG. 10 can be used with the third The pixel circuit 300 in the figure or the pixel circuit 900 in the ninth figure.

In summary, the display panel of the present disclosure can achieve combined compensation and dimming control functions. In addition, in the embodiment of the present invention, only three transistors and one capacitor (3T1C) are needed in the pixel circuit to realize the functions of compensation and dimming control, and the number of components in the compensation circuit is less than that of the conventional compensation circuit. In addition, in the embodiment of the present invention, and utilizing the characteristics of close proximity of the adjacent transistors, the transistors of the pixel circuit can be compensated for by shifting the temporary storage circuit through the above operation.

Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of patent application do not use the difference in names as a way to distinguish the components, but rather The difference in the function of the components is used as the basis for differentiation. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.

Although this disclosure has been disclosed as above by way of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this skill can make various changes and modifications within the spirit and scope of this disclosure, so this disclosure The protection scope of the content shall be deemed as defined by the scope of the attached patent application.

300‧‧‧Pixel circuit

OLED‧‧‧ LED

N1, N2‧‧‧ Node

Vcomp[N]‧‧‧Compensation signal

T10 to T12 ‧‧‧ transistor

C3‧‧‧Capacitance

OVDD, OVSS‧‧‧Power supply voltage

Scan[N]‧‧‧Scan signal

Vdata‧‧‧Data signal

Claims (10)

A display panel includes: a first shift temporary storage circuit, including a first transistor, coupled to a first output terminal, wherein the first output terminal outputs a compensation signal, wherein the first shift temporary storage The circuit further includes a fifth transistor parallel to the first transistor, and the fifth transistor is the same as the first transistor; a pixel circuit includes: a capacitor, wherein a first end of the capacitor is used To receive the compensation signal, and a second end of the capacitor is coupled to a first node; a second transistor for receiving a data signal according to a scan signal output by the first shift register circuit; A third transistor for receiving the compensation signal according to the scan signal, wherein a first end of the third transistor is coupled to a second node; a fourth transistor, wherein a control of the fourth transistor The terminal is coupled to the first node, a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is used to receive a first power supply voltage; a light emitting diode Body, wherein a first end of the light emitting diode is coupled to the second node, a second end of the light emitting diode is used to receive a second power supply voltage; wherein the fourth transistor and the first The transistor is the same. The display panel of claim 1, wherein the first shift The temporary storage circuit is used to output the compensation signal from the first output terminal to the first terminal of the capacitor of the pixel circuit and a second terminal of the third transistor of the pixel circuit. The display panel of claim 2, wherein the fifth transistor is coupled to the first output terminal, wherein the first shift register circuit further includes: a sixth transistor; and a seventh transistor, wherein the The sixth transistor and the seventh transistor are coupled to a second output terminal of the first shift register circuit, and the second output terminal of the first shift register circuit is used to output the scan signal to The pixel circuit. The display panel of claim 1, wherein the first shift register circuit is used to output the compensation signal of the first shift register circuit to the image from the first output terminal of the first shift register circuit The first end of the capacitor of the element circuit, wherein the display panel further includes: a second shift register circuit for outputting the second shift from a first output end of the second shift register circuit A second compensation signal of the temporary storage circuit is connected to a second end of the third transistor, wherein the second shift temporary storage circuit is a stage before the first shift temporary storage circuit. The display panel of claim 4, wherein the fifth transistor is coupled to the first output terminal of the first shift register circuit, wherein the first shift register circuit further includes: A sixth transistor; and a seventh transistor, wherein the sixth transistor and the seventh transistor are coupled to a second output terminal of the first shift temporary storage circuit, and the first shift temporary The second output terminal of the memory circuit is used to output the scan signal. The display panel of claim 1, wherein the compensation signal decreases from a first potential to a second potential within a compensation time interval, and decreases from the second potential to a third potential within a lighting time interval, wherein The second potential is the third potential plus the voltage across the first transistor. The display panel of claim 6, wherein after the scan signal is raised from a fourth potential to a fifth potential, the compensation signal is reduced from the second potential to the third potential. The display panel of claim 6, wherein the capacitor couples the first potential from the first end of the capacitor to the second end of the capacitor during a reset time interval, so that the fourth transistor does not conduct . The display panel of claim 6, wherein the potential of the second node is less than the second power supply voltage during the compensation time interval, so that the light emitting diode is not turned on, and the second transistor is turned on to transmit the data Signal to the second node. The display panel according to claim 6, in which the light is emitted During the time interval, the potential of the second node is the potential of the data signal minus the cross-voltage of the fourth transistor to compensate for the fourth transistor while the light-emitting diode is turned on.

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