CN111063297A

CN111063297A - Miniature micro LED display device

Info

Publication number: CN111063297A
Application number: CN202010109306.6A
Authority: CN
Inventors: 陈廷仰; 廖志洋
Original assignee: Yuchuang Semiconductor (guangzhou) Co Ltd
Current assignee: Yuchuang semiconductor (Nanjing) Co.,Ltd.
Priority date: 2020-02-22
Filing date: 2020-02-22
Publication date: 2020-04-24

Abstract

The invention discloses a micro LED display device, which comprises a plurality of pixels, wherein the plurality of pixels comprise: a first switch including a first transistor and a second transistor connected in parallel with each other, and including an input terminal connected to the data line and an output terminal connected to the first node; an input terminal including at least one transistor and connected to the first node and an output terminal connected to a second node; a driving transistor having an output terminal connected to the gate terminal of the second switch and connected between the first power supply voltage and the second power supply voltage; a first capacitor connected between the first node and the second power supply voltage; and a second capacitor connected between the second node and the second power supply voltage. The invention relates to a micro LED display device with high resolution, which can correct the leakage current of an analog switch and is suitable for a pixel circuit.

Description

Miniature micro LED display device

Technical Field

The invention relates to a display device, in particular to a micro LED display device.

Background

As the information society has developed, demands for Display devices have been increased, and various types of Display devices such as liquid crystal Display devices (liquid crystal Display devices), Plasma Display devices (Plasma Display devices), and Organic Light Emitting Display devices (Organic Light Emitting Display devices) have been widely used. Recently, attention is being given to a high-resolution display device (hereinafter referred to as ˝ micro LED display device ˝) using micro light emitting diodes (μ LEDs).

In order to fully realize vr (virtual reality), ar (augmented reality), and mr (mixed reality) technologies, more excellent display device characteristics are required, and accordingly, development of micro LED on Silicon or AMOLED on Silicon is in an increasing trend, and particularly, requirements for minimizing a pixel size for realizing high-resolution image quality are increasing.

Disclosure of Invention

The invention aims to provide a micro LED display device to solve the problems in the prior art.

In order to realize the purpose, the invention provides the following technical scheme:

a micro LED display device comprises a plurality of pixels, wherein each pixel comprises a first transistor and a second transistor which are connected in parallel, and then a first switch of an input terminal connected with a data line and an output terminal connected with a first node; an input terminal including at least one transistor and connected to the first node and an output terminal connected to a second node; a driving transistor having an output terminal connected to the gate terminal of the second switch and connected between the first power supply voltage and the second power supply voltage; a first capacitor connected between the first node and the second power supply voltage; and a second capacitor connected between the second node and the second power supply voltage.

The second switch includes a third transistor and a fourth transistor connected in parallel, the third transistor may be a P-channel transistor connected to its source terminal, and the fourth transistor may be an N-channel transistor connected to its source terminal.

The second switch includes a fifth transistor, which may be an N-channel transistor connected to its source terminal.

The second switch includes a sixth transistor, which may be a P-channel transistor connected to its source terminal.

The first transistor is a P-channel transistor, the second transistor is an N-channel transistor, the first transistor body is connectable to the first supply voltage, and the second transistor body is connectable to the second supply voltage.

The pixel includes: and the light emitting diode is connected between the first power supply voltage and the driving transistor.

The second capacitor has a larger capacity than the first capacitor.

The first capacitor may be a MOS capacitor and the second capacitor may be a MIM capacitor.

Compared with the prior art, the invention has the beneficial effects that: the invention relates to a micro LED display device with high resolution, which can correct the leakage current of an analog switch and is suitable for a pixel circuit.

Drawings

FIG. 1 is a schematic diagram of a manufacturing process of a display device according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a display device according to an embodiment of the invention.

FIG. 3 is an embodiment of a pixel of the display device shown in FIG. 2.

Fig. 4 is a timing chart of the operation of the pixel shown in fig. 3.

Fig. 5 is a diagram of another example of a pixel of the display device shown in fig. 2.

Fig. 6 is a timing chart showing the operation of the pixel shown in fig. 5.

Fig. 7 and 8 are diagrams of another example of the pixel of the display device shown in fig. 2.

Detailed Description

While the invention is susceptible to various modifications and alternative embodiments, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. The effects, features, and modes for achieving the objects of the present invention will be more apparent with reference to the accompanying drawings and embodiments described later. However, the embodiments to be carried out under the present invention are not limited thereto, and may be implemented in various ways.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, to which the same or equivalent constituent elements are assigned the same reference numerals, and descriptions of overlapping contents are omitted.

In the following embodiments, the terms first, second, etc. are not limited to a certain meaning, but are used for the purpose of distinguishing a single constituent element from other constituent elements. In addition, in the following embodiments, expressions to the singular number will include a plurality of expressions unless the context clearly points to other meanings.

In the following embodiments, linking as described for X and Y may include: the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X, Y may be an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Therefore, the predetermined connection relation is not limited to the connection relation mentioned in the drawings or the detailed description, and may include a case other than the connection relation mentioned in the drawings or the detailed description, for example.

In the case where X and Y are electrically connected, it may include: for example, more than 1 element (for example, a switch, a transistor, a capacitor, an inductor, a resistance unit, a diode, or the like) for electrically connecting X and Y is connected between X and Y.

In the following embodiments, ˝ ON ˝ used in association with an element state refers to a state in which the element is activated, and ˝ OFF ˝ refers to a state in which the element is not activated. ˝ ON ˝, used in connection with signals received by the element, refers to signals that activate the element, and ˝ OFF ˝ refers to signals that deactivate the element. The element may be activated by a high voltage or a low voltage. For example, a P-channel transistor is activated by a low voltage and an N-channel transistor is activated by a high voltage. Thus, the voltage ˝ ON ˝ for a P-channel transistor and an N-channel transistor should be interpreted as opposite (low versus high) voltage levels.

In the following embodiments, terms including or including do not mean that a feature described in the specification or existence of a constituent element is present, and do not mean that possibility that one or more features or constituent elements can be added is excluded in advance.

As shown in fig. 1, a display device 30 according to an embodiment of the present invention may include: a light emitting element array 10 and a driving circuit substrate 20. The light emitting element array 10 may be combined with the driving circuit substrate 20. The display device 30 may be a micro LED display device.

The light emitting device array 10 may include a plurality of light emitting devices. The light emitting elements may be light emitting diodes, LEDs. The light emitting element may be a micro or nano unit size light emitting diode LED. A plurality of light emitting diodes may be grown on a semiconductor wafer to fabricate at least one light emitting device array 10. Therefore, the display device 30 can be manufactured by bonding the light emitting element array 10 and the driver circuit board 20 without transferring the light emitting diodes individually to the driver circuit board 20.

The pixel circuits each corresponding to the light emitting diode on the light emitting element array 10 may be arranged on the driving circuit substrate 20. The light emitting diodes on the light emitting element array 10 and the pixel circuits on the driving circuit substrate 20 may constitute pixels in an electrically connected manner.

As shown in fig. 2, a display device 30 according to an embodiment of the present invention may include: a pixel section 110 and a driving section.

The pixel part 110 may be disposed in the image display region. The pixel part 110 may include: for example, a plurality of pixels PX arranged in various forms such as a matrix shape, a zigzag shape, and the like. The pixel PX emits one color, for example, one color among red, cyan, green, and white. The pixel PX may emit other colors in addition to red, cyan, green, and white.

The pixel PX may include a light emitting element. The light emitting element may be a sub light emitting element. For example, the light emitting elements may be light emitting diodes, LEDs. The light-emitting element may emit light of a single peak wavelength or may emit light of a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting element. The pixel circuit may include at least one thin film transistor and at least one capacitor, etc. The pixel circuit may be implemented in a semiconductor stacked structure on a substrate.

In the pixel portion 110, it may include: the scan lines SL1-SLn that apply scan signals to the pixels PX, and the data lines DL1-DLm that apply data signals to the pixels PX. The scanning lines SL1 to SLn are each connected to pixels PX arranged in the same row, and the data lines DL1 to DLm are each connected to pixels PX arranged in the same column. The single scan line per row in fig. 2 is shown for convenience of explanation, and the scan lines SL1-SLn may be formed as a dual scan line by a first scan line to which a first scan signal is applied and a second scan line to which a second scan signal of a first scan signal inversion signal is applied. For example, the first row scan line SL1 may include: a first scan line SL11 to which a first scan signal is applied and a second scan line SL12 to which a second scan signal is applied.

The driving unit includes a non-display region around the pixel unit 110, and can drive and control the pixel unit 110. The driving part 120 may include: a control section 121, a scan driving section 122, a data driving section 123, and a power supply section 124.

Under the control of the control section 121, the scan driving section 122 may sequentially apply scan signals to the scan lines SL1-SLn, and the data driving section 123 may apply data signals to the respective pixels PX. The pixels PX at this time respond to the scan signals received through the scan lines SL1-SLn and emit light with a luminance corresponding to the voltage level or the current level of the data signals received through the data lines DL 1-DLm.

The power supply unit 124 receives an external power supply and/or an internal power supply, converts the operations of the various components into voltages of various levels, and supplies the corresponding voltages to the pixel unit 110 in accordance with a power control signal input from the control unit 121.

The power supply section 124 may generate and apply the first power voltage VDD to the pixel section 110. The power supply unit 124 may generate and apply a driving voltage to the scan driving unit 122 and the data driving unit 123.

The control unit 121, the scan driving unit 122, the data driving unit 123, and the power supply unit 124 may be formed as independent integrated circuit chips or as a single integrated circuit chip, and then directly mounted on the substrate on which the pixel unit 110 is formed, or may be attached to a flexible printed circuit (flexible printed circuit) or attached to a substrate in a tcp (tape carrier package) manner, or may be directly formed in the substrate.

FIG. 3 is an embodiment of a pixel of the display device shown in FIG. 2. Fig. 4 is a timing chart of the operation of the pixel shown in fig. 3.

For convenience of description, in the embodiment of fig. 3, the pixel PX1 in the nth row and the mth column will be described. The pixel PX1 is one of the majority pixels included in the nth row, and is connected to the scan line SLn corresponding to the nth row and the data line DLm corresponding to the mth column.

The pixels PX1 may be connected to a scan line SLn transmitting a scan signal, a data line DLm transmitting a data signal crossing the scan line SLn, and a power line transmitting a first power voltage VDD.

The pixel PX1 may include: a light emitting diode LED and a pixel circuit connected to the light emitting diode LED. The pixel circuit may include: an analog switch, a first transistor T1, and a capacitor C.

The analog switch may be implemented with a first transmission gate TG 1.

The input terminal of the first transmission gate TG1 is connected to the first node Q1, and the output terminal is connected to the second node Q2. The first transmission gate TG1 receives the DATA signal DATA from the DATA line connected to the first node Q1 and transmits the DATA signal DATA to the second node Q2. The gate terminal of the first transmission gate TG1 has one end connected to the first SCAN line and receives the first SCAN signal SCAN, and the other end connected to the second SCAN line and receives the second SCAN signal SCANB, which is an inversion signal of the first SCAN signal SCAN. The first transmission gate TG1 may include a P-channel transistor TP1 and an N-channel transistor TN1 connected in parallel to each other. The P-channel transistor TP1 and the N-channel transistor TN1 may be MOS transistors. Hereinafter, the P-channel transistor TP1 and the N-channel transistor TN1 will be referred to as a PMOS transistor TP1 and an NMOS transistor TN1, respectively, for explanation. The PMOS transistor TP1 and the NMOS transistor TN1 may be connected together with the first node Q1 and the second node Q2.

A PMOS transistor TP1 may have a first terminal connected to the first node Q1 and a second terminal connected to the second node Q1. The gate terminal of the PMOS transistor TP1 may receive the second scan signal SCANB after being connected to the second scan line. The PMOS transistor TP1 body, e.g., substrate, silicon, may be connected to a first power supply voltage VDD.

The NMOS transistor TN1 may have a first terminal connected to the first node Q1 and a second terminal connected to the second node Q1. The gate terminal of the NMOS transistor TN1 may receive the first SCAN signal SCAN after being connected to the first SCAN line. The NMOS transistor TN1 may have a bulk body, e.g., substrate, connected to the second power supply voltage VSS. The second power supply voltage VSS may be the ground power supply GND.

The first transistor T1 may include: a gate terminal to which the second node Q2 is connected, a first terminal to which the light emitting diode LED is connected, and a second terminal to which the second power supply voltage VSS is connected. The first transistor T1 functions as a driving transistor which supplies current to the light emitting diode LED upon receiving a data signal according to the switching action of the first transmission gate TG 1.

The capacitor C may include: a first electrode connected to the second node Q2, and a second electrode connected to a second power supply voltage VSS.

May include a first electrode connected to a first power voltage VDD of the light emitting diode LED and a second electrode connected to a first electrode of the first transistor T1. The light emitting diode LED displays an image with luminance corresponding to the data signal.

As shown in fig. 4, in a frame unit, during a SCAN period, the first SCAN signal SCAN is applied to the first SCAN line, the first transfer gate TG1 is turned on after the second SCAN signal SCANB is applied to the second SCAN line, and the DATA signal DATA applied through the input terminal of the first transfer gate TG1 is transmitted to the second node Q2 through the output terminal. The capacitor C connected to the second node Q2 holds a voltage corresponding to the DATA signal DATA. Then, during the light emitting period, the first transmission gate TG1 is turned off, and after the first transistor T1 is turned on, the light emitting diode LED emits light with a luminance corresponding to the data signal.

During the light emission, the voltage of the gate terminal of the first transistor T1, i.e., the voltage of the second node Q2, should be maintained at a certain level. However, a leakage current may occur in the first transmission gate TG1 in the off state. According to the leakage current occurring in the first transmission gate TG1, the voltage of the capacitor C is changed, and accordingly, the gate electrode voltage of the first transistor T1 is also changed, so that the luminance of the light emitting diode LED may be changed.

As shown in fig. 4, during the light emission period, the voltage VQ2 of the second node Q2 gradually decreases or increases before the start of the frame in the range of the voltage VH greater than the intermediate voltage VM and the voltage VL lower than the intermediate voltage VM although the intermediate voltage VM, which is the voltage of the DATA signal DATA, does not change. The voltage VQ2 of the second node Q2 can thereby be changed to a capacity equivalent to the first voltage change amount Δ V1 during one screen. The farther the voltage VQ2 of the second node Q2 is from the intermediate voltage VM, that is, the smaller or larger the voltage VQ2 of the second node Q2 is compared with the intermediate voltage VM, the larger the first voltage change amount Δ V1 becomes. These voltage variations may have an influence on the characteristics of the display device.

The voltage variation can be minimized in a manner of driving the display device at a high frequency, but this causes an increase in power consumption. To compensate for the leakage current of the first transmission gate TG1 being turned off, the capacitance of the capacitor C may be increased. The capacitor C is required to have an appropriate capacity to maintain its voltage level when determined according to the frequency of the screen. However, a small pixel size display device like a micro LED display device has a very limited capacity of a capacitor that can be arranged because its space is limited.

Fig. 5 is a diagram of another example of a pixel of the display device shown in fig. 2. Fig. 6 is a timing chart showing the operation of the pixel shown in fig. 5.

In the embodiment of fig. 5, the description will be made by taking the pixel PX2 in the nth row and the mth column as an example for convenience of description. The pixel PX2 is one of the majority pixels included in the nth row, and is connected to the scan line SLn corresponding to the nth row and the data line DLm corresponding to the mth column.

The pixels PX2 may be connected to a scan line SLn for transmitting a scan signal, a data line DLm for transmitting a data signal across the scan line SLn, and a power supply line for transmitting a first power supply voltage VDD.

The pixel PX2 may include: a light emitting diode LED and a pixel circuit connected to the light emitting diode LED. The pixel circuit may include: the driving circuit comprises two analog switches, a driving transistor and a capacitor connected with the analog switches and the driving transistor in series.

The first analog switch may be implemented with a first transmission gate TG 1. An input terminal of the first transmission gate TG1 may be connected with the third node Q3, and an output terminal may be connected with the fourth node Q4. The first transmission gate TG1 may communicate the DATA signal DATA received from a DATA line connected with the first node Q3 to the fourth node Q4. The gate terminal of the first transmission gate TG1 has one end connected to the first SCAN line and receives the first SCAN signal SCAN, and the other end connected to the second SCAN line and receives the second SCAN signal SCANB, which is an inversion signal of the first SCAN signal SCAN. The first transmission gate TG1 may include a P-channel transistor TP1 and an N-channel transistor TN1 connected in parallel to each other. The P-channel transistor TP1 and the N-channel transistor TN1 may be MOS transistors. Hereinafter, the P-channel transistor TP1 and the N-channel transistor TN1 will be referred to as a PMOS transistor TP1 and an NMOS transistor TN1, respectively, for explanation. The PMOS transistor TP1 and the NMOS transistor TN1 may be connected together with the third node Q3 and the fourth node Q4.

The PMOS transistor TP1 has a first terminal connected to the third node Q3 and a second terminal connected to the fourth node Q4. The gate terminal of the PMOS transistor TP1 may receive the second scan signal SCANB after being connected to the second scan line. The PMOS transistor TP1 body, e.g., substrate, silicon, may be connected to a first power supply voltage VDD.

The NMOS transistor TN1 has a first terminal connected to the third node Q3 and a second terminal connected to the fourth node Q4. The gate terminal of the NMOS transistor TN1 may receive the first SCAN signal SCAN after being connected to the first SCAN line. The NMOS transistor TN1 may have a bulk body, e.g., substrate, connected to the second power supply voltage VSS. The second power supply voltage VSS may be the ground power supply GND.

The second analog switch may be in series with the first analog switch. The second analog switch may be implemented with a second transmission gate TG 2. The input terminal of the second transmission gate TG2 is connected to the fourth node Q4, and the output terminal is connected to the fifth node Q5. The second transmission gate TG2 communicates to the fifth node Q5 upon receiving the DATA signal DATA communicated from the fourth node Q4 through the first transmission gate TG 1. The gate terminal of the second transmission gate TG2 has one end connected to the first SCAN line and receives the first SCAN signal SCAN, and the other end connected to the second SCAN line and receives the second SCAN signal SCANB, which is an inversion signal of the first SCAN signal SCAN. The second transmission gate TG2 may include a P-channel transistor TP2 and an N-channel transistor TN2 connected in parallel to each other. The P-channel transistor TP2 and the N-channel transistor TN2 may be MOS transistors. Hereinafter, the P-channel transistor TP2 and the N-channel transistor TN2 will be referred to as a PMOS transistor TP2 and an NMOS transistor TN2, respectively, and will be described. The PMOS transistor TP2 and the NMOS transistor TN2 may be connected together with the fourth node Q4 and the fifth node Q5.

The PMOS transistor TP2 has a first terminal connected to the fourth node Q4 and a second terminal connected to the fifth node Q5. The gate terminal of the PMOS transistor TP2 may receive the second scan signal SCANB after being connected to the second scan line. The bulk body of the PMOS transistor TP2, e.g., substrate, silicon, may be connected to the fifth node Q5, i.e., the second terminal of the PMOS transistor TP 2. The first terminal of the PMOS transistor TP2 may be a drain terminal and the second terminal may be a source terminal.

The NMOS transistor TN2 has a first terminal connected to the fourth node Q4 and a second terminal connected to the fifth node Q5. The gate terminal of the NMOS transistor TN2 may receive the first SCAN signal SCAN after being connected to the first SCAN line. The NMOS transistor TN2 is a fourth node Q4, i.e., the first terminal of the NMOS transistor TN2, for example, substrate, silicon. The first terminal of the NMOS transistor TN2 may be the source terminal and the second terminal may be the drain terminal.

The first transistor T1 may include: a gate terminal to which the fifth node Q5 is connected, a first terminal to which the light emitting diode LED is connected, and a second terminal to which the second power supply voltage VSS is connected. The first transistor T1 functions as a driving transistor for supplying current to the light emitting diode LED upon receiving a data signal according to the switching operation of the first transmission gate TG1 and the second transmission gate TG 2.

The first capacitor C1 may be electrically connected between the first transmission gate TG1 and the second transmission gate TG 2. The first capacitor C1 may include a first electrode connected to the fourth node Q4 and a second electrode connected to the second power supply voltage VSS. The first capacitor C1 may be a mosetal-oxide-semiconductor capacitor.

The second capacitor C2 may be electrically connected between the second transmission gate TG2 and the first transistor T1. The second capacitor C2 may include a first electrode connected to the fifth node Q5 and a second electrode connected to the second power supply voltage VSS. The second capacitor C2 may be a MIMmetal-insulator-metal capacitor.

The capacity of the second capacitor C2 may be larger than the capacity of the first capacitor C1. The sum of the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 may be the same or similar to the sum of the capacitances of the capacitors C in the embodiment shown in fig. 3.

As shown in fig. 6, during scanning, a first SCAN signal SCAN is applied to a first SCAN line and a second SCAN signal SCANB is applied to a second SCAN line in units of a picture, so that the first transmission gate TG1 and the second transmission gate TG2 are turned on. At this time, the DATA signal DATA applied through the input terminal of the first transmission gate TG1 is further transmitted to the fourth node Q4 through the output terminal, and the voltage of the fourth node Q4 applied through the input terminal of the second transmission gate TG2 is further transmitted to the fifth node Q5 through the output terminal. The first capacitor C1 connected to the fourth node Q4 and the second capacitor C2 connected to the fifth node Q5 each hold a voltage corresponding to the DATA signal DATA.

Then, during the light emitting period, the first transmission gate TG1 and the second transmission gate TG2 are turned off, and after the first transistor T1 is turned on, the light emitting diode LED emits light with a luminance corresponding to the data signal. During the light emission, a leakage current at the gate terminal of the first transistor T1, i.e., the fifth node Q5, will be determined according to a voltage difference of the fourth node Q4 and the fifth node Q5. The first capacitor C1 has a delay effect, and can reduce not only the voltage variation of the fourth node Q4 but also the voltage variation of the fifth node Q5.

As shown in fig. 6, during the light emission, the voltage VQ5 of the fifth node Q5 does not change in the middle voltage VM with respect to the voltage of the DATA signal DATA as in the embodiment of fig. 4. In addition, in one picture of the voltage VH greater than the intermediate voltage VM and the voltage VL lower than the intermediate voltage VM, the second voltage variation Δ V2 of the voltage VQ5 of the fifth node Q5 is decreasing compared to the first voltage variation Δ V1 reference point line of the embodiment of fig. 4.

In the embodiment of fig. 5, when the capacitor capacity is not increased as compared with the embodiment of fig. 3, the capacity of the capacitor is dispersed, and the second transfer gate is added to suppress the voltage variation of the two terminals of the second transfer gate, so that the voltage variation of the gate electrode of the first transistor T1 can be minimized.

The pixel PX3 in fig. 7 and the pixel PX4 in fig. 8 differ from the pixel PX2 in fig. 5 in that the second analog switch includes only one of the PMOS transistor TP2 and the NMOS transistor TN2 that constitute the second transfer gate TG2 of the pixel PX2 in fig. 5.

Each of the pixel PX3 of fig. 7 and the pixel PX4 of fig. 8 may include a light emitting diode LED and a pixel circuit connected to the light emitting diode LED. The pixel circuit may comprise two analog switches and a drive transistor in series, and an analog switch and a capacitor connected to the drive transistor.

The first analog switch may be implemented with a first transmission gate TG 1. The first transfer gate TG1, the first transistor T1 functioning as a driving transistor, the first and second capacitors C1, C2, the light emitting diode LED, and the like are the same as those of the pixel PX2 shown in fig. 5, and thus, the description thereof is omitted.

The second analog switch may be implemented with either the NMOS transistor TN2 FIG. 7 or the PMOS transistor TP2 FIG. 8.

In fig. 7, the NMOS transistor TN2 has a first terminal connected to the fourth node Q4 and a second terminal connected to the fifth node Q5. The gate terminal of the NMOS transistor TN2 may receive the first SCAN signal SCAN after being connected to the first SCAN line. The NMOS transistor TN2 is a fourth node Q4, i.e., the first terminal of the NMOS transistor TN2, for example, substrate, silicon. The first terminal of the NMOS transistor TN2 may be a source terminal and the second terminal may be a drain terminal.

The first transistor T1 functions as a driving transistor, and supplies a current to the light emitting diode LED in response to a data signal by switching operations of the first transmission gate TG1 and the second NMOS transistor TN 2. The first capacitor C1 is electrically connected between the first transmission gate TG1 and the NMOS transistor TN 2. The second capacitor C2 is electrically connected between the NMOS transistor TN2 and the first transistor T1.

The PMOS transistor TP2 in fig. 8 has a first terminal connected to the fourth node Q4 and a second terminal connected to the fifth node Q5. The gate terminal of the PMOS transistor TP2 may receive the second scan signal SCANB after being connected to the second scan line. The bulk body of the PMOS transistor TP2, e.g., substrate, silicon, may be connected to the fifth node Q5, i.e., the second terminal of the PMOS transistor TP 2. The first terminal of the PMOS transistor TP2 may be a drain terminal and the second terminal may be a source terminal.

The first transistor T1 functions as a driving transistor for supplying current to the light emitting diode LED upon receiving a data signal according to the switching operation of the first transmission gate TG1 and the second PMOS transistor TP 2. The first capacitor C1 may be electrically connected between the first transmission gate TG1 and the PMOS transistor TP 2. The second capacitor C2 may be electrically connected between the PMOS transistor TP2 and the first transistor T1.

Compared with the embodiment of fig. 3, the embodiment of fig. 7 and 8 disperses the capacity of the capacitor without increasing the capacity of the capacitor, adds the NMOS transistor or the PMOS transistor to suppress the voltage variation of both terminals of the NMOS transistor or the PMOS transistor, and can minimize the gate voltage variation of the first transistor T1. The embodiment of fig. 7 and 8 has a similar effect to the embodiment of fig. 5, in that the pixel size can be reduced compared to the embodiment of fig. 5.

In a small-sized area such as a micro LED display device, a drive circuit is required to be provided, and a capacitance value of a capacitor is particularly important in order to maintain a drive voltage for a screen time. In a state where the capacitor capacity is small, if a leakage current of the MOS switch occurs, an emergency voltage change occurs within one frame time, which may cause a quality problem of the display device. To prevent this, high frequency driving is used to shorten the frame time, but this causes a small current increase, so this method is not suitable for applications where power consumption is an important factor.

An embodiment of the present invention provides a pixel circuit including: an analog switch connected to a body bias connection source and a small-capacity capacitor, which can minimize a leakage current occurring from the analog switch to reduce an influence on a capacitor connected to a gate of a driving transistor.

Embodiments of the present invention can minimize a capacitor voltage variation provided by a small-area pixel circuit to minimize a gate voltage variation of a driving transistor. Thus, embodiments of the present invention may embody a pixel circuit of 1 ㎛ pitch, yet maintain power conservation and display device characteristics at low frame frequencies.

The present invention has been described with reference to one embodiment shown in the accompanying drawings, which are intended to be illustrative only, and it is to be understood that various other modifications and equivalent embodiments may be devised by those skilled in the art. Therefore, the true scope of the invention should be determined only by the claims.

Claims

1. A micro LED display device, comprising a plurality of pixels, wherein: a first switch including a first transistor and a second transistor connected in parallel with each other, and including an input terminal connected to the data line and an output terminal connected to the first node; an input terminal including at least one transistor and connected to the first node and an output terminal connected to a second node; a driving transistor having an output terminal connected to the gate terminal of the second switch and connected between the first power supply voltage and the second power supply voltage; a first capacitor connected between the first node and the second power supply voltage; and a second capacitor connected between the second node and the second power supply voltage.

2. The micro LED display device as claimed in claim 1, wherein the second switch comprises a third transistor and a fourth transistor connected in parallel, the third transistor is a P-channel transistor connected to its source terminal, and the fourth transistor is an N-channel transistor connected to its source terminal.

3. The micro LED display device of claim 1, wherein the second switch comprises a fifth transistor, and the fifth transistor is an N-channel transistor connected to its source terminal.

4. The micro LED display device of claim 1, wherein the second switch comprises a sixth transistor, and the sixth transistor is a P-channel transistor connected to its source terminal.

5. The micro LED display device of claim 1, wherein the first transistor is a P-channel transistor, the second transistor is an N-channel transistor, the first transistor body is connectable to the first power supply voltage, and the second transistor body is a micro LED display device connected to the second power supply voltage.

6. The micro LED display device of claim 1, wherein the second capacitor has a larger capacity than the first capacitor.

7. The micro LED display device of claim 1, wherein the first capacitor is a MOS capacitor and the second capacitor is a micro LED display device of a MIM capacitor.