CN102945659A - Pixel circuit for silicon-based liquid crystal micro-displays - Google Patents

Abstract

The invention discloses a pixel point circuit of a silicon-based liquid crystal microdisplay. The display adopts a frame refresh mode, and there is a row selection main switch between each row of pixel points and a digital-to-analog converter DAC bus. The pixel point circuit is composed of 5 transmission gates and two storage capacitors, namely the first transmission gate (TG1), the second transmission gate (TG2), the third transmission gate (TG3), the fourth transmission gate (TG4), the fifth The transmission gate (TG5), the first storage capacitor CA, and the second storage capacitor CB; each transmission gate is composed of a pair of field effect transistors. The first storage capacitor CA is connected between the first transmission gate (TG1) and the second transmission gate (TG2), and the second storage capacitor CB is connected between the third transmission gate (TG3) and the fourth transmission gate (TG4), The other end of the first storage capacitor CA and the second storage capacitor CB are grounded; the output terminals of the fifth transmission gate are respectively connected to the first transmission gate (TG1) and the third transmission gate; the output terminals of the second and fourth transmission gates are connected to the liquid crystal load.

Description

A silicon-based liquid crystal microdisplay pixel point circuit

technical field

The invention relates to the technical field of Liquid Crystal on Silicon (LCoS, Liquid Crystal on Silicon), in particular to the field of pixel circuits of liquid crystal on silicon microdisplays.

Background technique

Liquid crystal-on-silicon microdisplay devices are made by filling liquid crystals between a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) silicon-based backplane with a driving circuit and an ITO (indium tin oxide) glass panel. A new type of micro-display device, which comprehensively applies CMOS integrated circuit technology and liquid crystal display technology, has many advantages such as high resolution, miniaturization and low cost, and is a micro-display device with great development potential.

The liquid crystal on silicon COMS drive backplane is a key component of the liquid crystal on silicon micro-display device, which is mainly composed of two parts: a pixel array and a peripheral driving circuit. The function of the LCoS drive circuit is to convert the video signal in digital format into an analog signal for driving the screen, and finally display it as an image recognizable by human eyes.

Each pixel circuit in LCoS technology is composed of a switch tube and a MOS capacitor. In the conventional process, the MOS capacitor accounts for half of the entire pixel area. With the increase of resolution and the decrease of circuit area, the capacitor area shrinks. As a result, the MOS capacitance becomes smaller and the image display quality deteriorates.

With the improvement of the resolution of micro-display devices, the parasitic capacitance brought about by the transistors in the pixel unit and the transmission lines connecting the pixels has an increasing influence on the circuit. Figure 1 is a traditional pixel circuit structure. With this structure, the equivalent capacitance of the DAC transmission line of the digital-to-analog converter in the array and the parasitic capacitance of the transmission gate of the pixel input terminal on all other rows and columns in the off state will become the DAC load capacitance of the digital-to-analog converter. The driving ability of the DAC is very demanding, and the uneven distribution of parasitic capacitance seriously affects the imaging quality of the display. The pixel point circuit design scheme proposed by the present invention can effectively solve the above-mentioned problems.

Contents of the invention

Technical problem: Aiming at the existing problem that the parasitic capacitance becomes bigger and bigger with the improvement of the resolution, the present invention proposes a silicon-based liquid crystal microdisplay pixel circuit, which can effectively reduce the parasitic capacitance.

Aiming at the problem that the size of the storage capacitor is limited by the pixel area, the present invention proposes a method for increasing the storage capacitor within a limited area.

Technical solution: In order to achieve the above purpose, in the pixel point circuit of the silicon-based liquid crystal microdisplay of the present invention, the pixel point circuit is composed of five transmission gates and two storage capacitors, that is, the first transmission gate, the second transmission gate, and the third transmission gate gate, the fourth transmission gate, the fifth transmission gate, the first storage capacitor C _A , and the second storage capacitor C _B ; each transmission gate is composed of a pair of field effect transistors, the first PMOS field effect transistor and the second NMOS field effect transistor The effect transistor constitutes the first transmission gate, the third PMOS field effect transistor and the fourth NMOS field effect transistor constitute the second transmission gate, the fifth PMOS field effect transistor and the sixth NMOS field effect transistor constitute the third transmission gate, and the seventh PMOS field effect transistor constitutes the third transmission gate. The effect transistor and the eighth NMOS field effect transistor constitute the fourth transmission gate, the ninth PMOS field effect transistor and the tenth NMOS field effect transistor constitute the fifth transmission gate; the first storage capacitor CA is connected to the first transmission gate and the second transmission gate Between, the second storage capacitor C _B is connected between the third transmission gate and the fourth transmission gate, the other end of the first storage capacitor C _A and the second storage capacitor C _B is grounded; the input terminal of the fifth transmission gate is the pixel The input end of the dot circuit is connected to the digital-to-analog converter DAC, and the output end of the fifth transmission gate is connected to the input ends of the first transmission gate and the third transmission gate respectively; the output end of the first transmission gate is connected to the second transmission gate The input terminal, the output terminal of the third transmission gate is connected to the input terminal of the fourth transmission gate, the output terminal of the second transmission gate is connected to the output terminal of the fourth transmission gate as the output terminal of the pixel point circuit is connected to the liquid crystal load.

The fifth transmission gate is controlled by the row selection signal. When the digital-to-analog converter DAC charges the pixel point circuit row by row, the row selection switch corresponding to the unselected row remains off, and the pixel point circuits in the same column are phased by the fifth transmission gate. Isolation reduces the parasitic capacitance caused by other pixels in the same column.

There is a row selection master switch between each row of pixels and the DAC bus of the digital-to-analog converter. The row-selection master switch is controlled by the row-selection signal to ensure that, except for the currently written row, the transmission lines of other rows in the array are connected to the digital-to-analog converter. The DAC bus is disconnected to reduce the parasitic capacitance introduced by the DAC transmission line of the digital-to-analog converter in the pixel array.

The first storage capacitor C _A and the second storage capacitor C _B adopt a storage capacitor structure in which two capacitors of a metal oxide semiconductor MOS capacitor and a polysilicon-insulating layer-polysilicon PIP capacitor are connected in parallel. Within the limited pixel area, the capacitance is increased, and the circuit stability and linearity are improved.

The pixel point circuit adopts the frame refresh mode, the first transmission gate and the third transmission gate control charging one of the first storage capacitor _CA and the second storage capacitor C _B , while the second transmission gate and the fourth transmission gate control Another storage capacitor discharges the liquid crystal load.

Beneficial effects: the pixel point circuit structure proposed by the present invention, although the equivalent capacitance of the transmission gate in the off state connected to the DAC transmission line of the digital-to-analog converter outside the array and the parasitic capacitance of the transmission gate in the on state in the pixel are increased, However, the equivalent capacitance of the digital-to-analog converter DAC transmission line in the array and the parasitic capacitance of the transmission gate of the pixel input terminal in the off state are reduced, and the maximum load capacitance of the digital-to-analog converter DAC is reduced by more than 95%, which greatly improves the performance of the display device. image quality.

The present invention adopts a storage capacitor structure in which two capacitors of a MOS capacitor and a PIP capacitor are connected in parallel, without increasing the capacitor area, the storage capacitor is increased by about 20%, and the display quality is improved.

Description of drawings

FIG. 1 is a structure diagram of a conventional pixel circuit.

Fig. 2 is a diagram of pixel connections in the LCoS array proposed by the present invention.

FIG. 3 is a structural diagram of a pixel point circuit proposed by the present invention.

Detailed ways

The pixel point circuit proposed by the present invention is shown in Figure 3. The pixel point circuit is composed of five transmission gates and two storage capacitors, that is, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate The transmission gate TG4, the fifth transmission gate TG5, the first storage capacitor _CA , and the second storage capacitor C _B ; each transmission gate is composed of a pair of field effect transistors, the first PMOS field effect transistor 1 and the second NMOS field effect transistor The tube 2 constitutes the first transmission gate TG1, the third PMOS field effect transistor 3 and the fourth NMOS field effect transistor 4 constitute the second transmission gate TG2, the fifth PMOS field effect transistor 5 and the sixth NMOS field effect transistor 6 constitute the third transmission gate Gate TG3, the seventh PMOS field effect transistor 7 and the eighth NMOS field effect transistor 8 constitute the fourth transmission gate TG4, the ninth PMOS field effect transistor 9 and the tenth NMOS field effect transistor 10 constitute the fifth transmission gate TG5; The capacitor C _A is connected between the first transmission gate TG1 and the second transmission gate TG2, the second storage capacitor C _B is connected between the third transmission gate TG3 and the fourth transmission gate TG4, the first storage capacitor C _A and the second The other end of the storage capacitor C _B is grounded; the input end of the fifth transmission gate TG5 is the input end of the pixel point circuit, connected to the digital-to-analog converter DAC, and the output end of the fifth transmission gate TG5 is respectively connected to the first transmission gate TG1 and the third transmission gate TG1. The input terminals of the transmission gate TG3 are connected; the output terminal of the first transmission gate TG1 is connected to the input terminal of the second transmission gate TG2, the output terminal of the third transmission gate TG3 is connected to the input terminal of the fourth transmission gate TG4, and the second transmission gate TG2 It is connected with the output terminal of the fourth transmission gate TG4 as the output terminal of the pixel point circuit to be connected to the liquid crystal load.

The fifth transmission gate TG5 is controlled by the row selection signal, and when the output voltage of the digital-to-analog converter DAC is charging the pixel circuit row by row, the row selection switch corresponding to the unselected row remains in the off state. Due to the existence of the fifth transmission gate TG5 , the pixel circuits in the same column are also in the disconnected state, which reduces the parasitic capacitance caused by other pixel circuits in the same column.

As shown in Figure 2, there is a row selection master switch between each row of pixels and the DAC bus of the digital-to-analog converter. The row selection master switch is controlled by the row selection signal. The row selection master switch can ensure that except for the currently written row, The transmission lines of other rows in the array are disconnected from the digital-to-analog converter DAC bus, so the parasitic capacitance introduced by the digital-to-analog converter DAC transmission lines in the pixel array can be greatly reduced.

Although the equivalent capacitance of the off-state transmission gate connected to the digital-to-analog converter DAC transmission line outside the array and the parasitic capacitance of the transmission gate in the on-state pixel are increased, the digital-to-analog converter DAC transmission line in the array is reduced, etc. Effective capacitance and the parasitic capacitance of the transmission gate of the pixel input terminal in the off state, the maximum load capacitance of the digital-to-analog converter DAC is reduced by more than 95%.

The PIP capacitor is composed of two polysilicon (poly) layers, separated by silicon dioxide in the middle, and the upper and lower plates are separated from the substrate and other devices by the field oxide layer. As long as the thickness of the growth oxide medium can be precisely controlled, it can be obtained Accurate capacitance value, unit capacitance value is slightly smaller than MOS capacitance. PIP capacitors have the advantages of stable performance, good linearity, and small parasitic capacitance.

Since the pixel circuit proposed by the present invention adopts CMOS technology, and the circuit already includes multiple poly layers, two polysilicon layers can be used to form a capacitor. The specific steps are first depositing the first polysilicon film on the gate oxide layer of the MOS transistor; then growing a dielectric layer film on the first polysilicon film; and then depositing a second film on the dielectric layer film. polysilicon film. Then connect the MOS capacitor and the PIP capacitor in parallel through wiring.

The present invention adopts a parallel structure of double capacitors, the first storage capacitor C _A and the second storage capacitor C _B are composed of MOS capacitors and PIP capacitors connected in parallel. Using this structure can increase the size of the MOS capacitor by about 20% under the condition of the same area.

Claims (5)

1. silicon based LCD micro-display pixel circuit, it is characterized in that the pixel circuit is comprised of 5 transmission gates and two memory capacitance, i.e. the first transmission gate (TG1), the second transmission gate (TG2), the 3rd transmission gate (TG3), the 4th transmission gate (TG4), the 5th transmission gate (TG5), the first memory capacitance C _A, the second memory capacitance C _BEach transmission gate consists of by a pair of field effect transistor, the one PMOS field effect transistor (1) and the 2nd NMOS field effect transistor (2) consist of the first transmission gate (TG1), the 3rd PMOS field effect transistor (3) and the 4th NMOS field effect transistor (4) consist of the second transmission gate (TG2), the 5th PMOS field effect transistor (5) and the 6th NMOS field effect transistor (6) consist of the 3rd transmission gate (TG3), the 7th PMOS field effect transistor (7) and the 8th NMOS field effect transistor (8) consist of the 4th transmission gate (TG4), and the 9th PMOS field effect transistor (9) and the tenth NMOS field effect transistor (10) consist of the 5th transmission gate (TG5); The first memory capacitance C _ABe connected between the first transmission gate (TG1) and the second transmission gate (TG2) the second memory capacitance C _BBe connected between the 3rd transmission gate (TG3) and the 4th transmission gate (TG4) the first memory capacitance C _AWith the second memory capacitance C _BOther end ground connection; The input end of the 5th transmission gate (TG5) is the input end of this pixel circuit, meets digital analog converter DAC, and the output terminal of the 5th transmission gate (TG5) links to each other with the input end of the first transmission gate (TG1) with the 3rd transmission gate (TG3) respectively; The input end of output termination second transmission gate (TG2) of the first transmission gate (TG1), the input end of output termination the 4th transmission gate (TG4) of the 3rd transmission gate (TG3), the output terminal of the second transmission gate (TG2) and the 4th transmission gate (TG4) links to each other as the output termination liquid crystal load of this pixel circuit.

2. silicon based LCD micro-display pixel circuit according to claim 1, it is characterized in that the 5th transmission gate (TG5) selects signal controlling by row, when digital analog converter DAC charges to the pixel circuit line by line, row corresponding to selected line do not select switch to keep off state, isolated by the 5th transmission gate (TG5) between the same row pixel circuit, reduced the stray capacitance that other pixels of same row cause.

3. silicon based LCD micro-display pixel circuit according to claim 1, it is characterized in that having a row to select master switch between every delegation pixel and the digital analog converter DAC bus, row selects master switch to select signal controlling by row, guarantee except when outside the front row that writes, the transmission line of other row and digital analog converter DAC bus disconnect in the array, reduce the stray capacitance that digital analog converter DAC transmission line is introduced in the pel array.

4. silicon based LCD micro-display pixel circuit according to claim 1 is characterized in that described the first memory capacitance C _A, the second memory capacitance C _BAll adopt the storage capacitor construction of metal-oxide semiconductor (MOS) mos capacitance and two Capacitance parallel connections of polysilicon-insulating layer-polysilicon PIP electric capacity.

5. silicon based LCD micro-display pixel circuit according to claim 1 is characterized in that described pixel circuit adopts the frame refresh mode, and the first transmission gate (TG1), the 3rd transmission gate (TG3) are controlled the first memory capacitance C _A, the second memory capacitance C _BIn a charging, simultaneously the second transmission gate (TG2) and the 4th transmission gate (TG4) are controlled another memory capacitance to the liquid crystal load discharge.

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