CN102945659A - Pixel circuit for silicon-based liquid crystal micro-displays - Google Patents
Pixel circuit for silicon-based liquid crystal micro-displays Download PDFInfo
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- CN102945659A CN102945659A CN2012105173135A CN201210517313A CN102945659A CN 102945659 A CN102945659 A CN 102945659A CN 2012105173135 A CN2012105173135 A CN 2012105173135A CN 201210517313 A CN201210517313 A CN 201210517313A CN 102945659 A CN102945659 A CN 102945659A
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Abstract
The invention discloses a pixel circuit for silicon-based liquid crystal micro-displays. A display adopts a frame refresh mode, and a row-selection main switch is arranged between each row of pixels and a DAC (digital-to-analog converter) bus. The pixel circuit is composed of five transmission gates and two storage capacitors, namely, a first transmission gate (TG1), a second transmission gate (TG2), a third transmission gate (TG3), a fourth transmission gate (TG4), a fifth transmission gate (TG5), a first storage capacitor CA and a second storage capacitor CB; and each transmission gate is composed of a pair of field-effect tubes. The first storage capacitor CA is connected between the first transmission gate (TG1) and the second transmission gate (TG2), the second storage capacitor CB is connected between the third transmission gate (TG3) and the fourth transmission gate (TG4), and the other ends of the first storage capacitor CA and the second storage capacitor CB are earthed; the output end of the fifth transmission gate is respectively connected with the first transmission gate (TG1) and the third transmission gate; and the output ends of the second and fourth transmission gates are connected with a liquid crystal load.
Description
Technical field
The present invention relates to silicon-base liquid crystal display device (LCoS, Liquid Crystal on Silicon) technical field, specifically belong to silicon based LCD micro-display pixel circuit field.
Background technology
The liquid crystal on silicon micro display device is a kind ofly to be prepared with the CMOS(ComplementaryMetal-Oxide-Semiconductor Transistor complementary metal oxide semiconductor (CMOS) of driving circuit) silica-based backboard and ITO(indium tin oxide) the can liquid crystal forms between the face glass novel micro-display device, its integrated application CMOS integrated circuit technique and lcd technology, having high resolving power, microminiaturization and the many advantages such as low-cost, is a kind of micro-display device that has development potentiality.
It is the key components of liquid crystal on silicon micro display device that liquid crystal on silicon COMS drives backboard, mainly is comprised of pel array and peripheral drive circuit two parts.The effect of LCoS driving circuit is the simulating signal that the vision signal of digital format is converted into into the driving screen, finally is shown as the cognizable image of human eye.
Each pixel circuit in the LCoS technology is comprised of a switching tube and a mos capacitance, and in common process, mos capacitance accounts for half of whole elemental area, along with the increase of resolution and reducing of circuit area, capacity area is dwindled, and causes mos capacitance to diminish, and image displaying quality descends.
Along with the lifting of micro display device resolution, the stray capacitance that the transmission line of the transistor in the pixel cell and connection pixel brings is increasing on the impact of circuit.Traditional pixel circuit structure such as Fig. 1.Adopt this structure, digital analog converter DAC transmission line equivalent capacity and the stray capacitance that is in the pixel input end transmission gate on other all ranks of off state all can become digital analog converter DAC load capacitance in the array, driving force requirement to digital analog converter DAC is very high, and the stray capacitance skewness has a strong impact on the display image quality.The pixel circuit design scheme that the present invention proposes can effectively solve above-mentioned problem.
Summary of the invention
Technical matters: for existing raising along with resolution, the problem that stray capacitance is increasing the present invention proposes a kind of silicon based LCD micro-display pixel circuit, can effectively reduce stray capacitance.
Be subjected to the problem of elemental area restriction for the size of memory capacitance, the present invention proposes a kind of method that in limited area, increases memory capacitance.
Technical scheme: for achieving the above object, in the silicon based LCD micro-display pixel circuit of the present invention, the pixel circuit is comprised of 5 transmission gates and two memory capacitance, i.e. the first transmission gate, the second transmission gate, the 3rd transmission gate, the 4th transmission gate, the 5th transmission gate, the first memory capacitance C
A, the second memory capacitance C
BEach transmission gate consists of by a pair of field effect transistor, the one PMOS field effect transistor and the 2nd NMOS field effect transistor consist of the first transmission gate, the 3rd PMOS field effect transistor and the 4th NMOS field effect transistor consist of the second transmission gate, the 5th PMOS field effect transistor and the 6th NMOS field effect transistor consist of the 3rd transmission gate, the 7th PMOS field effect transistor and the 8th NMOS field effect transistor consist of the 4th transmission gate, and the 9th PMOS field effect transistor and the tenth NMOS field effect transistor consist of the 5th transmission gate; The first memory capacitance CA is connected between the first transmission gate and the second transmission gate, the second memory capacitance C
BBe connected between the 3rd transmission gate and the 4th transmission gate the first memory capacitance C
AWith the second memory capacitance C
BOther end ground connection; The input end of the 5th transmission gate is the input end of this pixel circuit, meets digital analog converter DAC, and the output terminal of the 5th transmission gate links to each other with the input end of the first transmission gate with the 3rd transmission gate respectively; The first transmission gate the input end of output termination the second transmission gate, the 3rd transmission gate the input end of output termination the 4th transmission gate, the output terminal of the second transmission gate and the 4th transmission gate links to each other as the output termination liquid crystal load of this pixel circuit.
The 5th transmission gate selects signal controlling by row, when digital analog converter DAC charges to the pixel circuit line by line, row corresponding to selected line do not select switch to keep off state, and be isolated by the 5th transmission gate between the same row pixel circuit, reduced the stray capacitance that other pixels of same row cause.
There is a row to select master switch between every delegation pixel and the digital analog converter DAC bus, row selects master switch to select signal controlling by row, guarantee except when outside the front row that writes, the transmission line of other row and digital analog converter DAC bus disconnect in the array, reduce the stray capacitance that digital analog converter DAC transmission line is introduced in the pel array.
Described the first memory capacitance C
A, the second memory capacitance C
BAdopt the storage capacitor construction of metal-oxide semiconductor (MOS) mos capacitance and two Capacitance parallel connections of polysilicon-insulating layer-polysilicon PIP electric capacity.In limited pixel point areas, increased electric capacity, improved circuit stability and the linearity.
Described pixel circuit adopts the frame refresh mode, and the first transmission gate, the 3rd transmission gate are controlled the first memory capacitance C
A, the second memory capacitance C
BIn a charging, simultaneously the second transmission gate and the 4th transmission gate are controlled another memory capacitance to the liquid crystal load discharge.
Beneficial effect: the pixel circuit structure that the present invention proposes, although increased transmission gate stray capacitance in the transmission gate equivalent capacity that is in off state that is connected with the outer digital analog converter DAC transmission line of array and the pixel that is in conducting state, but the stray capacitance that has reduced the interior digital analog converter DAC transmission line equivalent capacity of array and be in the pixel input end transmission gate of off state, the maximum load electric capacity minimizing of digital analog converter DAC reaches more than 95%, has greatly improved the image quality of display device.
The present invention is by having adopted the storage capacitor construction of mos capacitance and two Capacitance parallel connections of PIP electric capacity, in the situation that do not increase capacity area, memory capacitance has increased about 20%, has improved display quality.
Description of drawings
Fig. 1 is a kind of traditional pixel circuit structure diagram.
Fig. 2 is pixel annexation figure in the LCoS array that proposes of the present invention.
Fig. 3 is the pixel circuit structure diagram that the present invention proposes.
Embodiment
The pixel circuit that the present invention proposes as shown in Figure 3, this pixel circuit is comprised of 5 transmission gates and two memory capacitance, i.e. the first transmission gate TG1, the second transmission gate TG2, the 3rd transmission gate TG3, the 4th transmission gate TG4, the 5th transmission gate TG5, the first memory capacitance C
A, the second memory capacitance C
BEach transmission gate consists of by a pair of field effect transistor, the one PMOS field effect transistor 1 and the 2nd NMOS field effect transistor 2 consist of the first transmission gate TG1, the 3rd PMOS field effect transistor 3 and the 4th NMOS field effect transistor 4 consist of the second transmission gate TG2, the 5th PMOS field effect transistor 5 and the 6th NMOS field effect transistor 6 consist of the 3rd transmission gate TG3, the 7th PMOS field effect transistor 7 and the 8th NMOS field effect transistor 8 consist of the 4th transmission gate TG4, and the 9th PMOS field effect transistor 9 and the tenth NMOS field effect transistor 10 consist of the 5th transmission gate TG5; The first memory capacitance C
ABe connected between the first transmission gate TG1 and the second transmission gate TG2 the second memory capacitance C
BBe connected between the 3rd transmission gate TG3 and the 4th transmission gate TG4 the first memory capacitance C
AWith the second memory capacitance C
BOther end ground connection; The input end of the 5th transmission gate TG5 is the input end of this pixel circuit, meets digital analog converter DAC, and the output terminal of the 5th transmission gate TG5 links to each other with the input end of the first transmission gate TG1 and the 3rd transmission gate TG3 respectively; The first transmission gate TG1 the input end of output termination the second transmission gate TG2, the input end of output termination the 4th transmission gate TG4 of the 3rd transmission gate TG3, the output terminal of the second transmission gate TG2 and the 4th transmission gate TG4 link to each other as the output termination liquid crystal load of this pixel circuit.
The 5th transmission gate TG5 selects signal controlling by row, and when digital analog converter DAC output voltage charged to the pixel circuit line by line, row corresponding to selected line do not select switch to keep off state.Because the existence of the 5th transmission gate TG5 also is in off-state, reduced the stray capacitance that other pixel circuit of same row cause between the same row pixel circuit.
As shown in Figure 2, there is a row to select master switch between every delegation pixel and the digital analog converter DAC bus, row selects master switch to select signal controlling by row, row selects master switch to guarantee except when outside the front row that writes, the transmission line of other row and digital analog converter DAC bus disconnect in the array, therefore can greatly reduce the stray capacitance that digital analog converter DAC transmission line is introduced in the pel array.
Although increased transmission gate stray capacitance in the transmission gate equivalent capacity that is in off state that is connected with the outer digital analog converter DAC transmission line of array and the pixel that is in conducting state, but the stray capacitance that has reduced the interior digital analog converter DAC transmission line equivalent capacity of array and be in the pixel input end transmission gate of off state, the maximum load electric capacity minimizing of digital analog converter DAC reaches more than 95%.
PIP electric capacity is made of two-layer polysilicon (poly) layer, the centre separates with silicon dioxide, and upper bottom crown separates by field oxide and substrate and other devices, as long as can accurately control the thickness of growth oxide layer medium, just can obtain accurate capacitance, the specific capacitance value is more smaller than mos capacitance.PIP electric capacity has the advantages such as stable performance, the linearity is good, stray capacitance is little.
Because the pixel circuit that the present invention proposes adopts CMOS technique, has comprised multilayer poly layer in the circuit, so can consist of capacitor with the two-layer polysilicon layer.Concrete steps are first after on the grid oxic horizon of metal-oxide-semiconductor, deposit the first polysilicon membrane; Again on the first polysilicon membrane, growth dielectric layer film; Then at dielectric layer film deposition the second polysilicon membrane.Again by connecting up mos capacitance and PIP Capacitance parallel connection.
The present invention has adopted the structure of two Capacitance parallel connections, the first memory capacitance C
A, the second memory capacitance C
BConsisted of by mos capacitance and PIP Parallel-connected Capacitor.Adopt this structure can be under condition of the same area, can increase size about 20% than mos capacitance.
Claims (5)
1. silicon based LCD micro-display pixel circuit, it is characterized in that the pixel circuit is comprised of 5 transmission gates and two memory capacitance, i.e. the first transmission gate (TG1), the second transmission gate (TG2), the 3rd transmission gate (TG3), the 4th transmission gate (TG4), the 5th transmission gate (TG5), the first memory capacitance C
A, the second memory capacitance C
BEach transmission gate consists of by a pair of field effect transistor, the one PMOS field effect transistor (1) and the 2nd NMOS field effect transistor (2) consist of the first transmission gate (TG1), the 3rd PMOS field effect transistor (3) and the 4th NMOS field effect transistor (4) consist of the second transmission gate (TG2), the 5th PMOS field effect transistor (5) and the 6th NMOS field effect transistor (6) consist of the 3rd transmission gate (TG3), the 7th PMOS field effect transistor (7) and the 8th NMOS field effect transistor (8) consist of the 4th transmission gate (TG4), and the 9th PMOS field effect transistor (9) and the tenth NMOS field effect transistor (10) consist of the 5th transmission gate (TG5); The first memory capacitance C
ABe connected between the first transmission gate (TG1) and the second transmission gate (TG2) the second memory capacitance C
BBe connected between the 3rd transmission gate (TG3) and the 4th transmission gate (TG4) the first memory capacitance C
AWith the second memory capacitance C
BOther end ground connection; The input end of the 5th transmission gate (TG5) is the input end of this pixel circuit, meets digital analog converter DAC, and the output terminal of the 5th transmission gate (TG5) links to each other with the input end of the first transmission gate (TG1) with the 3rd transmission gate (TG3) respectively; The input end of output termination second transmission gate (TG2) of the first transmission gate (TG1), the input end of output termination the 4th transmission gate (TG4) of the 3rd transmission gate (TG3), the output terminal of the second transmission gate (TG2) and the 4th transmission gate (TG4) links to each other as the output termination liquid crystal load of this pixel circuit.
2. silicon based LCD micro-display pixel circuit according to claim 1, it is characterized in that the 5th transmission gate (TG5) selects signal controlling by row, when digital analog converter DAC charges to the pixel circuit line by line, row corresponding to selected line do not select switch to keep off state, isolated by the 5th transmission gate (TG5) between the same row pixel circuit, reduced the stray capacitance that other pixels of same row cause.
3. silicon based LCD micro-display pixel circuit according to claim 1, it is characterized in that having a row to select master switch between every delegation pixel and the digital analog converter DAC bus, row selects master switch to select signal controlling by row, guarantee except when outside the front row that writes, the transmission line of other row and digital analog converter DAC bus disconnect in the array, reduce the stray capacitance that digital analog converter DAC transmission line is introduced in the pel array.
4. silicon based LCD micro-display pixel circuit according to claim 1 is characterized in that described the first memory capacitance C
A, the second memory capacitance C
BAll adopt the storage capacitor construction of metal-oxide semiconductor (MOS) mos capacitance and two Capacitance parallel connections of polysilicon-insulating layer-polysilicon PIP electric capacity.
5. silicon based LCD micro-display pixel circuit according to claim 1 is characterized in that described pixel circuit adopts the frame refresh mode, and the first transmission gate (TG1), the 3rd transmission gate (TG3) are controlled the first memory capacitance C
A, the second memory capacitance C
BIn a charging, simultaneously the second transmission gate (TG2) and the 4th transmission gate (TG4) are controlled another memory capacitance to the liquid crystal load discharge.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012105173135A CN102945659A (en) | 2012-12-05 | 2012-12-05 | Pixel circuit for silicon-based liquid crystal micro-displays |
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| CN2012105173135A CN102945659A (en) | 2012-12-05 | 2012-12-05 | Pixel circuit for silicon-based liquid crystal micro-displays |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935294A (en) * | 2014-03-20 | 2015-09-23 | 晶宏半导体股份有限公司 | Oscillator |
| CN106448552A (en) * | 2016-11-29 | 2017-02-22 | 京东方科技集团股份有限公司 | Display substrate, display device and display control method |
| CN106448553A (en) * | 2016-11-29 | 2017-02-22 | 京东方科技集团股份有限公司 | Display substrate, display device and displaying control method |
| CN111063297A (en) * | 2020-02-22 | 2020-04-24 | 禹创半导体(广州)有限公司 | Miniature micro LED display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101164334A (en) * | 2005-04-07 | 2008-04-16 | 国立大学法人东北大学 | Optical sensor, solid-state imaging device, and operation method of solid-state imaging device |
| US20120169692A1 (en) * | 2010-12-31 | 2012-07-05 | Opris Ion E | Micro Electromechanical System (MEMS) Spatial Light Modulator Pixel Driver Circuits |
-
2012
- 2012-12-05 CN CN2012105173135A patent/CN102945659A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101164334A (en) * | 2005-04-07 | 2008-04-16 | 国立大学法人东北大学 | Optical sensor, solid-state imaging device, and operation method of solid-state imaging device |
| US20120169692A1 (en) * | 2010-12-31 | 2012-07-05 | Opris Ion E | Micro Electromechanical System (MEMS) Spatial Light Modulator Pixel Driver Circuits |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935294A (en) * | 2014-03-20 | 2015-09-23 | 晶宏半导体股份有限公司 | Oscillator |
| CN106448552A (en) * | 2016-11-29 | 2017-02-22 | 京东方科技集团股份有限公司 | Display substrate, display device and display control method |
| CN106448553A (en) * | 2016-11-29 | 2017-02-22 | 京东方科技集团股份有限公司 | Display substrate, display device and displaying control method |
| CN106448553B (en) * | 2016-11-29 | 2018-10-23 | 京东方科技集团股份有限公司 | Display base plate, display device and display control method |
| CN106448552B (en) * | 2016-11-29 | 2018-11-23 | 京东方科技集团股份有限公司 | Display base plate, display device and display control method |
| CN111063297A (en) * | 2020-02-22 | 2020-04-24 | 禹创半导体(广州)有限公司 | Miniature micro LED display device |
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Application publication date: 20130227 |