TWI719815B - Driving circuit for pixel - Google Patents
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本案涉及一種像素驅動電路，尤其是涉及一種運用脈衝調幅以及脈衝調寬雙模機制的像素驅動電路。 This case relates to a pixel drive circuit, in particular to a pixel drive circuit using dual-mode pulse amplitude modulation and pulse width modulation mechanisms.
現有技術中，LED的驅動方式通常是以類似OLED的驅動方式來進行，即所謂的脈衝調幅(PAM)機制，然而，將脈衝調幅機制運用於無論是mini-LED或是micro-LED時，皆存在色偏問題。 In the prior art, the driving method of LED is usually carried out in a driving method similar to OLED, which is the so-called pulse amplitude modulation (PAM) mechanism. However, when the pulse amplitude modulation mechanism is applied to both mini-LEDs and micro-LEDs, both There is a color cast problem.
此外，在脈衝調幅(PAM)搭配脈衝調寬(PWM)雙模電路中，因電晶體閾值電壓的補償問題，控制訊號繁多，使得電路架構複雜化。 In addition, in the dual-mode circuit of pulse amplitude modulation (PAM) and pulse width modulation (PWM), due to the problem of the compensation of the threshold voltage of the transistor, there are many control signals, which complicates the circuit structure.
有鑑於上述習知技術的問題，本發明提供一種像素驅動電路，其包含：發光元件、第一電源線、脈衝調幅電晶體、發光驅動電容器、脈衝調寬驅動電路、脈衝調幅驅動電路、脈衝調幅感測電路以及脈衝調寬電晶體；發光元件係配置以根據驅動電流發光；第一電源線連接發光元件，以提供驅動電流；脈衝調幅電晶體之第一端連接第一電源線，第二端連接發光元件之陽極，且驅動電流之振幅係根據脈衝調幅電晶體之控制端之控制端電壓而改變；發光驅動電容器之一端連接脈衝調幅電晶體之第一端，其另一端連接脈衝調幅電晶體之 控制端；脈衝調寬驅動電路包含：第一電容器、第二電容器、第一電晶體以及第二電晶體，第一電容器包含第一端以及第二端；第二電容器包含第一端以及第二端，第二電容器之第一端連接第一電容器之第一端於串接節點；第一電晶體之第一端連接串接節點；第二電晶體之第一端連接第二電容器之第二端；脈衝調幅驅動電路連接脈衝調幅電晶體之控制端；脈衝調幅感測電路連接脈衝調幅電晶體之第二端；脈衝調寬電晶體之控制端連接脈衝調寬驅動電路之輸出節點，其第一端連接脈衝調幅電晶體之控制端，以透過脈衝調幅電晶體控制驅動電流之驅動歷時。 In view of the above-mentioned problems of the prior art, the present invention provides a pixel driving circuit, which includes: a light-emitting element, a first power line, a pulse amplitude modulation transistor, a light-emitting driving capacitor, a pulse width modulation driving circuit, a pulse amplitude modulation driving circuit, and a pulse amplitude modulation The sensing circuit and the pulse width modulation transistor; the light emitting element is configured to emit light according to the driving current; the first power line is connected to the light emitting element to provide the driving current; the first end of the pulse amplitude modulation transistor is connected to the first power line, and the second end Connect the anode of the light-emitting element, and the amplitude of the drive current is changed according to the control terminal voltage of the pulse amplitude modulation transistor; one end of the light-emitting drive capacitor is connected to the first end of the pulse amplitude modulation transistor, and the other end is connected to the pulse amplitude modulation transistor Of Control terminal; pulse width modulation drive circuit includes: a first capacitor, a second capacitor, a first transistor and a second transistor, the first capacitor includes a first terminal and a second terminal; the second capacitor includes a first terminal and a second terminal Terminal, the first terminal of the second capacitor is connected to the first terminal of the first capacitor at the series connection node; the first terminal of the first transistor is connected to the series connection node; the first terminal of the second transistor is connected to the second capacitor Terminal; the pulse amplitude modulation drive circuit is connected to the control terminal of the pulse amplitude modulation transistor; the pulse amplitude modulation sensing circuit is connected to the second terminal of the pulse amplitude modulation transistor; the control terminal of the pulse width modulation transistor is connected to the output node of the pulse width modulation drive circuit. One end is connected to the control end of the pulse amplitude modulation transistor to control the driving duration of the driving current through the pulse amplitude modulation transistor.
其中脈衝調寬驅動電路之輸出節點係第二電容器之第二端。 The output node of the pulse width modulation driving circuit is the second end of the second capacitor.
較佳地，脈衝調幅驅動電路可以包含第三電晶體，第三電晶體之第一端連接脈衝調幅電晶體之控制端。 Preferably, the pulse amplitude modulation drive circuit may include a third transistor, and the first terminal of the third transistor is connected to the control terminal of the pulse amplitude modulation transistor.
較佳地，脈衝調幅感測電路可以包含脈衝調幅感測電晶體，脈衝調幅感測電晶體之第一端連接脈衝調幅電晶體之第二端，以及脈衝調幅感測電晶體係設置以對脈衝調幅電晶體之閾值電壓進行補償。 Preferably, the pulse amplitude modulation sensing circuit may include a pulse amplitude modulation sensing transistor, the first end of the pulse amplitude modulation sensing transistor is connected to the second end of the pulse amplitude modulation transistor, and the pulse amplitude modulation sensing transistor system is set to adjust the pulse The threshold voltage of the amplitude modulation transistor is compensated.
較佳地，第一電晶體之控制端可以連接第一掃描線、第二電晶體之控制端連接第二掃描線、第三電晶體之控制端連接第三掃描線以及脈衝調幅感測電晶體之控制端連接第四掃描線，且第一掃描線、第二掃描線、第三掃描線以及第四掃描線連接解多工器。 Preferably, the control terminal of the first transistor can be connected to the first scan line, the control terminal of the second transistor is connected to the second scan line, the control terminal of the third transistor is connected to the third scan line and the pulse amplitude modulation sensing transistor The control terminal is connected to the fourth scan line, and the first scan line, the second scan line, the third scan line and the fourth scan line are connected to the demultiplexer.
較佳地，第一電晶體之第二端、第二電晶體之第二端、第三電晶體之第二端以及脈衝調幅感測電晶體之第二端可以連接第一資料線，第一電容器之第二端連接第二資料線。 Preferably, the second end of the first transistor, the second end of the second transistor, the second end of the third transistor, and the second end of the pulse amplitude modulation sensing transistor can be connected to the first data line, the first The second end of the capacitor is connected to the second data line.
較佳地，第三電晶體係設置以對脈衝調寬電晶體之閾值電壓進行補償。 Preferably, the third transistor system is configured to compensate the threshold voltage of the pulse width modulation transistor.
較佳地，脈衝調幅電晶體以及脈衝調寬電晶體可以是低溫多晶矽(LTPS)電晶體。 Preferably, the pulse amplitude modulation transistor and the pulse width modulation transistor may be low temperature polysilicon (LTPS) transistors.
較佳地，第一電晶體、第二電晶體、第三電晶體以及脈衝調幅感測電晶體可以是氧化銦鎵鋅(IGZO)電晶體。 Preferably, the first transistor, the second transistor, the third transistor and the pulse amplitude modulation sensing transistor may be indium gallium zinc oxide (IGZO) transistors.
根據本發明另一實施例，提供本發明提供一種像素驅動電路，其包含：發光元件、第一電源線、脈衝調幅電晶體、發光驅動電容器、脈衝調寬驅動電路、開關電晶體、脈衝調寬電晶體、脈衝調幅感測電晶體以及發光控制電容器，發光元件係配置以根據驅動電流發光；第一電源線連接發光元件，以提供驅動電流；脈衝調幅電晶體之第一端連接第一電源線，第二端連接發光元件之陽極，且驅動電流之振幅係根據脈衝調幅電晶體之控制端的電壓而改變；發光驅動電容器之一端連接脈衝調幅電晶體之第一端，另一端連接脈衝調幅電晶體之控制端；脈衝調寬驅動電路包含：第一電容器、第二電容器、第一電晶體、第二電晶體以及第三電晶體，第一電容器包含第一端以及第二端；第二電容器包含第一端以及第二端，第二電容器之第一端連接第一電容器之第一端於串接節點；第一電晶體之第一端連接第一資料線，第二端連接串接節點；第二電晶體之第一端連接第二電容器之第二端；開關電晶體之第一端連接脈衝調幅電晶體之控制端，第二端連接第三電晶體之第一端；脈衝調寬電晶體之控制端連接第二電晶體之第一端，脈衝調寬電晶體之第一端連接開關電晶體之控制端以及第二電晶體之第二端，以根據開關電晶體透過脈衝調幅電晶體控制驅動電流之驅動歷時；脈衝調幅感測電晶體之控制端連接第二電晶體之控制端，脈衝調幅感測電晶體之第一端連接脈衝調幅電晶體之第二端，第二端連接脈衝調幅電晶體之控制端；發光控制電容器之一端連接開關電晶體之第二端。 According to another embodiment of the present invention, the present invention provides a pixel driving circuit, which includes: a light-emitting element, a first power line, a pulse amplitude modulation transistor, a light-emitting driving capacitor, a pulse width modulation driving circuit, a switching transistor, and a pulse width modulation Transistor, pulse amplitude modulation sensing transistor, and light emitting control capacitor. The light emitting element is configured to emit light according to the driving current; the first power line is connected to the light emitting element to provide driving current; the first end of the pulse amplitude modulation transistor is connected to the first power line , The second end is connected to the anode of the light-emitting element, and the amplitude of the driving current is changed according to the voltage of the control terminal of the pulse amplitude modulation transistor; one end of the light-emitting drive capacitor is connected to the first end of the pulse amplitude modulation transistor, and the other end is connected to the pulse amplitude modulation transistor The control terminal; the pulse width modulation drive circuit includes: a first capacitor, a second capacitor, a first transistor, a second transistor and a third transistor, the first capacitor includes a first terminal and a second terminal; the second capacitor includes A first end and a second end, the first end of the second capacitor is connected to the first end of the first capacitor at the series connection node; the first end of the first transistor is connected to the first data line, and the second end is connected to the series connection node; The first terminal of the second transistor is connected to the second terminal of the second capacitor; the first terminal of the switching transistor is connected to the control terminal of the pulse amplitude modulation transistor, and the second terminal is connected to the first terminal of the third transistor; the pulse width modulation circuit The control terminal of the crystal is connected to the first terminal of the second transistor, and the first terminal of the pulse width modulation transistor is connected to the control terminal of the switching transistor and the second terminal of the second transistor, so as to transmit the pulse amplitude modulation transistor according to the switching transistor Control the driving duration of the drive current; the control terminal of the pulse amplitude modulation sensing transistor is connected to the control terminal of the second transistor, the first terminal of the pulse amplitude modulation sensing transistor is connected to the second terminal of the pulse amplitude modulation transistor, and the second terminal is connected to the pulse The control terminal of the amplitude modulation transistor; one terminal of the light-emitting control capacitor is connected to the second terminal of the switching transistor.
較佳地，脈衝調幅感測電晶體可以是設置以對脈衝調幅電晶體之閾值電壓進行補償。 Preferably, the pulse amplitude modulation sensing transistor can be set to compensate the threshold voltage of the pulse amplitude modulation transistor.
較佳地，第一電晶體之控制端可以連接第一掃描線、第二電晶體之控制端連接第二掃描線，以及脈衝調幅感測電晶體之控制端連接第三掃描線，第一掃描線、第二掃描線以及第三掃描線連接解多工器。 Preferably, the control terminal of the first transistor can be connected to the first scan line, the control terminal of the second transistor is connected to the second scan line, and the control terminal of the pulse amplitude modulation sensing transistor is connected to the third scan line, the first scan The line, the second scan line and the third scan line are connected to the demultiplexer.
較佳地，第一電容器之第二端可以連接第二資料線。 Preferably, the second terminal of the first capacitor can be connected to the second data line.
較佳地，脈衝調寬電晶體之第二端可以連接第二電源線。 Preferably, the second end of the pulse width modulation transistor can be connected to the second power line.
較佳地，脈衝調幅電晶體以及脈衝調寬電晶體可以是低溫多晶矽(LTPS)電晶體。 Preferably, the pulse amplitude modulation transistor and the pulse width modulation transistor may be low temperature polysilicon (LTPS) transistors.
較佳地，第一電晶體、第二電晶體、第三電晶體、開關電晶體以及脈衝調幅感測電晶體可以是氧化銦鎵鋅(IGZO)電晶體。 Preferably, the first transistor, the second transistor, the third transistor, the switching transistor, and the pulse amplitude modulation sensing transistor may be indium gallium zinc oxide (IGZO) transistors.
100,400:像素驅動電路 100,400: Pixel drive circuit
101,401:發光元件 101, 401: light-emitting elements
C1:第一電容器 C1: The first capacitor
C2:第二電容器 C2: second capacitor
Cst:發光驅動電容器 Cst: Light-emitting drive capacitor
Cp:發光控制電容器 Cp: luminescence control capacitor
DR1:脈衝調寬驅動電路 DR1: Pulse width modulation drive circuit
DR2:脈衝調幅驅動電路 DR2: Pulse amplitude modulation drive circuit
Id:驅動電流 Id: drive current
PL1:第一電源線 PL1: The first power cord
PL2:第二電源線 PL2: second power cord
S:串接節點 S: serial node
SR1:脈衝調幅感測電路 SR1: Pulse amplitude modulation sensing circuit
SL1:第一掃描線 SL1: the first scan line
SL2:第二掃描線 SL2: second scan line
SL3:第三掃描線 SL3: Third scan line
SL4:第四掃描線 SL4: Fourth scan line
Tsw:開關電晶體 Tsw: switching transistor
Tg1:第一電晶體 Tg1: first transistor
Tg2:第二電晶體 Tg2: second transistor
Tg3:第三電晶體 Tg3: third transistor
Tg4:脈衝調幅感測電晶體 Tg4: Pulse amplitude modulation sensing transistor
Tp:脈衝調寬電晶體 Tp: Pulse width modulation transistor
Td:脈衝調幅電晶體 Td: Pulse amplitude modulation transistor
V1,Vs1,V2,Vs2:電壓位準 V1, Vs1, V2, Vs2: voltage level
Vdata_PWM,Vdata_PAM:資料電壓 V data_PWM ,V data_PAM : data voltage
Vw:電壓訊號 V w : voltage signal
Vth:閾值電壓 V th : threshold voltage
第1圖係繪示根據本發明一實施例之像素驅動電路示意圖。 FIG. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention.
第2圖係繪示第1圖所示之像素驅動電路之操作時序圖。 FIG. 2 is a timing diagram of the operation of the pixel driving circuit shown in FIG. 1. FIG.
第3(A)圖至第3(G)圖係分別繪示對應第2圖所示時序圖之操作階段示意圖。 Fig. 3(A) to Fig. 3(G) are schematic diagrams of operation stages corresponding to the timing diagram shown in Fig. 2 respectively.
第4圖係繪示根據本發明一實施例之像素驅動電路示意圖。 FIG. 4 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention.
第5(A)圖至第5(K)圖係分別繪示第4圖之像素驅動電路之操作階段示意圖。 5(A) to 5(K) are schematic diagrams showing the operation stages of the pixel driving circuit in FIG. 4, respectively.
為利貴審查委員瞭解本發明之技術特徵、內容與優點及其所能達成之功效，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之 真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的申請專利範圍，合先敘明。 In order to facilitate the reviewers to understand the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is described in detail with the accompanying drawings and in the form of embodiment expressions as follows. The drawings used therein are as follows: The subject matter is for illustrative and auxiliary manual purposes only, and may not be after the implementation of the present invention The true ratio and precise configuration should not be interpreted in terms of the ratio and configuration relationship of the attached drawings, and should not limit the scope of the patent application for the actual implementation of the present invention, and shall be stated first.
參照第1圖，其繪示根據本發明一實施例之像素驅動電路示意圖。像素驅動電路100包含：發光元件101、第一電源線PL1、脈衝調幅電晶體Td、發光驅動電容器Cst、脈衝調寬驅動電路DR1、脈衝調幅驅動電路DR2、脈衝調幅感測電路SR1以及脈衝調寬電晶體Tp；發光元件101係配置以根據驅動電流Id發光；第一電源線PL1連接發光元件101，以提供驅動電流Id；脈衝調幅電晶體Td之第一端連接第一電源線PL1，第二端連接發光元件101之陽極，且驅動電流Id之振幅係根據脈衝調幅電晶體Td之控制端之控制端電壓而改變；發光驅動電容器Cst之一端連接脈衝調幅電晶體Td之第一端，其另一端連接脈衝調幅電晶體Td之控制端；脈衝調幅驅動電路DR2連接脈衝調幅電晶體Td之控制端；脈衝調幅感測電路SR1連接脈衝調幅電晶體Td之第二端；脈衝調寬電晶體Tp之控制端連接脈衝調寬驅動電路DR1之輸出節點，脈衝調寬電晶體Tp之第一端連接脈衝調幅電晶體Td之控制端，以透過脈衝調幅電晶體Td控制驅動電流Id之驅動歷時。
Referring to FIG. 1, it shows a schematic diagram of a pixel driving circuit according to an embodiment of the present invention. The
脈衝調寬驅動電路DR1包含：第一電容器C1、第二電容器C2、第一電晶體Tg1以及第二電晶體Tg2，第一電容器C1包含第一端以及第二端；第二電容器C2包含第一端以及第二端，第二電容器C2之第一端連接第一電容器C1之第一端於串接節點S；第一電晶體Tg1之第一端連接串接節點S；第二電晶體Tg2之第一端連接第二電容器C2之第二端。 The pulse width modulation driving circuit DR1 includes: a first capacitor C1, a second capacitor C2, a first transistor Tg1, and a second transistor Tg2. The first capacitor C1 includes a first terminal and a second terminal; and the second capacitor C2 includes a first terminal. The first end of the second capacitor C2 is connected to the first end of the first capacitor C1 at the series connection node S; the first end of the first transistor Tg1 is connected to the series connection node S; the second end of the second transistor Tg2 The first terminal is connected to the second terminal of the second capacitor C2.
其中脈衝調寬驅動電路DR1之輸出節點係第二電容器之第二端。 The output node of the pulse width modulation driving circuit DR1 is the second end of the second capacitor.
應當注意，本實施例係以PMOSFET作為脈衝調幅電晶體Td，在其他實施例中，可以NMOSFET串接發光元件101實現本發明提供之像素驅動電路。
It should be noted that this embodiment uses a PMOSFET as the pulse amplitude modulation transistor Td. In other embodiments, the NMOSFET can be connected in series with the light-emitting
根據本發明一實施例，脈衝調幅驅動電路DR2可以包含第三電晶體Tg3，第三電晶體Tg3之第一端連接脈衝調幅電晶體Td之控制端。 According to an embodiment of the present invention, the pulse amplitude modulation driving circuit DR2 may include a third transistor Tg3, and the first terminal of the third transistor Tg3 is connected to the control terminal of the pulse amplitude modulation transistor Td.
通常，在同一個顯示面板中的每一個像素驅動電路的電晶體的閾值電壓存在差異，這種差異導致了顯示面板亮度均勻性的劣化，因此，需要對上述電晶體的閾值電壓差異進行補償，根據本發明一實施例，脈衝調幅感測電路SR1可以包含脈衝調幅感測電晶體Tg4，脈衝調幅感測電晶體Tg4之第一端連接脈衝調幅電晶體Td之第二端，以及脈衝調幅感測電晶體Tg4係設置以對脈衝調幅電晶體Td之閾值電壓進行補償，將後述詳細的補償機制。 Generally, there is a difference in the threshold voltage of the transistor of each pixel driving circuit in the same display panel, and this difference causes the deterioration of the brightness uniformity of the display panel. Therefore, it is necessary to compensate for the difference in the threshold voltage of the above-mentioned transistor. According to an embodiment of the present invention, the pulse amplitude modulation sensing circuit SR1 may include a pulse amplitude modulation sensing transistor Tg4, the first terminal of the pulse amplitude modulation sensing transistor Tg4 is connected to the second terminal of the pulse amplitude modulation transistor Td, and the pulse amplitude modulation sensing The transistor Tg4 is set to compensate the threshold voltage of the pulse amplitude modulation transistor Td. The detailed compensation mechanism will be described later.
進一步地，將第一電晶體Tg1之控制端連接第一掃描線SL1、第二電晶體Tg2之控制端連接第二掃描線SL2、第三電晶體Tg3之控制端連接第三掃描線SL3，且脈衝調幅感測電晶體Tg4之控制端連接第四掃描線SL4，此外，將第一掃描線SL1、第二掃描線SL2、第三掃描線SL3以及第四掃描線SL4連接解多工器，第一電晶體Tg1之第二端、第二電晶體Tg2之第二端、第三電晶體Tg3之第二端以及脈衝調幅感測電晶體Tg4之第二端連接第一資料線DL1，第一電容器C1之第二端連接第二資料線DL2。 Further, the control terminal of the first transistor Tg1 is connected to the first scan line SL1, the control terminal of the second transistor Tg2 is connected to the second scan line SL2, and the control terminal of the third transistor Tg3 is connected to the third scan line SL3, and The control end of the pulse amplitude modulation sensing transistor Tg4 is connected to the fourth scan line SL4. In addition, the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 are connected to the demultiplexer. The second terminal of a transistor Tg1, the second terminal of the second transistor Tg2, the second terminal of the third transistor Tg3, and the second terminal of the pulse amplitude modulation sensing transistor Tg4 are connected to the first data line DL1, the first capacitor The second end of C1 is connected to the second data line DL2.
根據本發明一實施例，第三電晶體Tg3係設置以對脈衝調寬電晶體Tp之閾值電壓進行補償，將描述詳細的補償機制於下文。 According to an embodiment of the present invention, the third transistor Tg3 is configured to compensate the threshold voltage of the pulse width modulation transistor Tp. The detailed compensation mechanism will be described below.
接下來請同時參照第2圖及第3(A)圖至第3(G)圖，第2圖係繪示根據本發明一實施例說明像素驅動電路100的詳細操作的時序圖，第3(A)圖至第
3(G)圖係分別繪示對應第2圖所示時序圖之階段T1至階段T6之像素驅動電路100之示意圖，其中階段T6以第3(F)圖及第3(G)圖來繪示。
Next, please refer to FIG. 2 and FIG. 3(A) to FIG. 3(G) at the same time. FIG. 2 is a timing diagram illustrating the detailed operation of the
請先參照第2圖的階段T1以及第3(A)圖，在階段T1中，於脈衝調寬電晶體Tp第二端(第1圖A點)輸入電壓位準V1，透過第一資料線DL1輸入電壓位準Vs1，且V1>Vs1。階段T1進一步區分為虛線左側之電壓重置階段以及虛線右側的脈衝調幅電晶體Td之感測階段，其中電壓重置階段係指以通過掃描線SL1~SL4之訊號導通電晶體Tg1~Tg4，進行電晶體Tg1~Tg4之電壓重置，而後在虛線右側之脈衝調寬電晶體Tp之感測階段截止電晶體Tg1、Tg2及Tg4，以進行如第3(A)圖中的實線箭頭所示的脈衝調寬電晶體Tp感測，以對脈衝調寬電晶體Tp之閾值電壓進行補償。 Please refer to the stage T1 in Figure 2 and Figure 3(A). In stage T1, the voltage level V1 is input to the second end of the pulse width modulation transistor Tp (point A in Figure 1) through the first data line The DL1 input voltage level is Vs1, and V1>Vs1. Stage T1 is further divided into the voltage reset stage on the left side of the dashed line and the pulse amplitude modulation transistor Td sensing stage on the right side of the dashed line. The voltage reset stage refers to the signal passing through the scan lines SL1~SL4 to turn on the transistors Tg1~Tg4. The voltages of the transistors Tg1~Tg4 are reset, and then the transistors Tg1, Tg2, and Tg4 are turned off at the sensing stage of the pulse width transistor Tp on the right side of the dotted line, as shown by the solid arrow in Figure 3(A) The pulse width modulation transistor Tp is sensed to compensate the threshold voltage of the pulse width modulation transistor Tp.
接下來請參照第2圖的階段T2以及第3(B)圖，在階段T2中，於脈衝調寬電晶體Tp第二端(第1圖A點)輸入電壓位準V2，透過第一資料線DL1輸入電壓位準Vs2，且V2<Vs2。同樣地，階段T2進一步區分為虛線左側之電壓重置階段以及虛線右側的脈衝調幅電晶體Td之感測階段，其中電壓重置階段係指以通過掃描線SL1~SL4之訊號導通電晶體Tg1~Tg4，進行電晶體Tg1~Tg4之電壓重置，而後在虛線右側之脈衝調幅電晶體Td之感測階段截止電晶體Tg1~Tg3，以進行如第3(B)圖中的實線箭頭所示的脈衝調幅電晶體Td感測，以對脈衝調幅電晶體Td之閾值電壓進行補償。 Next, please refer to the stage T2 of Fig. 2 and Fig. 3(B). In stage T2, the voltage level V2 is input to the second terminal of the pulse width modulation transistor Tp (point A in Fig. 1) through the first data The input voltage level of line DL1 is Vs2, and V2<Vs2. Similarly, the stage T2 is further divided into the voltage reset stage on the left side of the dashed line and the pulse amplitude modulation transistor Td sensing stage on the right side of the dashed line. The voltage reset stage refers to the signal passing through the scan lines SL1 to SL4 to turn on the transistor Tg1~ Tg4, reset the voltage of the transistors Tg1~Tg4, and then cut off the transistors Tg1~Tg3 in the sensing phase of the pulse amplitude modulation transistor Td on the right side of the dotted line, as shown by the solid arrow in Figure 3(B) The pulse amplitude modulation transistor Td is sensed to compensate the threshold voltage of the pulse amplitude modulation transistor Td.
接下來請參照第2圖的階段T3以及第3(C)圖，在階段T3中，對脈衝調寬電晶體Tp之控制端電壓進行重置，以作為對下面即將描述的T6階段的準備。 Next, please refer to the stage T3 of Fig. 2 and Fig. 3(C). In stage T3, the control terminal voltage of the pulse width modulation transistor Tp is reset to prepare for the T6 stage described below.
在第2圖的階段T4以及所對應的第3(D)圖中，進行脈衝調寬資料電壓Vdata_PWM的寫入。在第2圖的階段T5以及所對應的第3(E)圖中，進行脈衝調幅資料電壓Vdata_PAM的寫入。在一實施例中，於脈衝調寬資料電壓Vdata_PWM的寫 入階段，電壓訊號Vw為一遞增電壓或一固定電壓；於脈衝調幅資料電壓Vdata_PAM的寫入階段，電壓訊號Vw為一遞增電壓或一固定電壓。 In the stage T4 of Fig. 2 and the corresponding Fig. 3(D), the pulse width modulation data voltage V data_PWM is written. In the stage T5 of Fig. 2 and the corresponding Fig. 3(E), the pulse amplitude modulation data voltage V data_PAM is written. In one embodiment, during the writing phase of the pulse width modulation data voltage V data_PWM , the voltage signal Vw is an increasing voltage or a fixed voltage; during the writing phase of the pulse amplitude modulation data voltage V data_PAM , the voltage signal Vw is an increasing voltage Or a fixed voltage.
接下來請參照第2圖的T6階段以及所對應之第3(F)圖及第3(G)圖，以說明本發明技術特徵之透過電壓訊號Vw以及脈衝調寬電晶體Tp和脈衝調幅電晶體Td之設置調制(modulate)驅動電流Id之驅動歷時及振幅。其中，在第3(F)圖中，因脈衝調幅電晶體Td之控制端電壓小於脈衝調幅電晶體Td之第一端的電壓，脈衝調幅電晶體Td因而導通，致使發光元件101發光，在第3(G)圖中，因電壓訊號Vw的輸入，脈衝調寬電晶體Tp之控制端電壓從而小於脈衝調寬電晶體Tp之第二端的電壓，脈衝調寬電晶體Tp因而導通，進一步導致脈衝調幅電晶體Td之控制端電壓上升，導致脈衝調幅電晶體Td截止，致使發光元件101不發光。
Next, please refer to the T6 stage in Figure 2 and the corresponding Figures 3(F) and 3(G) to illustrate the technical characteristics of the present invention through voltage signal V w , pulse width modulation transistor Tp and pulse amplitude modulation The transistor Td is set to modulate the driving duration and amplitude of the driving current Id. Among them, in Figure 3(F), because the control terminal voltage of the pulse amplitude modulation transistor Td is less than the voltage of the first terminal of the pulse amplitude modulation transistor Td, the pulse amplitude modulation transistor Td is therefore turned on, causing the
根據本發明一實施例，脈衝調幅電晶體Td以及脈衝調寬電晶體Tp可以是低溫多晶矽(LTPS)電晶體，但本發明不限於此。 According to an embodiment of the present invention, the pulse amplitude modulation transistor Td and the pulse width modulation transistor Tp may be low temperature polysilicon (LTPS) transistors, but the present invention is not limited thereto.
根據本發明一實施例，第一電晶體Tg1、第二電晶體Tg2、第三電晶體Tg3以及脈衝調幅感測電晶體Tg4可以是氧化銦鎵鋅(IGZO)電晶體，但本發明不限於此。 According to an embodiment of the present invention, the first transistor Tg1, the second transistor Tg2, the third transistor Tg3, and the pulse amplitude modulation sensing transistor Tg4 may be indium gallium zinc oxide (IGZO) transistors, but the present invention is not limited thereto. .
接下來，根據本發明另一實施例，參照第4圖，其繪示根據本發明一實施例之像素驅動電路示意圖。像素驅動電路400包含：發光元件401、第一電源線PL1、脈衝調幅電晶體Td、發光驅動電容器Cst、脈衝調寬驅動電路DR1、開關電晶體Tsw、脈衝調寬電晶體Tp、脈衝調幅感測電晶體Tg4以及發光控制電容器Cp，發光元件401係配置以根據驅動電流Id發光；第一電源線PL1連接發光元件401，以提供驅動電流Id；脈衝調幅電晶體Td之第一端連接第一電源線PL1，第二端連接發光元件401之陽極，且驅動電流Id之振幅係根據脈衝調幅電晶體Td之控制端的電壓而改變；發光驅動電容器Cst之一端連接脈衝調幅電晶
體Td之第一端，另一端連接脈衝調幅電晶體Td之控制端；脈衝調寬驅動電路DR1包含：第一電容器C1、第二電容器C2、第一電晶體Tg1、第二電晶體Tg2以及第三電晶體Tg3，第一電容器C1包含第一端以及第二端；第二電容器C2包含第一端以及第二端，第二電容器C2之第一端連接第一電容器C1之第一端於串接節點S；第一電晶體Tg1之第一端連接第一資料線DL1，第二端連接串接節點S；第二電晶體Tg2之第一端連接第二電容器C2之第二端；開關電晶體Tsw之第一端連接脈衝調幅電晶體Td之控制端，第二端連接第三電晶體Tg3之第一端；脈衝調寬電晶體Tp之控制端連接第二電晶體Tg2之第一端，脈衝調寬電晶體Tp之第一端連接開關電晶體Tsw之控制端以及第二電晶體Tg2之第二端，以根據開關電晶體Tsw透過脈衝調幅電晶體Td控制驅動電流Id之驅動歷時；脈衝調幅感測電晶體Tg4之控制端連接第二電晶體Tg2之控制端，脈衝調幅感測電晶體Tg4之第一端連接脈衝調幅電晶體Td之第二端，第二端連接脈衝調幅電晶體Td之控制端；發光控制電容器Cp之一端連接開關電晶體Tsw之第二端。
Next, according to another embodiment of the present invention, referring to FIG. 4, which illustrates a schematic diagram of a pixel driving circuit according to an embodiment of the present invention. The pixel driving circuit 400 includes: a light-emitting
應當注意，本實施例係以PMOSFET作為脈衝調幅電晶體Td，在其他實施例中，可以NMOSFET串接發光元件401實現本發明提供之像素驅動電路。
It should be noted that this embodiment uses a PMOSFET as the pulse amplitude modulation transistor Td. In other embodiments, the NMOSFET can be connected in series with the light-emitting
在本實施例中，同樣存在著如上所述在同一個顯示面板中的每一個像素驅動電路的電晶體的閾值電壓存在差異的狀況，這種差異導致了顯示面板亮度均勻性的劣化，因此，需要對上述電晶體的閾值電壓差異進行補償，其中，脈衝調幅感測電晶體Tg4便是設置以對脈衝調幅電晶體Td之閾值電壓進行補償，其補償機制將詳述於下文。 In this embodiment, there is also a difference in the threshold voltage of the transistor of each pixel driving circuit in the same display panel as described above. This difference leads to the deterioration of the brightness uniformity of the display panel. Therefore, The threshold voltage difference of the above-mentioned transistors needs to be compensated. The pulse amplitude modulation sensing transistor Tg4 is set to compensate the threshold voltage of the pulse amplitude modulation transistor Td. The compensation mechanism will be described in detail below.
進一步地，將第一電晶體Tg1之控制端連接第一掃描線SL1、第二電晶體Tg2之控制端連接第二掃描線SL2，以及第三電晶體Tg3之控制端連接第三掃描線SL3，第一掃描線SL1、第二掃描線SL2以及第三掃描線SL3連接解多工器，第一電容器C1之第二端連接第二資料線DL2，脈衝調寬電晶體Tp之第二端連接第二電源線PL2。 Further, the control terminal of the first transistor Tg1 is connected to the first scan line SL1, the control terminal of the second transistor Tg2 is connected to the second scan line SL2, and the control terminal of the third transistor Tg3 is connected to the third scan line SL3, The first scan line SL1, the second scan line SL2, and the third scan line SL3 are connected to the demultiplexer, the second end of the first capacitor C1 is connected to the second data line DL2, and the second end of the pulse width modulation transistor Tp is connected to the second end Two power cord PL2.
接下來請參照第5(A)圖至第5(K)圖，第5(A)圖至第5(K)圖係根據本發明一實施例分別繪示像素驅動電路400之各階段驅動示意圖，在所繪示的本實施例中，所施加的電壓值僅為示例，該些電壓值旨在說明像素驅動電路的驅動方式，而不旨在限制。 Next, please refer to Fig. 5(A) to Fig. 5(K), Fig. 5(A) to Fig. 5(K) are schematic diagrams of each stage of the pixel driving circuit 400 according to an embodiment of the present invention. In the illustrated embodiment, the applied voltage values are only examples, and these voltage values are intended to illustrate the driving method of the pixel driving circuit, and are not intended to limit.
請先參照第5(A)圖，在此階段中，係以所示的電壓配置透過掃描線SL1~SL3之訊號導通電晶體Tg1~Tg4，進行電晶體Tg1~Tg4之電壓重置。 Please refer to Figure 5(A) first. At this stage, the signal through the scan lines SL1~SL3 is turned on by the transistors Tg1~Tg4 in the voltage configuration shown, and the voltage of the transistors Tg1~Tg4 is reset.
在第5(B)圖中，將第一資料線DL1的電壓由5V降為0V，以對脈衝調寬電晶體Tp之控制端電壓進行重置。 In Figure 5(B), the voltage of the first data line DL1 is reduced from 5V to 0V to reset the control terminal voltage of the pulse width modulation transistor Tp.
在第5(C)圖中，將第二電源線PL2之電壓升高為10V，以對脈衝調寬電晶體Tp之閾值電壓Vth進行補償。在第5(D)圖中，將第二電源線PL2之電壓升高為12V，以截止開關電晶體Tsw，並且直到後面即將描述的第5(K)圖的階段才重新導通開關電晶體Tsw。 In Fig. 5(C), the voltage of the second power line PL2 is increased to 10V to compensate the threshold voltage V th of the pulse width modulation transistor Tp. In Figure 5(D), the voltage of the second power line PL2 is increased to 12V to turn off the switching transistor Tsw, and the switching transistor Tsw is not turned on again until the stage of Figure 5(K) described later .
在第5(E)圖中，將第一電源線PL1之電壓由0V提高為10V，並提供相同位準的10V電壓給發光元件401的陰極(以避免發光元件401在此階段發光)，完成脈衝調幅電晶體Td之閾值電壓的補償。
In Figure 5(E), the voltage of the first power line PL1 is increased from 0V to 10V, and the same level of 10V voltage is provided to the cathode of the light-emitting element 401 (to prevent the light-emitting
在第5(F)圖中，將第二電源線PL2的電壓位準由12V降低至0V，並將第二掃描線SL2的電壓由-5V改為12V，所有電晶體截止。在第5(G)圖中，如 圖中箭頭所示，進行脈衝調幅資料電壓Vdata_PAM的寫入。在第5(H)圖中，如圖中箭頭所示，進行脈衝調寬資料電壓Vdata_PWM的寫入，並於第5(I)圖中，對第一資料線DL1施加5V電壓位準，截止第一電晶體Tg1。 In Figure 5(F), the voltage level of the second power line PL2 is reduced from 12V to 0V, and the voltage of the second scan line SL2 is changed from -5V to 12V, and all transistors are turned off. In Figure 5(G), as indicated by the arrow in the figure, the pulse amplitude modulation data voltage V data_PAM is written. In Figure 5(H), as shown by the arrow in the figure, the pulse width modulation data voltage V data_PWM is written, and in Figure 5(I), a voltage level of 5V is applied to the first data line DL1, Turn off the first transistor Tg1.
應當注意，於第1圖至第3(G)圖所示的實施例中，發光元件101由第3(F)圖所示的發光狀態變為第3(G)圖所示的不發光狀態，相較於該實施例，本實施例(對應第4圖至第5(K)圖)之像素驅動電路400之發光元件401係由即將描述的第5(J)圖所示的不發光狀態變為由第5(K)圖所示的發光狀態。
It should be noted that in the embodiments shown in FIGS. 1 to 3(G), the light-emitting
在第5(J)圖中，透過第二資料線DL2輸入之電壓訊號Vw係一線性遞減電壓，其導通脈衝調寬電晶體Tp以及開關電晶體Tsw(如第5(K)圖所示)，並因此導通脈衝調幅電晶體Td，致使發光元件401發光，完成本發明提供之透過電壓訊號Vw以及脈衝調寬電晶體Tp和脈衝調幅電晶體Td之設置調制(modulate)驅動電流Id之驅動歷時及振幅之技術特徵。
In Figure 5(J), the voltage signal V w input through the second data line DL2 is a linearly decreasing voltage, which turns on the pulse width modulation transistor Tp and the switching transistor Tsw (as shown in Figure 5(K)) ), and therefore turn on the pulse amplitude modulation transistor Td, causing the light-emitting
根據本發明一實施例，脈衝調幅電晶體Td以及脈衝調寬電晶體Tp可以是低溫多晶矽(LTPS)電晶體。 According to an embodiment of the present invention, the pulse amplitude modulation transistor Td and the pulse width modulation transistor Tp may be low temperature polysilicon (LTPS) transistors.
根據本發明一實施例，第一電晶體Tg1、第二電晶體Tg2、第三電晶體Tg3、開關電晶體Tsw以及脈衝調幅感測電晶體Tg4可以是氧化銦鎵鋅(IGZO)電晶體。 According to an embodiment of the present invention, the first transistor Tg1, the second transistor Tg2, the third transistor Tg3, the switching transistor Tsw, and the pulse amplitude modulation sensing transistor Tg4 may be indium gallium zinc oxide (IGZO) transistors.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。 The above description is only illustrative, and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.
100:像素驅動電路 100: Pixel drive circuit
101:發光元件 101: Light-emitting element
C1:第一電容器 C1: The first capacitor
C2:第二電容器 C2: second capacitor
Cst:發光驅動電容器 Cst: Light-emitting drive capacitor
DR1:脈衝調寬驅動電路 DR1: Pulse width modulation drive circuit
DR2:脈衝調幅驅動電路 DR2: Pulse amplitude modulation drive circuit
Id:驅動電流 Id: drive current
PL1:第一電源線 PL1: The first power cord
S:串接節點 S: serial node
SR1:脈衝調幅感測電路 SR1: Pulse amplitude modulation sensing circuit
SL1:第一掃描線 SL1: the first scan line
SL2:第二掃描線 SL2: second scan line
SL3:第三掃描線 SL3: Third scan line
SL4:第四掃描線 SL4: Fourth scan line
Tg1:第一電晶體 Tg1: first transistor
Tg2:第二電晶體 Tg2: second transistor
Tg3:第三電晶體 Tg3: third transistor
Tg4:脈衝調幅感測電晶體 Tg4: Pulse amplitude modulation sensing transistor
Tp:脈衝調寬電晶體 Tp: Pulse width modulation transistor
Td:脈衝調幅電晶體 Td: Pulse amplitude modulation transistor
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW109102491A TWI719815B (en) | 2020-01-22 | 2020-01-22 | Driving circuit for pixel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW109102491A TWI719815B (en) | 2020-01-22 | 2020-01-22 | Driving circuit for pixel |
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| Publication Number | Publication Date |
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| TWI719815B true TWI719815B (en) | 2021-02-21 |
| TW202129616A TW202129616A (en) | 2021-08-01 |
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| TW109102491A TWI719815B (en) | 2020-01-22 | 2020-01-22 | Driving circuit for pixel |
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| TW (1) | TWI719815B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114399974A (en) * | 2021-09-28 | 2022-04-26 | 友达光电股份有限公司 | Display panel and operation method thereof |
| CN114708827A (en) * | 2022-04-27 | 2022-07-05 | Tcl华星光电技术有限公司 | Driving circuit, display panel and driving method thereof |
| EP4390905A1 (en) * | 2022-12-23 | 2024-06-26 | Samsung Display Co., Ltd. | Display device and tiled display device |
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| KR101588044B1 (en) * | 2005-12-20 | 2016-01-25 | 코닌클리케 필립스 엔.브이. | Method and apparatus for controlling current supplied to electronic devices |
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| CN114399974A (en) * | 2021-09-28 | 2022-04-26 | 友达光电股份有限公司 | Display panel and operation method thereof |
| TWI786853B (en) * | 2021-09-28 | 2022-12-11 | 友達光電股份有限公司 | Display panel and operation method thereof |
| CN114399974B (en) * | 2021-09-28 | 2023-12-12 | 友达光电股份有限公司 | Display panel and operation method thereof |
| CN114708827A (en) * | 2022-04-27 | 2022-07-05 | Tcl华星光电技术有限公司 | Driving circuit, display panel and driving method thereof |
| EP4390905A1 (en) * | 2022-12-23 | 2024-06-26 | Samsung Display Co., Ltd. | Display device and tiled display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202129616A (en) | 2021-08-01 |
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