TWI799055B - Pixel circuit, display panel and driving method thereof - Google Patents

Abstract

A pixel circuit includes a pulse width modulation (PWM) control circuit for performing PWM control and PWM inter-compensation gray scale writing; a sweep coupling circuit coupled to the PWM control for capacitively coupling a global sweep signal into the pixel circuit; a pulse amplitude modulation (PAM) control circuit coupled to the PWM control circuit for performing PAM control and PAM inter-compensation gray scale writing; and a light emitting diode (LED) coupled to the PAM control circuit, controlled by the PAM control circuit to emit or stop emitting, the PAM control circuit performing PAM control on the LED to control a current flowing the LED.

Description

Pixel circuit, its display panel and its driving method

The invention relates to a pixel circuit, its display panel and its driving method.

Liquid crystal display (LCD) has low radiation, low power, etc., and has become the mainstream of current displays. The LCD panel includes a plurality of pixel circuits. In each pixel circuit, the pulse width modulation (PWM, pulse width modulation) mode has better color shift (color shift) and relatively better power consumption than pulse amplitude modulation (PAM, pulse amplitude modulation) .

Currently, it is very difficult to implement the pixel circuit with PWM control function in the active region. The main challenge is that it is easy to cause uneven near and far ends, resulting in uneven brightness of low-gray-scale displays. (Mura) is more serious.

In addition, if the control signal uses a gate on array (GOA) to control light emission, normal errors will cause uneven brightness of the 6H line display.

In addition, serious crosstalk (crosstalk) may also occur when writing signals are filled in or when light is emitted.

Therefore, this case proposes a pixel circuit, its display panel and its driving method in order to solve the above or other conventional problems.

According to an embodiment of the present case, a pixel circuit is proposed, including: a pulse width modulation (PWM) control circuit for performing PWM control, and performing PWM internal compensation gray scale writing; a scanning coupling circuit coupled to the A pulse width modulation control circuit is used to capacitively couple an overall scanning signal to the pixel circuit; a pulse amplitude modulation (PAM) control circuit is coupled to the pulse width modulation control circuit for PAM control , and perform PAM internal supplementary grayscale writing; and a light-emitting diode, coupled to the pulse amplitude modulation control circuit, controlled by the pulse amplitude modulation control circuit to emit light or stop emitting light, the pulse amplitude modulation The control circuit performs PAM control on the light-emitting diode to control a current flowing through the light-emitting diode.

According to another embodiment of the present case, a driving method of a pixel circuit is proposed, including: performing a pulse amplitude modulation (PAM) controlled initial and PAM internal gray scale writing in a first operation stage; In the second operation stage, the initial pulse width modulation (PWM) control and PWM inter-complement grayscale writing are performed; and in a third operation stage, the light emission reset is performed before emitting light.

According to another embodiment of the present case, a display panel is proposed, including: an active array including a plurality of pixel circuits; and a driving circuit coupled to and driving the active array; wherein each of the pixel circuits includes: a pulse Width modulation (PWM) control circuit, used for PWM control, and PWM internal supplementary grayscale writing; a scanning coupling circuit, coupled to the pulse width modulation control circuit, for An overall scanning signal is capacitively coupled to the pixel circuit; a pulse amplitude modulation (PAM) control circuit is coupled to the pulse width modulation control circuit for PAM control and PAM internal gray scale writing input; and a light-emitting diode, coupled to the pulse amplitude modulation control circuit, controlled by the pulse amplitude modulation control circuit to emit light or stop emitting light, and the pulse amplitude modulation control circuit controls the light-emitting diode PAM control to control a current flowing through the LED.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

100, 200, 300: pixel circuit

110, 210, 310: pulse width modulation control circuit

120, 220, 320: scanning coupling circuit

130, 230, 330: pulse amplitude modulation control circuit

D: light emitting diode

340: Luminous reset circuit

T11~T15, T21~T26, T31~T46: Transistor

C11~C34: capacitance

600: display panel

610: active array

620: drive circuit

710~730: Steps

FIG. 1A and FIG. 1B show the circuit structure diagram of the pixel circuit according to the first embodiment of the present invention.

FIG. 2A and FIG. 2B show the circuit structure diagram of the pixel circuit according to the second embodiment of the present application.

FIG. 3 shows a circuit structure diagram of a pixel circuit according to a third embodiment of the present invention.

FIG. 4A and FIG. 4B show the operation diagrams of the first operation stage and the second operation stage according to the third embodiment of the present application.

FIG. 5A and FIG. 5B show a schematic diagram of the operation of the third operation stage according to the third embodiment of the present application.

FIG. 6 shows a functional block diagram of a display panel according to a fourth embodiment of the present application.

FIG. 7 shows a flowchart of a pixel circuit driving method according to a fifth embodiment of the present invention.

The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations or definitions of these terms shall prevail. Each embodiment of the disclosure has one or more technical features. On the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1A and FIG. 1B show the circuit structure diagram of the pixel circuit according to the first embodiment of the present invention. As shown in FIG. 1A and FIG. 1B, the pixel circuit 100 according to the first embodiment of the present invention includes: a pulse width modulation (PWM) control circuit 110, a sweep coupling circuit (sweep coupling circuit) 120, a pulse amplitude modulation ( PAM) control circuit 130 and light emitting diode D. The LED D is coupled between the PWM control circuit 130 and the ground terminal VSS. The light emitting diode D is controlled by the pulse amplitude modulation control circuit 130 to emit light or stop emitting light.

The pulse width modulation control circuit 110 is used for PWM control. The pulse width modulation control circuit 110 includes: transistors T11 - T14 and a first capacitor C11 .

The transistor T11 includes: a first terminal (such as but not limited to a source) receiving an initial control signal VST (also referred to as a first initial control signal); a second terminal (such as but not limited to a drain ) is coupled to the first internal node W; and a control terminal (such as but not limited to a gate) receives the initial control signal VST.

Transistor T12 includes: a first end (for example but not limited to source) Receive the grayscale signal Sig (the first grayscale signal); a second terminal (such as but not limited to drain) coupled to the transistor T14; and a control terminal (such as but not limited to gate) The control signal SPWM[n] (also called the first control signal) is received.

The transistor T13 includes: a first terminal (such as but not limited to a source) coupled to the internal node W; a second terminal (such as but not limited to a drain) coupled to the transistor T14; and a The control terminal (such as but not limited to gate) receives the control signal SPWM[n].

The transistor T14 includes: a first terminal (such as but not limited to source) receiving the operating voltage VDD_PWM (also referred to as the first operating voltage); a second terminal (such as but not limited to drain) coupled connected to the transistor T13 and the pulse amplitude modulation control circuit 130 ; and a control terminal (such as but not limited to a gate) coupled to the internal node W.

The first capacitor C11 is coupled between the internal node W and the internal node P (also referred to as a second internal node).

The scan coupling circuit 120 is coupled to the PWM control circuit 110 for coupling the global sweep signal GS to the pixel circuit 100 . The scan coupling circuit 120 includes a transistor T15 and a second capacitor C12.

Transistor T15 includes: a first terminal (for example, but not limited to source) receiving voltage SVGH (also referred to as a first reference voltage); a second terminal (for example but not limited to drain) coupled to the internal node P; and a control terminal (such as but not limited to a gate) for receiving the scan enable signal SEN[n].

The second capacitor C12 is coupled to the internal node P and the overall scan signal Between GS.

The PWM control circuit 130 is coupled to the PWM control circuit 110 and the light emitting diode D. As shown in FIG. The pulse amplitude modulation control circuit 130 is used for performing PAM control on the light-emitting diode D, so as to control the magnitude of the current flowing through the light-emitting diode D. As shown in FIG.

Please refer to Figure 1A and Figure 1B again. Before starting the operation, perform the initialization operation first. During the initialization operation, the initial control signal VST is logic low to turn on the transistor T11 , so that the voltage of the internal node W drops to logic low, and then turns on the transistor T14 .

Afterwards, when it is desired to write the grayscale signal Sig, the control signal SPWM[n] is logic low to turn on the transistors T12 and T13 .

Since the transistors T12 , T13 and T14 are turned on, the grayscale signal Sig can be written into the pulse amplitude modulation control circuit 130 . What's more, the grayscale signal Sig can be written into the internal node W through the transistors T12 , T13 and T14 to perform internal compensation (internal supplementary grayscale writing).

When the grayscale signal Sig is written into the internal node W, the transistor T14 is turned off.

After the grayscale signal Sig is written, if light is to be emitted, the overall scan signal GS starts to fall at timing T1 (at the same time, the scan enable signal SEN[n] turns logic high to turn off the transistor T15). When the transistor T15 is turned off, the potential of the internal node P is no longer controlled by the voltage SVGH.

As the overall scan signal GS decreases, the voltages of the internal nodes P and W also decrease accordingly. When the voltage at internal node W drops below the transistor When the critical voltage of body T14 is reached, the transistor T14 is turned on, so that the operating voltage VDD_PWM turns off the light-emitting path of the pulse amplitude modulation control circuit 130 , and then turns off the light-emitting diode D.

In FIG. 1A and FIG. 1B , the scan enable signal SEN[n] is used for scan enable control instead of the conventional control method, so that the desired output slope can be freely obtained.

Therefore, in the first embodiment of the present application, in combination with the scan enable signal SEN[n], a progressive light-emitting scan waveform can be effectively generated.

FIG. 2A and FIG. 2B show the circuit structure diagram of the pixel circuit according to the second embodiment of the present application. As shown in FIG. 2A and FIG. 2B, the pixel circuit 200 according to the second embodiment of the present case includes: a pulse width modulation control circuit 210, a scanning coupling circuit 220, a pulse amplitude modulation control circuit 230 and a light-emitting diode D .

Basically, the pulse width modulation control circuit 210 and the pulse amplitude modulation control circuit 230 are the same as or similar to the pulse width modulation control circuit 110 and the pulse amplitude modulation control circuit 130 in Fig. 1A and Fig. 1B, so the details are in This is omitted.

The PWM control circuit 210 includes transistors T21 - T24 and a capacitor C21 .

The scanning coupling circuit 220 includes transistors T25 and T26, and a capacitor C22. Transistor T25 is the same as transistor T15 in FIG. 1A, so its details are omitted here.

Transistor T26 includes: a first end (for example, but not limited to source) receiving the overall scan signal GS; a second end (for example but not limited to drain) coupled to the capacitor C22; and a control terminal (such as but not limited to a gate) for receiving a control signal PCT[n] (which may be referred to as a second control signal).

The capacitor C22 is coupled between the internal node P and the transistor T26.

Please refer to Figure 2A and Figure 2B again. When the scan enable signal SEN[n] turns to logic high, the control signal PCT[n] turns to logic low synchronously to turn on the transistor T26 so that the overall scan signal GS can be coupled to the inside of the pixel circuit 200 .

That is, as shown in FIG. 2A and FIG. 2B, when there is an output (to make the light-emitting diode D emit light), the control signal PCT[n] is synchronously turned to logic low to turn on the transistor T26, but the overall scanning The signal GS is also pulled by the capacitor C21; when there is no output (so that the light-emitting diode D does not emit light), the control signal PCT[n] turns to logic high to turn off the transistor T26, so that the overall scanning signal GS cannot be coupled to the picture The interior of the element circuit 200, that is to reduce the load force of the capacitor C21 on the overall scan signal GS.

In FIG. 2A and FIG. 2B , the control signal PCT[n] can reduce the load force of the capacitor C21 on the overall scan signal GS when there is no output.

FIG. 3 shows a circuit structure diagram of a pixel circuit according to a third embodiment of the present invention. As shown in Figure 3, the pixel circuit 300 according to the third embodiment of the present case includes: a pulse width modulation control circuit 310, a scan coupling circuit 320, a pulse amplitude modulation control circuit 330, a light emission reset circuit 340, and a transistor T46 with LED D.

The PWM control circuit 310 includes transistors T31 - T36 and a capacitor C31 . Basically, the transistors T31~T34 of the pulse width modulation control circuit 310 and the capacitor C31 are the same as or similar to the pulse width in Fig. 1A or Fig. 2A T11~T14 (or T21~T24) and capacitor C11 (or C21) of the control circuit 110 (or 210) are modulated, so details thereof are omitted here.

The transistor T35 includes: a first terminal (such as but not limited to a source) coupled to the transistor T34; a second terminal (such as but not limited to a drain) coupled to the light-emitting reset circuit 340; And a control terminal (such as but not limited to gate) receives the control signal EPWM[n] (the third control signal).

The transistor T36 includes: a first terminal (such as but not limited to a source) coupled to the operating voltage VDD_PWM; a second terminal (such as but not limited to a drain) coupled to the transistor T34; and a The control terminal (such as but not limited to gate) receives the control signal EPWM[n].

The scan coupling circuit 320 includes a transistor T37 and a capacitor C32. The scanning coupling circuit 320 is basically the same or similar to the scanning coupling circuit 120 (or 220 ) in FIG. 1A or FIG. 2A , so its details are omitted here.

The pulse amplitude modulation control circuit 330 includes: transistors T38 - T42 and a capacitor C33 .

The transistor T38 includes: a first terminal (for example, but not limited to a source) for receiving an initial signal VST_PAM (also referred to as a second initial control signal); a second terminal (for example, but not limited to a drain) coupled to the transistor T40; and a control terminal (such as but not limited to a gate) for receiving the initial control signal VST_PAM.

The transistor T39 includes: a first end (for example, but not limited to a source) for receiving the grayscale signal VPAM_R/G/B (second grayscale signal); a second end (for example, but not limited to a drain ) is coupled to the transistor T41; and a control terminal (such as but not subject to limited to the gate) to receive the control signal SPAM[n] (also referred to as the fourth control signal).

The transistor T40 includes: a first end (such as but not limited to a source) coupled to the transistor T38; a second end (such as but not limited to a drain) coupled to the transistor T41; and a The control terminal (such as but not limited to gate) receives the control signal SPAM[n].

The transistor T41 includes: a first terminal (such as but not limited to a source) coupled to the transistor T42; a second terminal (such as but not limited to a drain) coupled to the light-emitting reset circuit 340; And a control terminal (such as but not limited to a gate) is coupled to the transistor T38.

The transistor T42 includes: a first terminal (such as but not limited to source) receiving the operating voltage VDD_PAM (also referred to as the second operating voltage); a second terminal (such as but not limited to drain) coupled connected to the transistor T41; and a control terminal (such as but not limited to gate) receiving the control signal EPWM[n].

The capacitor C33 is coupled between the operating voltage VDD_PAM and the transistor T38.

The light reset circuit 340 includes: transistors T43 - T45 and a capacitor C34 .

Transistor T43 includes: a first end (for example, but not limited to source) receiving the set voltage Vset; a second end (for example, but not limited to drain) coupled to PWM control circuit 310; and a control A terminal (such as but not limited to a gate) receives the set signal SET[n].

Transistor T44 includes: a first terminal (such as but not limited to source) coupled to transistor T45; a second terminal (such as but not limited to drain) coupled to pulse an amplitude modulation control circuit 330 ; and a control terminal (such as but not limited to a gate) coupled to the PWM control circuit 310 .

The transistor T45 includes: a first terminal (such as but not limited to a source) coupled to the light-emitting diode D; a second terminal (such as but not limited to a drain) coupled to the transistor T44; And a control terminal (such as but not limited to a gate) receives the signal EPAM[n] (also referred to as the fifth control signal).

The capacitor C34 is coupled between the setting voltage Vset and the control terminal of the transistor T44.

Transistor T46 includes: a first end (such as but not limited to the source) coupled to the anode of the light-emitting diode D; a second end (such as but not limited to the drain) coupled to the light-emitting diode D a cathode of the pole body D; and a control terminal (such as but not limited to a gate) for receiving a test signal TEST. When the light-emitting diode D is to be tested, the test signal TEST is logic low to turn on the transistor T46 so that current flows through the light-emitting diode D. In this way, it can be tested whether the light-emitting diode D can emit light normally.

In the third embodiment of the present application, the pixel circuit 300 has three operation stages: S1, S2 and S3. In the first operation stage S1, the initial and PAM interpolation grayscale writing of the PWM control circuit 330 is performed. In the second operation stage S2, the PWM control circuit 310 performs initial and PWM in-fill gray scale writing. In the third operation stage S3 (light-emitting stage), light-emitting reset is performed and then light is emitted.

FIG. 4A and FIG. 4B show the operation diagrams of the first operation stage and the second operation stage according to the third embodiment of the present application. FIG. 5A and FIG. 5B show a schematic diagram of the operation of the third operation stage according to the third embodiment of the present application.

As shown in Figure 4A and Figure 4B, the first operation stage S1 includes two sub-operation stages S1-1 and S1-2; and the second operation stage S2 includes two sub-operation stages S2-1 and S2-2 .

In the sub-operation stage S1-1, the initial operation of the PWM control circuit 330 is performed. In the sub-operation phase S1-1, the initial signal VST_PAM is reduced to logic low, so that the transistor T38 is turned on, and the transistor T41 is also turned on.

In the sub-operation stage S1-2, PAM inter-filling grayscale writing is performed. In the sub-operation stage S1-2, the signal SPAM drops to a logic low, so that the transistors T39 and T40 are turned on, so the grayscale signal VPAM_R/G/B is written into the internal node W'.

In the second operation stage S2, the PWM control circuit 310 performs initial and PWM in-fill gray scale writing. In the sub-operation phase S2-1, the initial signal VST is reduced to logic low, so that the transistor T31 is turned on, and the transistor T34 is also turned on.

In the sub-operation stage S2-2, PWM inter-compensation grayscale writing is performed. In the sub-operation stage S2 - 2 , the signal SPWM[n] drops to logic low, so that the transistors T32 and T33 are turned on, so the grayscale signal Sig is written into the internal node W.

As shown in FIG. 5A and FIG. 5B , the third operation stage S3 includes four sub-operation stages S3 - 1 -S3 - 4 . In the third operation stage S3, the light is reset and the light is turned on again.

In the sub-operation stage S3-1, the control signal SET[n] is reduced to logic The logic is low, so that the transistor T43 is turned on, and the voltage of the internal node C is dropped to the set voltage Vset (for example, but not limited to -3V), and the transistor T44 is turned on by default (in normally white (normally white) )in the case of).

In the sub-operation stage S3-2, EPWM[n] drops to logic low to start the PWM control circuit 310 to control the gate voltage of the transistor T34 to control the timing of the operation voltage VDD_PWM input to the transistor T44.

In the sub-operation stage S3-3, when EPAM[n] is logic low, the transistor T45 is turned on to form the light-emitting path of the LED D (transistors T42, T41, T44 and T45 are all turned on).

In the sub-operation stage S3-4, when the overall scan signal GS falls, the voltage of the transistor T34 will also drop (for example, linearly) to the corresponding grayscale voltage, so that the operating voltage VDD_PWM can turn off the transistor. T44, to achieve turning off the light-emitting diode D.

In the third embodiment of the present application, like the first embodiment, by integrating the scanning coupling circuit 320 in the pixel circuit 300 , the driving can be made more complete.

In addition, the scanning coupling circuit 320 of the third embodiment can also be the same as the scanning coupling circuit 220 of the second embodiment, which is also within the spirit of the present application.

FIG. 6 shows a functional block diagram of a display panel according to a fourth embodiment of the present application. As shown in FIG. 6 , the display panel 600 according to the fourth embodiment of the present application includes an active array 610 and a driving circuit 620 . The active array 610 includes a plurality of pixel circuits (such as the pixel circuits 100, 200 or 300). The driving circuit 620 is coupled to and drives the active array 610 . The structure and operation of the driving circuit 620 are not particularly limited here.

FIG. 7 shows a flowchart of a pixel circuit driving method according to a fifth embodiment of the present invention. The pixel circuit driving method according to the fifth embodiment of the present case includes: in a first operation phase, performing a pulse amplitude modulation (PAM) controlled initial and PAM internal gray scale writing (710); In the operation phase, perform initial pulse width modulation (PWM) control and PWM inter-complement grayscale writing (720); and in a third operation phase, perform light emission reset and then emit light (730).

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

710-730: Steps

Claims (9)

A pixel circuit, comprising: a pulse width modulation (PWM) control circuit, used for PWM control, and PWM internal complement gray scale writing; a scanning coupling circuit, coupled to the pulse width modulation control circuit, Capacitively coupling an overall scan signal to the pulse width modulation control circuit, the scan coupling circuit includes at least one capacitor; a pulse amplitude modulation (PAM) control circuit coupled to the pulse width modulation control circuit, Used for PAM control and PAM internal supplementary grayscale writing; and a light emitting diode, coupled to the pulse amplitude modulation control circuit, controlled by the pulse amplitude modulation control circuit to emit light or stop emitting light, The pulse amplitude modulation control circuit performs PAM control on the light-emitting diode to control a current flowing through the light-emitting diode. The pixel circuit as described in Claim 1, wherein the pulse width modulation control circuit includes: a first transistor to a fourth transistor, and a first capacitor; the scanning coupling circuit includes a fifth transistor and a second capacitor; wherein, the first transistor includes: a first terminal receiving a first initial control signal; a second terminal coupled to a first internal node; and a control terminal receiving the first initial control signal Signal; The second transistor includes: a first terminal for receiving a first grayscale signal; a second terminal coupled to the fourth transistor; and a control terminal for receiving a first control signal; the third transistor includes: A first terminal is coupled to the first internal node; a second terminal is coupled to the fourth transistor; and a control terminal receives the first control signal; the fourth transistor includes: a first terminal receives a a first operating voltage; a second terminal coupled to the third transistor; and a control terminal coupled to the first internal node; the first capacitor coupled to the first internal node and a second internal node between; the fifth transistor includes: a first terminal receiving a first reference voltage; a second terminal coupled to the second internal node; and a control terminal receiving a scan enable signal; and the second capacitor coupled between the second internal node and the overall scan signal. The pixel circuit as described in claim item 2, wherein the scan coupling circuit further includes a sixth transistor, and the sixth transistor includes: a first end receiving the overall scan signal; a second end coupled to the a second capacitor; and a control terminal receiving a second control signal, when the scanning enabling signal transitions, the second control signal synchronously transitions to turn on the sixth transistor, so that the overall scanning signal is coupled to the picture element circuit. The pixel circuit according to claim 2, wherein, during the initialization operation, the first initial control signal turns on the first transistor, so that the voltage of the first internal node drops and turns on the fourth transistor; When the first grayscale signal is written, the first control signal turns on the second transistor and the third transistor; in response to the second, third and fourth transistors being turned on, the grayscale The signal is written into the pulse amplitude modulation control circuit; the first grayscale signal is written into the first internal node through the second, the third and the fourth transistors for internal compensation; when the second When a grayscale signal is written into the first internal node, the fourth transistor is turned off; after the first grayscale signal is written, when light is to be emitted, the overall scan signal starts to drop and at the same time, the scan The enable signal turns off the fifth transistor; as the overall scan signal drops, the voltages of the first internal node and the second internal node drop; in response to a voltage drop of the first internal node, the fourth transistor The crystal is turned on, so that the first operating voltage turns off a light-emitting path of the pulse amplitude modulation control circuit, and then turns off the light-emitting diode. The pixel circuit as described in claim 1, wherein the pixel circuit further includes a lighting reset circuit, and the pulse width modulation control circuit includes: a first transistor to a sixth transistor, and a first Capacitor; the scanning coupling circuit includes a seventh transistor and a second capacitor; the pulse amplitude modulation control circuit includes: an eighth transistor to a twelfth transistor and a third capacitor; and The light-emitting reset circuit includes: a thirteenth transistor to a fifteenth transistor, and a fourth capacitor, wherein the first transistor includes: a first terminal receiving a first initial control signal; a first transistor Two terminals are coupled to a first internal node; and a control terminal receives the first initial control signal; the second transistor includes: a first terminal receives a first first grayscale signal; a second terminal is coupled to the fourth transistor; and a control terminal to receive a first control signal; the third transistor includes: a first terminal coupled to the first internal node; a second terminal coupled to the fourth transistor and a control terminal receiving the first control signal; the fourth transistor includes: a first terminal coupled to the sixth transistor; a second terminal coupled to the first transistor; and a control terminal coupled connected to the first transistor; the fifth transistor includes: a first terminal coupled to the fourth transistor; a second terminal coupled to the light reset circuit; and a control terminal receiving a third control signal; the sixth transistor includes: a first terminal receiving a first operating voltage; a second terminal coupled to the fourth transistor; and a control terminal receiving the third control signal; the first capacitor, coupled connected between the first internal node and a second internal node; The seventh transistor includes: a first terminal receiving a first reference voltage; a second terminal coupled to the second internal node; and a control terminal receiving a scan enable signal; and the second capacitor coupled to Between the second internal node and the overall scan signal; the eighth transistor includes: a first terminal receiving a second initial signal; a second terminal coupled to the tenth transistor; and a control terminal receiving the The second initial signal; the ninth transistor includes: a first terminal receiving a second grayscale signal; a second terminal coupled to the eleventh transistor; and a control terminal receiving a fourth control signal; the The tenth transistor includes: a first terminal coupled to the eighth transistor; a second terminal coupled to the eleventh transistor; and a control terminal receiving the fourth control signal; the eleventh transistor It includes: a first terminal coupled to the twelfth transistor; a second terminal coupled to the light reset circuit; and a control terminal coupled to the eighth transistor; the twelfth transistor includes: A first terminal receives a second operating voltage; a second terminal is coupled to the eleventh transistor; and a control terminal receives the third control signal; the third capacitor is coupled between the second operating voltage and the Between the eighth transistor; the thirteenth transistor includes: a first terminal receiving a setting voltage; a second terminal coupled to the PWM control circuit; and a control terminal receiving a setting signal; The fourteenth transistor includes: a first terminal coupled to the fifteenth transistor; a second terminal coupled to the pulse amplitude modulation control circuit; and a control terminal coupled to the PWM control circuit; the The fifteenth transistor includes: a first terminal coupled to the light-emitting diode; a second terminal coupled to the fourteenth transistor; and a control terminal receiving a fifth control signal; and the fourth capacitor coupled between the setting voltage and the control terminal of the fourteenth transistor. The pixel circuit as described in claim 5, wherein, in a first operation stage, the initial and PAM internal grayscale writing of the pulse amplitude modulation control circuit is performed; in a second operation stage, the The initial and PWM internal complement gray scale writing of the PWM control circuit; and in a third operation phase, reset the light and then emit light. A driving method for a pixel circuit, comprising: in a first operation stage, performing a pulse amplitude modulation (PAM) controlled initial and PAM internal gray scale writing; in a second operation stage, performing pulse width Modulation (PWM) controlled initial and PWM inter-complement grayscale writing, wherein an overall scan signal is capacitively coupled to the pixel circuit through a scan coupling circuit including at least one capacitor; and in a third operation stage Inside, perform a light reset and then light again. A display panel, comprising: An active array, including a plurality of pixel circuits; and a driving circuit, coupled and driving the active array; wherein, each of the pixel circuits includes: a pulse width modulation (PWM) control circuit for PWM control , and perform PWM internal supplementary grayscale writing; a scan coupling circuit, coupled to the pulse width modulation control circuit, for capacitively coupling an overall scan signal to the pulse width modulation control circuit, the scan coupling circuit Including at least one capacitor; a pulse amplitude modulation (PAM) control circuit coupled to the pulse width modulation control circuit for PAM control and PAM internal gray scale writing; and a light emitting diode, Coupled to the pulse amplitude modulation control circuit, controlled by the pulse amplitude modulation control circuit to emit light or stop emitting light, the pulse amplitude modulation control circuit performs PAM control on the light emitting diode to control the flow of light through the light emitting diode A current in a diode. The display panel as described in Claim 8, wherein, in a first operation stage, the initial and PAM internal grayscale writing of the pulse amplitude modulation control circuit is performed; in a second operation stage, the PWM The initial and PWM inter-complement grayscale writing of the control circuit; and in a third operation stage, reset the light and then emit light.

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