TWI758014B - 用於直接晶片附接之具有毛細流動結構的半導體晶粒 - Google Patents

用於直接晶片附接之具有毛細流動結構的半導體晶粒 Download PDF

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TWI758014B
TWI758014B TW109144389A TW109144389A TWI758014B TW I758014 B TWI758014 B TW I758014B TW 109144389 A TW109144389 A TW 109144389A TW 109144389 A TW109144389 A TW 109144389A TW I758014 B TWI758014 B TW I758014B
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capillary flow
substrate
channel
semiconductor device
semiconductor die
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TW109144389A
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TW202131449A (zh
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李仲培
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美商美光科技公司
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本文提供一種具有用於一直接晶片附接之一毛細流動結構之半導體裝置。該半導體裝置通常包括一基板及具有電耦接至該基板之一導電支柱之一半導體晶粒。該半導體晶粒之前側可與該基板間隔開一定距離，從而形成一間隙。該半導體裝置進一步包括自該半導體晶粒之該前側突出之第一及第二細長毛細流動結構，該等第一及第二細長毛細流動結構至少部分地朝向該基板延伸。該等第一及第二細長毛細流動結構可以一第一寬度彼此間隔開，該第一寬度經組態以引起一底部填充材料沿著該等第一及第二細長毛細流動結構之一長度進行毛細流動。該等第一及第二毛細流動結構可包括在其間形成通道以引起一增加流速之毛細流動的成對細長毛細流動結構。

Description

用於直接晶片附接之具有毛細流動結構的半導體晶粒
本發明大體上係關於半導體裝置，及在若干實施例中係關於具有用於直接晶片附接之毛細流動增強結構之半導體晶粒。
諸如記憶體裝置、微處理器及發光二極體之微電子裝置通常包括安裝至基板中及圍封在保護層中之一或多個半導體晶粒。半導體晶粒包括諸如記憶體單元、處理器電路、互連電路系統等之功能特徵。在直接晶片附接(DCA)技術中，移除習知的裝置封裝。一些直接晶片附接技術包括板面晶片(COB)組態，其中半導體晶粒直接安裝至基板及電互連至基板，該基板例如，印刷電路板(PCB)、陶瓷基板或玻璃陶瓷基板等等。半導體晶粒藉由晶粒至基板(D2S)連接電耦接至基板，該連接可包括具有結合襯墊之晶粒，該等結合襯墊具有經組態以安裝至上下倒轉之基板之支柱及/或焊料凸塊，其中晶粒之前側面向基板(例如，覆晶)。當覆晶用於COB組態時，半導體晶粒可能會進行底部填充以防止主動表面及凸塊受到熱機械及化學損壞，及減小可能會導致由基板及半導體晶粒之不匹配熱膨脹引起的損壞之剪應力。半導體晶粒使用非導電黏合底部填充材料接合至基板。
圖1A展示習知的覆晶半導體裝置10，其包括晶粒12及一或多個互連結構，例如具有焊料凸塊22之D2S支柱20。圖1B展示在已將其翻轉之後，使得D2S支柱20及焊料凸塊22與基板50介接以形成D2S電連接之半導體裝置10。基板50與晶粒12之間的間隙使用施加至間隙邊緣之非導電黏合劑進行底部填充。在許多應用中，毛細底部填充(CUF)動作藉由間隙產生底部填充材料流40，使得流40通常在基板50與晶粒12之間均勻。CUF流40之流速通常限制COB製造製程之產量。
本發明之實施例可係關於一種用於直接晶片附接之半導體裝置。該半導體裝置可包含：基板；半導體晶粒；及毛細流動結構。該半導體晶粒可具有自前側延伸之導電支柱。該半導體晶粒可藉由該導電支柱電耦接至該基板。該半導體晶粒之該前側可與該基板間隔開一間隙。該毛細流動結構可具有自該前側朝向該基板突出之第一及第二細長流動元件。該等第一及第二細長流動元件可彼此橫向間隔開第一寬度，該第一寬度經組態以引起底部填充材料沿著該等第一及第二細長流動元件的長度進行毛細流動。
本發明之另一實施例可係關於一種用於直接晶片附接之半導體裝置。該半導體裝置可包含：基板；半導體晶粒；及第一及第二毛細流動結構。該半導體晶粒可具有自前側延伸之導電支柱，該半導體晶粒藉由該導電支柱電耦接至該基板。該半導體晶粒之該前側與該基板間隔開一間隙。該等第一及第二毛細流動結構中之每一者可具有自該前側朝向該基板突出之第一及第二細長流動元件。該等第一及第二毛細流動結構可彼此橫向間隔開第一寬度，該第一寬度經組態以引起底部填充材料在該等第一及第二毛細流動結構之間進行毛細流動。
本文揭示之技術係關於半導體裝置、具有半導體裝置之系統，及用於製造半導體裝置之相關方法。術語「半導體裝置」一般指包括一或多個半導體材料之固態裝置。半導體裝置之實例包括邏輯裝置、記憶體裝置及二極體等等。此外，術語「半導體裝置」可指成品裝置或變成成品裝置之前的各個處理階段時之總成或其他結構。
取決於使用的上下文，術語「基板」可指支撐電子組件(例如，晶粒)之結構，諸如晶圓級基板或切單之晶粒級基板。術語「基板」亦可表示用於晶粒堆疊應用之另一晶粒。一般熟習相關技術者應認識到，可在晶圓級或在晶粒級執行本文所描述之方法之合適態樣。此外，除非上下文另有指示，否則可使用習知的半導體製造技術來形成本文中所揭示之結構。舉例而言，材料可使用化學氣相沈積、物理氣相沈積、原子層沈積、旋塗、電鍍及/或其他合適的技術沈積。類似地，舉例而言，材料可使用電漿蝕刻、濕式蝕刻、化學-機械平坦化，或其他合適的技術移除。
本發明技術包括經組態以增強毛細作用以在直接晶片附接處理期間增加底部填充材料之流速之結構。本發明技術之毛細流動結構可在晶粒之前側上或在基板之介接表面上，及其經組態以與不含毛細流動結構之習知總成相比，藉由間隙增加底部填充材料之流速。
毛細流動結構可藉由以下方式形成於半導體晶粒之表面或基板之表面上：(a)藉由光阻劑材料或硬式光罩之開口來電鍍毛細流動結構之圖案；(b)將預成型之毛細結構附接至表面；(c)將材料沈積至基板表面之凸起部分上；及其他合適的技術。儘管所說明之毛細流動結構被示為具有延伸半導體晶粒(圖2A)之大部分長度的長度，但是在其他實施例中，毛細流動結構之長度更短。在一些實施例中，可沿著半導體晶粒之長度使用多個毛細流動結構。所說明之毛細流動結構可具有通常對應於在底部填充期間接觸半導體晶粒及基板之組件之間的間隙距離之高度，或其可部分地在半導體晶粒與基板之間延伸。在此等實施例中，毛細流動結構可適當地延伸組件之間的間隙距離之大於20%、大於40%、大於60%、大於80%，或大於90%。
圖2A展示處於前側向上組態之半導體裝置110a。半導體裝置110a包括半導體晶粒112及自半導體晶粒112之前側111延伸之支柱120。支柱120可包括在每個支柱120之遠端處之焊料凸塊122，其經組態以藉由焊料凸塊122之回焊將半導體晶粒112電耦接至基板。支柱可由例如銅(Cu)之合適導電材料形成，及具有焊料蓋以形成電連接(例如，錫-銀(SnAg)焊料蓋)。在組裝期間，使用聯合回焊、聲波回焊，或其他技術回焊焊料蓋。可使用光罩處理技術形成支柱。形成支柱之結合襯墊通常為銅，因此銅柱使用銅至銅接合技術耦接至結合襯墊。在其他實施例中，支柱可由與結合襯墊不同的材料形成，或支柱可由材料組合形成。
在一些實施例中，半導體裝置110a亦包括在半導體晶粒112之前側111處之毛細流動結構130。個別毛細流動結構130可包括自半導體晶粒112之前側111以高度H突出之第一流動元件131及第二流動元件132。第一流動元件131及第二流動元件132可具有厚度T及長度L。可基於以下項調整高度H、厚度T及長度L：(a)半導體晶粒112之組態，(b)支柱120之高度及間隔，(c)半導體裝置110a與基板之間的所需間隙，(d)毛細流動結構製造製程能力，及/或(e)所需底部填充材料流速，以及其他考慮因素。
每個毛細流動結構130之第一流動元件131及第二流動元件132可間隔開第一距離W1，使得兩個相鄰之毛細流動結構130不會跨越任何支柱120。毛細流動結構130可彼此間隔開第二距離W2，使得兩個相鄰的毛細流動結構130位於至少一個支柱120之相對二側上。在許多應用中，第一距離W1可小於第二距離W2。相對距離W1及W2為晶粒上可用的佔據面積、支柱120之配置及增強特定底部填充材料之毛細作用的距離之函數。舉例而言，由於流體之毛細流速通常與流體流過之通道的有效面積之大小成反比地增加，因此寬度W1及W2可經組態以與不具有毛細流動結構130之裝置相比增加底部填充材料之流速。可根據本發明技術之實施例使用任何數目之毛細流動結構130。
第一流動元件131及第二流動元件132可由用該類型之底部填充材料充分「浸潤」之材料製成。在許多應用中，第一流動元件131及第二流動元件132可包括金屬或金屬合金，諸如銅或鋁。在此類應用中，第一流動元件131及第二流動元件132可與半導體晶粒112之導電電路系統電隔離。第一流動元件131及第二流動元件132可替代地包括矽、玻璃，或具有平滑表面之其他材料，該平滑表面與底部填充材料良好地介接以增加毛細力。第一流動元件131及第二流動元件132可為用底部填充材料充分浸潤之固體金屬、陶瓷或聚合物材料，或該等元件可具有芯及塗覆有用底部填充材料充分浸潤之材料。
圖2B示出直接晶片附接總成100a，該直接晶片附接總成具有倒置的圖2A之半導體裝置110a，使得焊料凸塊122與基板150上之觸點(未展示)介接。在此組態中，支柱120及焊料凸塊122電連接至基板150，及毛細流動結構130處於基板150與半導體晶粒112之間的間隙中。在操作中，取決於毛細流動結構130之幾何形狀及沿著半導體晶粒112施加底部填充材料之位置，在半導體晶粒112與基板150之間的間隙中施加在半導體晶粒112之周邊處的底部填充材料將以不同速率流動。
垂直於長度L之施加至半導體晶粒112之第一邊緣152的底部填充材料將具有流速140，該流速類似於圖1B之習知技術之流速。流速140僅基於間隙尺寸，因為底部填充材料不會在第一邊緣152處與毛細流動結構130交互。
對比之下，取決於底部填充材料流過之通道之有效面積，平行於毛細流動結構130之長度L之施加至半導體晶粒112的第二邊緣154之底部填充材料將具有更高流速。在與間隙之開放邊緣(例如，第一邊緣152)相鄰的流動通道，底部填充材料將具有等於或大於流速140之流速142。在此等通道中，毛細流動結構130之一側影響毛細力，從而影響流速142。在兩個毛細流動結構130跨越支柱120 (亦即，一列支柱120在毛細流動結構130中之兩者之間)之流動通道中，底部填充材料將具有等於或大於流速142之流速144。在此等通道中，間隔開寬度W2之一個毛細結構130之第一流動元件131及相鄰毛細結構130之第二流動元件132增加毛細力以增加流速144。在個別流動結構130之第一流動元件131與第二流動元件132之間的流動通道中，底部填充材料將具有等於或大於流速144之流速146。在此等通道中，流速146預期為最高流速，因為第一流動元件131與第二流動元件132之間的較小第一寬度W1產生更高毛細力以增加流速146，並且亦因為第一流動元件131與第二流動元件132之間的空間不含支柱120。因此，期望本發明技術減小底部填充物以覆晶組態跨越面向基板150之半導體晶粒112的頂面之整個表面區域填充所需的時間。
本發明技術亦進一步有助於在整個半導體晶粒112之表面區域中保持半導體晶粒112與基板150之間的所需間隔。在沒有毛細流動結構130之情況下，半導體晶粒112可相對於基板150傾斜，使得一個區域在半導體晶粒112與基板150之間具有較小間隙，而另一區域具有較大間隙。此可能會在具有小間隙之區域中引起支柱120之間的短路，及在具有較大間隙之區域中斷開連接。期望毛細流動結構130充當在半導體晶粒112與基板150之間提供均勻空間的間隔物。因此，毛細流動結構130亦增加良率。
圖3A展示以前側向上組態配置之半導體裝置110b。相似附圖標記係指圖2A至圖3B中之相似組件。半導體裝置110b包括半導體晶粒112，該半導體晶粒具有自半導體晶粒112之前側111延伸之支柱120，及在每個支柱120之遠端處之焊料凸塊122。半導體裝置110b可進一步包括毛細流動結構130，其具有遠離半導體晶粒112之前側111突出至高度H之第一流動元件131及第二流動元件132，且該第一流動元件及該第二流動元件具有厚度T及長度L。在此實施例中，第一流動元件131及第二流動元件132彼此間隔開寬度W3，使得其跨越一列支柱120。寬度W3可等於或不同於半導體裝置110a之寬度W2。
圖3B示出直接晶片附接總成100b，其具有倒置之圖3A之半導體裝置110b，使得焊料凸塊122與基板150上之觸點(未展示)介接。在此組態中，毛細流動結構130在基板150與半導體晶粒112之間的間隙中。在與間隙之開放邊緣(例如，第一邊緣152)相鄰的流動通道中，底部填充材料將具有等於或大於流速140，及等於或小於直接晶片附接總成110a之流速142之流速148。在第一流動元件131與第二流動元件132之間的流動通道中，底部填充材料將具有流速149。流速149可大於流速148，但存在支柱120將至少略微阻礙第一流動元件131與第二流動元件132之間的流動。
圖4展示包括遠離基板150突出之毛細流動結構230之基板150。毛細流動結構230類似於圖2A中之毛細流動結構130，除了毛細流動結構230自基板150，而非半導體晶粒112延伸。因此，毛細流動結構230可彼此間隔開增加毛細流動速率之距離，及每個毛細流動結構230可包括彼此間隔開進一步增加毛細流動速率之距離的第一流動元件231及第二流動元件232。當半導體裝置110a倒置以直接晶片附接至基板150時，毛細流動結構230至少部分地自基板150延伸至半導體裝置110a之前側111。圖2B中之直接晶片附接總成之組態類似地應用於圖4中所示之基板，除了毛細流動結構230替代毛細流動結構130。
圖2A至圖4之所說明支柱及毛細流動結構組態係例示性的，及支柱及毛細流動結構中之任一者可具有不同形狀、尺寸或間隔以形成晶粒與基板之間的所需底部填充流速。
圖5為說明根據本發明技術之實施例之併入有半導體裝置的系統之方塊圖。具有上文參考圖2A至圖4所描述之特徵的半導體裝置中之任一者可併入至大量更大及/或更複雜的系統中之任一者中，該等系統之代表性實例為在圖5中示意性地展示之系統500。系統500可包括處理器502、記憶體504 (例如，SRAM、DRAM、快閃及/或其他記憶體裝置)、輸入/輸出裝置506，及/或其他子系統或組件508。上文參考圖2A至圖4描述之半導體總成、裝置及裝置封裝可包括在圖5中所示之元件中之任一者中。所得系統500可經組態以執行各種合適的計算、處理、儲存、感測、成像及/或其他功能中之任一者。因此，系統500之代表性實例包括但不限於：電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路家電、手持式裝置(例如，掌上型電腦、可穿戴式電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器之或可程式化之消費型電子裝置、網路電腦及微型電腦。系統500之額外代表性實例包括燈、相機、交通工具等。在此等及其他實例中，系統500可容納於單一單元中或例如藉由通信網路分佈於多個互連單元上。因此，系統500之組件可包括本端及/或遠端記憶體儲存裝置及各種合適的電腦可讀媒體中之任一者。
本發明技術包括優於習知的覆晶底部填充製程之若干優點。本發明技術之毛細流動結構組態增加底部填充材料之毛細流動動作。在一些實施例中，本發明技術允許(a)由於沿著毛細流動結構之更高底部填充材料流速而引起的更快覆晶底部填充處理，(b)增加的接合表面積及機械抓握以改良半導體晶粒至基板之黏附性，及(c)減少將半導體晶粒安裝至基板所需的底部填充材料之量。所說明的實施例描繪使用本發明技術之毛細流動結構組態之半導體裝置之實例；然而，毛細流動結構之其他裝置組態亦在本發明技術之範疇內。
如在前面之描述中所使用，鑒於圖中所示之定向，術語「垂直」，「橫向」，「上部」及「下部」可指代半導體裝置中之特徵之相對方向或位置。舉例而言，「上部」或「最上部」可指比另一特徵更接近頁面之頂部定位之特徵。然而，此等術語應廣泛地理解為包括具有其他定向之半導體裝置，該等定向諸如倒置或傾斜定向，其中頂部/底部、上面/下面、上方/下方、向上/向下、左側/右側，及遠端/近端可取決於定向而互換。此外，為了易於參考，貫穿本發明，相同附圖標記用於標識類似或相似組件或特徵，但使用相同附圖標記並不暗示特徵應理解為相同的。實際上，在本文中所描述之許多實例中，相同編號之特徵具有結構及/或功能彼此不同之複數個實施例。此外，除非本文中具體地標註，否則相同著色可用於指示橫截面中之可在成分上類似的材料，但使用相同著色並不暗示材料應理解為相同的。
前述揭示內容亦可參考數量及數目。除非特別說明，否則不應將此等數量及數目視為限制性的，而應作為與新技術相關之可能數量或數目的示例。而且，就此而言，本發明可使用術語「複數個」指代數量或數目。就此而言，術語「複數個」表示大於一，例如，二、三、四、五等之任何數目。出於本發明之目的，短語「A、B及C中之至少一者」例如表示(A)、(B)、(C)、(A及B)、(A及C)、(B及C)，或(A、B及C)，包括列出多於三個元素時之所有進一步可能的排列。
自前述內容中應瞭解，儘管本文中已經出於說明之目的描述了新技術之特定實施例，但可在不偏離本發明之情況下進行各種修改。因此，本發明不受除所附申請專利範圍之外的限制。此外，在具體實施例之上下文中描述之新技術之某些態樣亦可在其他實施例中組合或移除。此外，儘管已經在彼等實施例之上下文中描述了與新技術之某些實施例相關聯的優點，但其他實施例亦可顯示此類優點，且並非所有的實施例均要顯示此類優點以落入本發明之範疇內。因此，本發明及相關聯的技術可涵蓋未明確地在本文中展示或描述之其他實施例。
10:習知的覆晶半導體裝置 12:晶粒 20:D2S支柱 22:焊料凸塊 40:底部填充材料流 50:基板 100a:直接晶片附接總成 110a:半導體裝置 110b:半導體裝置 111:前側 112:半導體晶粒 120:支柱 122:焊料凸塊 130:毛細流動結構 131:第一流動元件 132:第二流動元件 140:流速 142:流速 144:流速 146:流速 148:流速 149:流速 150:基板 152:第一邊緣 154:第二邊緣 230:毛細流動結構 231:第一流動元件 232:第二流動元件 500:系統 502:處理器 504:記憶體 506:輸入/輸出裝置 508:子系統或組件 H:高度 L:長度 T:厚度 W1:第一距離 W2:第二距離 W3:寬度
圖1A為展示根據現有技術組態之半導體晶粒之放大透視圖。
圖1B為展示作為覆晶安裝至基板之圖1A的半導體晶粒之放大透視圖。
圖2A為展示具有根據本發明技術之實施例組態之互連結構及毛細流動結構的半導體晶粒之放大透視圖。
圖2B為展示作為覆晶安裝至基板之圖2A的半導體晶粒之放大透視圖。
圖3A為展示具有根據本發明技術之實施例組態之互連結構及毛細流動結構的半導體晶粒之放大透視圖。
圖3B為展示作為覆晶安裝至基板之圖3A的半導體晶粒之放大透視圖。
圖4為展示具有根據本發明技術之實施例組態之毛細流動結構的基板之放大透視圖。
圖5為包括根據本發明技術之實施例組態之半導體裝置的系統之示意圖。
100a:直接晶片附接總成
110a:半導體裝置
111:前側
112:半導體晶粒
120:支柱
122:焊料凸塊
130:毛細流動結構
131:第一流動元件
132:第二流動元件
140:流速
142:流速
144:流速
146:流速
150:基板
152:第一邊緣
154:第二邊緣

Claims (17)

  1. 一種用於直接晶片附接之半導體裝置，其包含：一基板；一半導體晶粒，其具有自一前側延伸之一導電支柱，該半導體晶粒藉由該導電支柱電耦接至該基板，且該半導體晶粒之該前側與該基板間隔開一間隙；及一毛細流動結構，其具有自該前側朝向該基板突出之第一及第二細長流動元件，該等第一及第二細長流動元件彼此橫向間隔開一第一寬度，該第一寬度經組態以引起一底部填充材料(a underfill material)沿著該等第一及第二細長流動元件之一長度進行毛細流動(capillary flow)，其中該等第一及第二流動元件之表面、該基板、及該半導體晶粒之該前側形成一第一通道，該底部填充材料因引起之毛細流動而行進通過該第一通道。
  2. 如請求項1之半導體裝置，其中當該半導體晶粒電耦接至該基板時，該等第一及第二細長流動元件接觸該基板。
  3. 如請求項1之半導體裝置，其中該第一通道不含支柱，並且其中在該第一通道內一引起的毛細流動速率高於該間隙內在該第一通道外部之一引起的毛細流動速率。
  4. 如請求項1之半導體裝置，其中該導電支柱在該第一通道內部，並且 其中在該第一通道內一引起的毛細流動速率高於該間隙內在該第一通道外部之一引起的毛細流動速率。
  5. 如請求項1之半導體裝置，其進一步包含具有自該前側朝向該基板突出之第一及第二細長流動元件之一第二毛細流動結構，該第二毛細流動結構之該等第一及第二毛細流動元件中之每一者彼此橫向間隔開一第二寬度，該第二寬度經組態以引起一底部填充材料沿著該第二毛細流動結構之該等第一及第二細長流動元件之一長度進行毛細流動。
  6. 如請求項5之半導體裝置，其中：該第二毛細流動結構之該等第一及第二細長流動元件之表面、該基板、及該半導體晶粒之該前側形成一第二通道，該底部填充材料因引起的毛細流動行進藉由該第二通道，及該等第一及第二毛細流動結構之相對外表面、該基板及該半導體晶粒之該前側形成一第三通道，該底部填充材料因引起的毛細流動行進通過該第三通道。
  7. 如請求項6之半導體裝置，其中在該等第一及第二通道內一引起的毛細流動速率高於在該第三通道內一引起的毛細流動速率。
  8. 如請求項6之半導體裝置，其中在該第三通道內一引起的毛細流動速率高於該間隙內在該等第一、第二、及第三通道外部之一引起的毛細流動速率。
  9. 一種用於直接晶片附接之半導體裝置，其包含：一基板；一半導體晶粒，其具有自一前側延伸之一導電支柱，該半導體晶粒藉由該導電支柱電耦接至該基板，且該半導體晶粒之該前側與該基板間隔開一間隙；及第一及第二毛細流動結構，每一者具有自該前側朝向該基板突出之第一及第二細長流動元件，該等第一及第二毛細流動結構彼此橫向間隔開一第一寬度，該第一寬度經組態以引起一底部填充材料在該等第一及第二毛細流動結構之間進行毛細流動，其中當該半導體晶粒電耦接至該基板時，該等第一及第二毛細流動結構接觸該基板。
  10. 如請求項9之半導體裝置，其中該第一毛細流動結構之該等第一及第二細長流動元件彼此橫向間隔開一第二寬度，並且其中該第二毛細流動結構之該等第一及第二細長流動元件彼此間隔開一第三寬度。
  11. 如請求項10之半導體裝置，其中該第一寬度大於該等第二及第三寬度。
  12. 如請求項9之半導體裝置，其中該第一毛細流動結構之該等第一及第二細長流動元件、該基板、及該半導體晶粒之該前側形成一第一通道，該底部填充材料因引起的毛細流動行進通過該第一通道，並且其中該第二毛 細流動結構之該等第一及第二細長流動元件、該基板、及該半導體晶粒之該前側形成一第二通道，該底部填充材料因引起的毛細流動行進藉由該第二通道。
  13. 如請求項12之半導體裝置，其中該等第一及第二通道不含支柱，並且其中在該等第一及第二通道中之任一者內一引起的毛細流動速率高於該間隙內在該第一通道外部之一引起的毛細流動速率。
  14. 如請求項12之半導體裝置，其中該等第一及第二毛細流動結構之相對外表面、該基板、及該半導體晶粒之該前側形成一第三通道，該底部填充材料因引起的毛細流動行進通過該第三通道。
  15. 如請求項14之半導體裝置，其中該導電支柱在該第一通道內部，並且其中在該第一通道內一引起的毛細流動速率高於該間隙內在該第一通道外部之一引起的毛細流動速率。
  16. 如請求項14之半導體裝置，其中在該等第一及第二通道內一引起的毛細流動速率高於在該第三通道內一引起的毛細流動速率。
  17. 如請求項14之半導體裝置，其中在該第三通道內一引起的毛細流動速率高於該間隙內在該等第一、第二、及第三通道外部之一引起的毛細流動速率。
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