TWI749958B - Pixel driving circuit - Google Patents

Pixel driving circuit Download PDF

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TWI749958B
TWI749958B TW109145315A TW109145315A TWI749958B TW I749958 B TWI749958 B TW I749958B TW 109145315 A TW109145315 A TW 109145315A TW 109145315 A TW109145315 A TW 109145315A TW I749958 B TWI749958 B TW I749958B
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switch
terminal
control
control signal
period
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TW109145315A
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TW202147286A (en
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林志隆
廖威勝
吳佳恩
陳松駿
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友達光電股份有限公司
國立成功大學
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Abstract

A pixel driving circuit includes a light emitting unit, thirteen switches and three capacitors. A driving circuit of the light emitting unit passes only one of the switches to reduce power consumption. In addition, threshold voltages and operation voltages are compensated in the pixel driving circuit so that the light emitting unit can provide consistent brightness.

Description

畫素驅動電路Pixel drive circuit

本揭露是有關於發光二極體的畫素驅動電路。This disclosure relates to a pixel driving circuit for light-emitting diodes.

目前發光二極體已經廣泛地應用於各類型的顯示器當中。發光二極體發光時的亮度與其驅動電流的大小有關，而其驅動電流的大小係由驅動電晶體來控制。然而，因為製程的變異會造成顯示器中的每個畫素的驅動電晶體的臨界電壓(threshold voltage,Vth)不盡相同，如此一來將會使得不同畫素之中的發光二極體具有不同的驅動電流而使每個發光二極體的亮度不一，進而造成顯示器在顯示畫面的時候會有亮度不均勻的問題。此外，驅動電流示由操作電壓所提供，而操作電壓容易因為傳遞路徑中的線阻產生壓降，使得每個畫素的操作電壓不同，使驅動電流產生誤差。At present, light-emitting diodes have been widely used in various types of displays. The brightness of the light-emitting diode when it emits light is related to the size of its driving current, and the size of its driving current is controlled by the driving transistor. However, because of the variation of the manufacturing process, the threshold voltage (Vth) of the driving transistor of each pixel in the display will be different, which will cause the light-emitting diodes in different pixels to have different values. The driving current causes the brightness of each light-emitting diode to be different, which in turn causes the problem of uneven brightness when the display displays pictures. In addition, the drive current is provided by the operating voltage, and the operating voltage is prone to a voltage drop due to the line resistance in the transmission path, which makes the operating voltage of each pixel different and causes errors in the drive current.

因此，如何針對顯示器畫素之驅動電晶體的臨界電壓做補償，並也對操作電壓做補償，是本領域的技術人員所致力研究的目標。Therefore, how to compensate for the critical voltage of the driving transistor of the display pixel and also compensate for the operating voltage is the goal of the research by those skilled in the art.

本發明的實施例提出一種畫素驅動電路，包括以下元件。發光單元具有第一端及第二端，發光單元的第一端連接至第一操作電壓。第一開關具有第一端、第二端及控制端，第一開關的第一端連接至發光單元的第二端，第一開關的第二端連接至第二操作電壓。第二開關具有第一端、第二端及控制端，第二開關的第一端連接至第一開關的控制端，第二開關的第二端連接至第一開關的第二端及第二操作電壓，第二開關的控制端連接至第一控制訊號。第一電容具有第一端及第二端，第一電容的第一端連接至第一開關的控制端及第二開關的第一端。第二電容具有第一端及第二端，第二電容的第一端連接至第一電容的第二端，第二電容的第二端連接至一參考電壓。第三開關具有第一端、第二端及控制端，第三開關的第一端連接至第一開關的控制端、第二開關的第一端及第一電容的第一端，第三開關的控制端連接至第二控制訊號。第四開關具有第一端、第二端及控制端，第四開關的第一端連接至第四開關的控制端，第四開關的第二端連接至參考電壓。第五開關具有第一端、第二端及控制端，第五開關的第一端連接至第一開關的第二端及第二開關的第二端，第五開關的第二端連接至第一電容的第二端及第二電容的第一端。第六開關具有第一端、第二端及控制端，第六開關的第一端連接至第五開關的第二端、第一電容的第二端及第二電容的第一端，第六開關的第二端連接至二極體電壓，第六開關的控制端連接至第三控制訊號。第七開關具有第一端、第二端及控制端，第七開關的第一端連接至第五開關的控制端，第七開關的第二端連接至二極體電壓，第七開關的控制端連接至第三控制訊號。第八開關具有第一端、第二端及控制端，第八開關的第一端連接至第五開關的控制端及第七開關的第一端。第三電容具有第一端及第二端，第三電容的第一端連接至第八開關的第二端，第三電容的第二端連接至參考電壓。第九開關具有第一端、第二端及控制端，第九開關的第一端連接至第三電容的第一端及第八開關的第二端，第九開關的第二端連接至第一控制訊號，第九開關的控制端連接至第一控制訊號。第十開關具有第一端、第二端及控制端，第十開關的第一端連接至第八開關的第二端、第三電容的第一端及第九開關的第一端，第十開關的第二端連接至第八開關的控制端，第十開關的控制端連接至第一控制訊號。第十一開關具有第一端、第二端及控制端，第十一開關的第一端連接至第八開關的控制端及第十開關的第二端，第十一開關的第二端連接至第四控制訊號，第十一開關的控制端連接至第三控制訊號。第十二開關具有第一端、第二端及控制端，第十二開關的第一端連接至第八開關的控制端、第十開關的第二端及第十一開關的第一端，第十二開關的第二端連接至一資料電壓，第十二開關的控制端連接至第二控制訊號。The embodiment of the present invention provides a pixel driving circuit, which includes the following components. The light-emitting unit has a first end and a second end, and the first end of the light-emitting unit is connected to the first operating voltage. The first switch has a first terminal, a second terminal and a control terminal. The first terminal of the first switch is connected to the second terminal of the light-emitting unit, and the second terminal of the first switch is connected to the second operating voltage. The second switch has a first terminal, a second terminal and a control terminal. The first terminal of the second switch is connected to the control terminal of the first switch, and the second terminal of the second switch is connected to the second terminal and the second terminal of the first switch. Operating voltage, the control terminal of the second switch is connected to the first control signal. The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is connected to the control terminal of the first switch and the first terminal of the second switch. The second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is connected to the second terminal of the first capacitor, and the second terminal of the second capacitor is connected to a reference voltage. The third switch has a first terminal, a second terminal, and a control terminal. The first terminal of the third switch is connected to the control terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor. The third switch The control terminal of is connected to the second control signal. The fourth switch has a first terminal, a second terminal and a control terminal. The first terminal of the fourth switch is connected to the control terminal of the fourth switch, and the second terminal of the fourth switch is connected to the reference voltage. The fifth switch has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth switch is connected to the second terminal of the first switch and the second terminal of the second switch, and the second terminal of the fifth switch is connected to the second terminal. The second end of a capacitor and the first end of the second capacitor. The sixth switch has a first terminal, a second terminal and a control terminal. The first terminal of the sixth switch is connected to the second terminal of the fifth switch, the second terminal of the first capacitor, and the first terminal of the second capacitor. The second end of the switch is connected to the diode voltage, and the control end of the sixth switch is connected to the third control signal. The seventh switch has a first terminal, a second terminal and a control terminal. The first terminal of the seventh switch is connected to the control terminal of the fifth switch, and the second terminal of the seventh switch is connected to the diode voltage. The control of the seventh switch The terminal is connected to the third control signal. The eighth switch has a first end, a second end and a control end. The first end of the eighth switch is connected to the control end of the fifth switch and the first end of the seventh switch. The third capacitor has a first terminal and a second terminal, the first terminal of the third capacitor is connected to the second terminal of the eighth switch, and the second terminal of the third capacitor is connected to the reference voltage. The ninth switch has a first terminal, a second terminal and a control terminal. The first terminal of the ninth switch is connected to the first terminal of the third capacitor and the second terminal of the eighth switch. The second terminal of the ninth switch is connected to the first terminal. A control signal, the control terminal of the ninth switch is connected to the first control signal. The tenth switch has a first terminal, a second terminal, and a control terminal. The first terminal of the tenth switch is connected to the second terminal of the eighth switch, the first terminal of the third capacitor, and the first terminal of the ninth switch. The second end of the switch is connected to the control end of the eighth switch, and the control end of the tenth switch is connected to the first control signal. The eleventh switch has a first terminal, a second terminal and a control terminal. The first terminal of the eleventh switch is connected to the control terminal of the eighth switch and the second terminal of the tenth switch, and the second terminal of the eleventh switch is connected To the fourth control signal, the control terminal of the eleventh switch is connected to the third control signal. The twelfth switch has a first end, a second end and a control end. The first end of the twelfth switch is connected to the control end of the eighth switch, the second end of the tenth switch and the first end of the eleventh switch, The second end of the twelfth switch is connected to a data voltage, and the control end of the twelfth switch is connected to the second control signal.

在一些實施例中，畫素驅動電路依序操作於第一期間、第二期間、第三期間及第四期間。在第一期間內，第二開關、第四開關、第六開關、第七開關、第九開關及第十開關處於一導通狀態，第一開關、第三開關、第五開關、第八開關、第十一開關及第十二開關處於一截止狀態。在第二期間內，第三開關、第四開關、第六開關、第七開關、第八開關及第十二開關處於導通狀態，第一開關、第二開關、第五開關、第九開關、第十開關及第十一開關處於截止狀態。在第三期間的第一子期間內，第十一開關處於導通狀態內，第一開關至第三開關、第五開關至第十開關及第十二處於截止狀態。在第三期間的第二子期間內，第一開關、第五開關、第八開關及第十一開關處於導通狀態內，第二開關、第三開關、第六開關、第七開關、第九開關、第十開關及第十二開關處於截止狀態。在第四期間內，第六開關及第七開關處於導通狀態，第一開關、第二開關、第三開關、第五開關、第八開關至第十二開關處於截止狀態。In some embodiments, the pixel driving circuit sequentially operates in the first period, the second period, the third period, and the fourth period. During the first period, the second switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch, and the tenth switch are in a conducting state, and the first switch, the third switch, the fifth switch, the eighth switch, The eleventh switch and the twelfth switch are in an off state. In the second period, the third switch, the fourth switch, the sixth switch, the seventh switch, the eighth switch, and the twelfth switch are in the conducting state, and the first switch, the second switch, the fifth switch, the ninth switch, The tenth switch and the eleventh switch are in an off state. In the first sub-period of the third period, the eleventh switch is in the on state, and the first switch to the third switch, the fifth switch to the tenth switch, and the twelfth switch are in the off state. In the second sub-period of the third period, the first switch, the fifth switch, the eighth switch, and the eleventh switch are in the conducting state, and the second switch, the third switch, the sixth switch, the seventh switch, and the ninth switch are in the conducting state. The switch, the tenth switch and the twelfth switch are in an off state. In the fourth period, the sixth switch and the seventh switch are in the on state, and the first switch, the second switch, the third switch, the fifth switch, the eighth switch to the twelfth switch are in the off state.

在一些實施例中，第八開關及第十一開關為P型電晶體，第一開關至第七開關、第九開關、第十開關及第十二開關為N型電晶體。In some embodiments, the eighth switch and the eleventh switch are P-type transistors, and the first to seventh switches, the ninth switch, the tenth switch, and the twelfth switch are N-type transistors.

在一些實施例中，第一開關的臨界電壓匹配至第四開關的臨界電壓。In some embodiments, the threshold voltage of the first switch is matched to the threshold voltage of the fourth switch.

在一些實施例中，在第一期間內，第一控制訊號與第三控制訊號為第一高準位，第二控制訊號為第一低準位，第四控制訊號為第二高準位。在第二期間內，第一控制訊號為第一低準位，第二控制訊號及第三控制訊號為第一高準位，第四控制訊號為第二高準位。在第三期間內，第一控制訊號、第二控制訊號及第三控制訊號為第一低準位，第四控制訊號由第二高準位逐漸地降低至第二低準位。在第四期間內，第一控制訊號及第二控制訊號為第一低準位，第三控制訊號為第一高準位，第四控制訊號為第二高準位。In some embodiments, during the first period, the first control signal and the third control signal are at the first high level, the second control signal is at the first low level, and the fourth control signal is at the second high level. In the second period, the first control signal is the first low level, the second control signal and the third control signal are the first high level, and the fourth control signal is the second high level. In the third period, the first control signal, the second control signal, and the third control signal are at the first low level, and the fourth control signal is gradually reduced from the second high level to the second low level. In the fourth period, the first control signal and the second control signal are at the first low level, the third control signal is at the first high level, and the fourth control signal is at the second high level.

在一些實施例中，第一操作電壓大於第二操作電壓。In some embodiments, the first operating voltage is greater than the second operating voltage.

在一些實施例中，上述的發光單元為發光二極體。In some embodiments, the above-mentioned light-emitting unit is a light-emitting diode.

在一些實施例中，上述發光二極體的尺寸為次毫米。In some embodiments, the size of the above-mentioned light-emitting diode is sub-millimeter.

在一些實施例中，上述的畫素驅動電路設置於顯示面板內。In some embodiments, the above-mentioned pixel driving circuit is disposed in the display panel.

在一些實施例中，上述的畫素驅動電路設置於背光模組內。In some embodiments, the above-mentioned pixel driving circuit is disposed in the backlight module.

在上述的畫素驅動電路中，可以補償臨界電壓與操作電壓，並且具有節省功率消耗的功效。In the above-mentioned pixel driving circuit, the threshold voltage and the operating voltage can be compensated, and it has the effect of saving power consumption.

關於本文中所使用之「第一」、「第二」等，並非特別指次序或順位的意思，其僅為了區別以相同技術用語描述的元件或操作。Regarding the “first”, “second”, etc. used in this text, it does not particularly mean the order or sequence, but only distinguishes elements or operations described in the same technical terms.

圖1是根據一實施例繪示畫素驅動電路的電路架構圖。畫素驅動電路100可以設置在顯示裝置的背光模組上以提供背光源，或者設置在顯示面板中做為一像素，本揭露並不在此限。畫素驅動電路100包括了發光單元110、開關T1~T12、第一電容C1、第二電容C2及第三電容C3。發光單元110例如為發光二極體，此發光二極體的尺寸可以是次毫米等級或其他合適的大小，本揭露並不在此限。FIG. 1 is a circuit structure diagram of a pixel driving circuit according to an embodiment. The pixel driving circuit 100 can be arranged on a backlight module of a display device to provide a backlight, or arranged as a pixel in a display panel, and the present disclosure is not limited thereto. The pixel driving circuit 100 includes a light-emitting unit 110, switches T1 to T12, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The light-emitting unit 110 is, for example, a light-emitting diode, and the size of the light-emitting diode may be sub-millimeter or other suitable size, and the present disclosure is not limited thereto.

發光單元110具有第一端110-1及第二端110-2，發光單元110的第一端110-1連接至操作電壓VDD。開關T1具有第一端T1-1、第二端T1-2及控制端T1-3，開關T1的第一端T1-1連接至發光單元110的第二端110-2，開關T1的第二端T1-2連接至操作電壓VSS，其中操作電壓VSS小於操作電壓VDD。開關T2具有第一端T2-1、第二端T2-2及控制端T2-3，開關T2的第一端T2-1連接至開關T1的控制端T1-3，開關T2的第二端T2-2連接至開關T1的第二端T1-2及操作電壓VSS，開關T2的控制端T2-3連接至控制訊號S1。第一電容C1具有第一端C1-1及第二端C1-2，第一電容C1的第一端C1-1連接至開關T1的控制端T1-3及開關T2的第一端T2-1。第二電容C2具有第一端C2-1及第二端C2-2，第二電容C2的第一端C2-1連接至第一電容C1的第二端C1-2，第二電容C2的第二端C2-2連接至參考電壓Vref。開關T3具有第一端T3-1、第二端T3-2及控制端T3-3，開關T3的第一端T3-1連接至開關T1的控制端T1-3、開關T2的第一端T2-1及第一電容C1的第一端C1-1，開關T3的控制端T3-3連接至控制訊號S2。開關T4具有第一端T4-1、第二端T4-2及控制端T4-3，開關T4的第一端T4-1連接至開關T4的控制端T4-3以及開關T3的第二端T3-2，開關T4的第二端T4-2連接至參考電壓Vref。開關T5具有第一端T5-1、第二端T5-2及控制端T5-3，開關T5的第一端T5-1連接至開關T1的第二端T1-2及開關T2的第二端T2-2，開關T5的第二端 T5-2連接至第一電容C1的第二端C1-2及第二電容C2的第一端C2-1。開關T6具有第一端T6-1、第二端T6-2及控制端T6-3，開關T6的第一端T6-1連接至開關T5的第二端T5-2、第一電容C1的第二端C1-2及第二電容C2的第一端C2-1，開關T6的第二端T6-2連接至二極體電壓VLED，開關T6的控制端T6-3連接至控制訊號EM。 The light-emitting unit 110 has a first terminal 110-1 and a second terminal 110-2, and the first terminal 110-1 of the light-emitting unit 110 is connected to an operating voltage VDD. The switch T1 has a first terminal T1-1, a second terminal T1-2, and a control terminal T1-3. The first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light emitting unit 110, and the second terminal of the switch T1 The terminal T1-2 is connected to the operating voltage VSS, where the operating voltage VSS is less than the operating voltage VDD. The switch T2 has a first terminal T2-1, a second terminal T2-2, and a control terminal T2-3. The first terminal T2-1 of the switch T2 is connected to the control terminal T1-3 of the switch T1, and the second terminal T2 of the switch T2 -2 is connected to the second terminal T1-2 of the switch T1 and the operating voltage VSS, and the control terminal T2-3 of the switch T2 is connected to the control signal S1. The first capacitor C1 has a first terminal C1-1 and a second terminal C1-2. The first terminal C1-1 of the first capacitor C1 is connected to the control terminal T1-3 of the switch T1 and the first terminal T2-1 of the switch T2. . The second capacitor C2 has a first terminal C2-1 and a second terminal C2-2. The first terminal C2-1 of the second capacitor C2 is connected to the second terminal C1-2 of the first capacitor C1. The two terminals C2-2 are connected to the reference voltage V ref . The switch T3 has a first terminal T3-1, a second terminal T3-2, and a control terminal T3-3. The first terminal T3-1 of the switch T3 is connected to the control terminal T1-3 of the switch T1 and the first terminal T2 of the switch T2. -1 and the first terminal C1-1 of the first capacitor C1, and the control terminal T3-3 of the switch T3 is connected to the control signal S2. The switch T4 has a first terminal T4-1, a second terminal T4-2, and a control terminal T4-3. The first terminal T4-1 of the switch T4 is connected to the control terminal T4-3 of the switch T4 and the second terminal T3 of the switch T3. -2, the second terminal T4-2 of the switch T4 is connected to the reference voltage Vref . The switch T5 has a first terminal T5-1, a second terminal T5-2, and a control terminal T5-3. The first terminal T5-1 of the switch T5 is connected to the second terminal T1-2 of the switch T1 and the second terminal of the switch T2. T2-2, the second terminal T5-2 of the switch T5 is connected to the second terminal C1-2 of the first capacitor C1 and the first terminal C2-1 of the second capacitor C2. The switch T6 has a first terminal T6-1, a second terminal T6-2, and a control terminal T6-3. The first terminal T6-1 of the switch T6 is connected to the second terminal T5-2 of the switch T5 and the second terminal T5-2 of the first capacitor C1. The two terminals C1-2 and the first terminal C2-1 of the second capacitor C2, the second terminal T6-2 of the switch T6 are connected to the diode voltage V LED , and the control terminal T6-3 of the switch T6 is connected to the control signal EM.

開關T7具有第一端T7-1、第二端T7-2及控制端T7-3，開關T7的第一端T7-1連接至開關T5的控制端T5-3，開關T7的第二端T7-2連接至二極體電壓VLED，開關T7的控制端T7-3連接至控制訊號EM。開關T8具有第一端T8-1、第二端T8-2及控制端T8-3，開關T8的第一端T8-1連接至開關T5的控制端T5-3及開關T7的第一端T7-1。第三電容C3具有第一端C3-1及第二端C3-2，第三電容C3的第一端C3-1連接至開關T8的第二端T8-2，第三電容C3的第二端C3-2連接至參考電壓Vref。開關T9具有第一端T9-1、第二端T9-2及控制端T9-3，開關T9的第一端T9-1連接至第三電容C3的第一端C3-1及開關T8的第二端T8-2，開關T9的第二端T9-2連接至控制訊號S1，開關T9的控制端T9-3連接至控制訊號S1。開關T10具有第一端T10-1、第二端T10-2及控制端T10-3，開關T10的第一端T10-1連接至開關T8的第二端T8-2、第三電容C3的第一端C3-1及開關T9的第一端T9-1，開關T10的第二端T10-2連 接至開關T8的控制端T8-3，開關T10的控制端T10-3連接至控制訊號S1。開關T11具有第一端T11-1、第二端T11-2及控制端T11-3，開關T11的第一端T11-1連接至開關T8的控制端T8-3及開關T10的第二端T10-2，開關T11的第二端T11-2連接至控制訊號Vsweep，開關T11的控制端T11-3連接至控制訊號EM。開關T12具有第一端T12-1、第二端T12-2及控制端T12-3，開關T12的第一端T12-1連接至開關T8的控制端T8-3、開關T10的第二端T10-2及開關T11的第一端T11-1，開關T12的第二端T12-2連接至資料電壓VDATA，開關T12的控制端T12-3連接至控制訊號S2。 The switch T7 has a first terminal T7-1, a second terminal T7-2, and a control terminal T7-3. The first terminal T7-1 of the switch T7 is connected to the control terminal T5-3 of the switch T5, and the second terminal T7 of the switch T7 -2 is connected to the diode voltage V LED , and the control terminal T7-3 of the switch T7 is connected to the control signal EM. The switch T8 has a first terminal T8-1, a second terminal T8-2, and a control terminal T8-3. The first terminal T8-1 of the switch T8 is connected to the control terminal T5-3 of the switch T5 and the first terminal T7 of the switch T7. -1. The third capacitor C3 has a first terminal C3-1 and a second terminal C3-2. The first terminal C3-1 of the third capacitor C3 is connected to the second terminal T8-2 of the switch T8, and the second terminal of the third capacitor C3 C3-2 is connected to the reference voltage V ref . The switch T9 has a first terminal T9-1, a second terminal T9-2, and a control terminal T9-3. The first terminal T9-1 of the switch T9 is connected to the first terminal C3-1 of the third capacitor C3 and the first terminal C3-1 of the switch T8. Two terminals T8-2, the second terminal T9-2 of the switch T9 is connected to the control signal S1, and the control terminal T9-3 of the switch T9 is connected to the control signal S1. The switch T10 has a first terminal T10-1, a second terminal T10-2, and a control terminal T10-3. The first terminal T10-1 of the switch T10 is connected to the second terminal T8-2 of the switch T8 and the second terminal T8-2 of the third capacitor C3. One terminal C3-1 and the first terminal T9-1 of the switch T9, the second terminal T10-2 of the switch T10 is connected to the control terminal T8-3 of the switch T8, and the control terminal T10-3 of the switch T10 is connected to the control signal S1. The switch T11 has a first terminal T11-1, a second terminal T11-2, and a control terminal T11-3. The first terminal T11-1 of the switch T11 is connected to the control terminal T8-3 of the switch T8 and the second terminal T10 of the switch T10 -2, the second terminal T11-2 of the switch T11 is connected to the control signal V sweep , and the control terminal T11-3 of the switch T11 is connected to the control signal EM. The switch T12 has a first terminal T12-1, a second terminal T12-2, and a control terminal T12-3. The first terminal T12-1 of the switch T12 is connected to the control terminal T8-3 of the switch T8 and the second terminal T10 of the switch T10. -2 and the first terminal T11-1 of the switch T11, the second terminal T12-2 of the switch T12 is connected to the data voltage V DATA , and the control terminal T12-3 of the switch T12 is connected to the control signal S2.

在此實施例中，開關T1~T12例如為薄膜電晶體(thin film transistor)，其中開關T8、T11為P型電晶體，開關T1~T7、T9、T10、T12為N型電晶體。此外，開關T1的臨界電壓匹配至開關T4的臨界電壓，以下會再詳細說明臨界電壓匹配的功效。 In this embodiment, the switches T1 to T12 are, for example, thin film transistors, where the switches T8 and T11 are P-type transistors, and the switches T1 to T7, T9, T10, and T12 are N-type transistors. In addition, the threshold voltage of the switch T1 is matched to the threshold voltage of the switch T4, and the effect of the threshold voltage matching will be described in detail below.

圖2是根據一實施例繪示畫素驅動電路中各個控制訊號的時序圖。請參照圖2，畫素驅動電路依序操作於第一期間210、第二期間220、第三期間230及第四期間240，而第四期間240結束後又回到第一期間210。 FIG. 2 is a timing diagram of various control signals in the pixel driving circuit according to an embodiment. 2, the pixel driving circuit sequentially operates in the first period 210, the second period 220, the third period 230, and the fourth period 240, and after the fourth period 240 ends, it returns to the first period 210.

圖3是根據一實施例繪示在第一期間內畫素驅動電路的開關示意圖。請參照圖2與圖3，第一期間210是用以重置畫素驅動電路100。在第一期間210內，控制訊號S1與控制訊號EM為高準位VGH，控制訊號S2為低 準位VGL，控制訊號Vsweep為高準位Vsweep_H，其中高準位VGH可相同或不相同於高準位Vsweep_H，本揭露並不在此限。因此，開關T2、T4、T6、T7、T9、T10處於導通狀態，開關T1、T3、T5、T8、T11、T12處於截止狀態。在第一期間210內，節點A的電位相同於參考電壓VSS。節點B及節點C的電位相同於二極體電壓VLED。節點D及節點E的電位相同於高準位VGH。 FIG. 3 is a schematic diagram showing the switching of the pixel driving circuit in the first period according to an embodiment. 2 and 3, the first period 210 is used to reset the pixel driving circuit 100. In the first period 210, the control signal S1 and the control signal EM are at the high level V GH , the control signal S2 is at the low level V GL , and the control signal V sweep is at the high level V sweep_H , where the high level V GH can be the same Or it may not be the same as the high level V sweep_H , and the disclosure is not limited thereto. Therefore, the switches T2, T4, T6, T7, T9, and T10 are in the on state, and the switches T1, T3, T5, T8, T11, and T12 are in the off state. In the first period 210, the potential of the node A is the same as the reference voltage VSS. The potentials of the node B and the node C are the same as the diode voltage V LED . The potentials of the node D and the node E are the same as the high level V GH .

圖4是根據一實施例繪示在第二期間內畫素驅動電路的開關示意圖。請參照圖2與圖4，第二期間220是用以做電壓補償。在第二期間220內，控制訊號S1為低準位VGL，控制訊號S2與控制訊號EM為高準位VGH，控制訊號Vsweep為高準位Vsweep_H。因此，開關T3、T4、T6、T7、T8、T12處於導通狀態，開關T1、T2、T5、T9、T10、T11處於截止狀態。在此期間，節點A的電位相同於Vref+VTH_T4，其中VTH_T4為開關T4的臨界電壓。節點B與節點C的電位相同於二極體電壓VLED。節點D的電位相同於資料電壓VDATA。節點E的電位會因為第三電容C3的充電而增加，直到節點E的電位等於VDATA+|VTH_T8|時開關T8切換為截止狀態，其中VTH_T8為開關T8的臨界電壓。 4 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to an embodiment. 2 and 4, the second period 220 is used for voltage compensation. In the second period 220, the control signal S1 is at the low level V GL , the control signal S2 and the control signal EM are at the high level V GH , and the control signal V sweep is at the high level V sweep_H . Therefore, the switches T3, T4, T6, T7, T8, and T12 are in the on state, and the switches T1, T2, T5, T9, T10, and T11 are in the off state. During this period, the potential of the node A is the same as V ref +V TH_T4 , where V TH_T4 is the threshold voltage of the switch T4. The potentials of the node B and the node C are the same as the diode voltage V LED . The potential of the node D is the same as the data voltage V DATA . The potential of the node E will increase due to the charging of the third capacitor C3 until the potential of the node E is equal to V DATA + |V TH_T8 | when the switch T8 is switched to the off state, where V TH_T8 is the threshold voltage of the switch T8.

圖5是根據一實施例繪示在第三期間內第一子期間的畫素驅動電路的開關示意圖。請參照圖2與圖5，第三期間230分為第一子期間230-1及第二子期間230-2，在第一子期間230-1發光單元110為截止，而在第二子期 間230-2發光單元110為導通並發光。第一子期間230-1及第二子期間230-2的長度是由資料電壓VDATA所決定。換言之，在此實施例中是以脈寬調變(pulse width modulation，PWM)的方式來驅動發光單元110，藉此決定像素的亮度。具體來說，在第三期間230內，控制訊號S1、控制訊號S2及控制訊號EM為低準位VGL，控制訊號Vsweep由高準位Vsweep_H逐漸地降低至低準位Vsweep_L。 FIG. 5 is a schematic diagram showing the switching of the pixel driving circuit in the first sub-period in the third period according to an embodiment. 2 and 5, the third period 230 is divided into a first sub-period 230-1 and a second sub-period 230-2, in the first sub-period 230-1 the light-emitting unit 110 is turned off, and in the second sub-period The 230-2 light-emitting unit 110 is turned on and emits light. The lengths of the first sub-period 230-1 and the second sub-period 230-2 are determined by the data voltage V DATA . In other words, in this embodiment, the light-emitting unit 110 is driven in a pulse width modulation (PWM) manner, thereby determining the brightness of the pixel. Specifically, during the third period 230, the control signal S1, the control signal S2 and a control signal EM is the low level V GL, the control signal V sweep reduced from the high level V sweep_H gradually to the low level V sweep_L.

在第一子期間230-1內，開關T11處於導通狀態內，開關T1~T3、T5~T10、T12處於截止狀態。節點A的電位不變，維持在Vref+VTH_T4。節點B與節點C的電位相同於二極體電壓VLED。節點D的電位相同於控制訊號Vsweep。節點E的電位相同於VDATA+|VTH_T8|。節點D的電位會逐漸地下降，直到以下數學式1成立時開關T8切換為導通狀態，然後會進入第二子期間230-2。 In the first sub-period 230-1, the switch T11 is in the on state, and the switches T1 to T3, T5 to T10, and T12 are in the off state. The potential of the node A does not change and remains at V ref +V TH_T4 . The potentials of the node B and the node C are the same as the diode voltage V LED . The potential of the node D is the same as the control signal V sweep . The potential of node E is the same as V DATA +|V TH_T8 |. The potential of the node D will gradually decrease until the switch T8 is switched to the on state when the following mathematical formula 1 is established, and then the second sub-period 230-2 will be entered.

Figure 109145315-A0305-02-0013-2
Figure 109145315-A0305-02-0013-2

其中VE表示節點E的電位，VD表示節點D的電位。由於開關T8的臨界電壓自我補償，因此上述數學式1的成立條件並不受開關T8的臨界電壓所影響。當資料電壓VDATA越大時，數學式1越早成立，也就越早進入第二子期間230-2。 Where V E represents the potential of node E, and V D represents the potential of node D. Since the threshold voltage of the switch T8 is self-compensating, the above-mentioned mathematical formula 1 is not affected by the threshold voltage of the switch T8. When the data voltage V DATA is larger, the mathematical formula 1 is established earlier, and the second sub-period 230-2 is entered earlier.

圖6是根據一實施例繪示在第三期間內第二子期間的畫素驅動電路的開關示意圖。請參照圖2與圖6，在第二子期間230-2內，開關T1、T5、T8、T11處於導通狀態內，開關T2、T3、T6、T7、T9、T10、T12處於截止狀態。在此期間，節點E與節點C的電位相同於VDATA+|VTH_T8|，此電位會導通開關T5，這使得節點B的電位為操作電壓VSS。節點B的電位從第一子期間230-1的VLED改變至VSS，其變化量為VSS-VLED，因此節點A的電位會從Vref+VTH_T4改變為Vref+VTH_T4+VSS-VLED，此電位會導通開關T1產生電流ILED，此電流ILED流經發光單元110與開關T1，電流ILED的大小如以下數學式2所示。 6 is a schematic diagram showing the switching of the pixel driving circuit in the second sub-period in the third period according to an embodiment. 2 and 6, in the second sub-period 230-2, the switches T1, T5, T8, and T11 are in the on state, and the switches T2, T3, T6, T7, T9, T10, and T12 are in the off state. During this period, the potentials of the node E and the node C are the same as V DATA +|V TH_T8 |, this potential will turn on the switch T5, which makes the potential of the node B the operating voltage VSS. The potential of node B changes from V LED in the first sub-period 230-1 to VSS, and the amount of change is VSS-V LED . Therefore, the potential of node A changes from V ref +V TH_T4 to V ref +V TH_T4 +VSS- V LED , this potential will turn on the switch T1 to generate a current I LED , this current I LED flows through the light-emitting unit 110 and the switch T1, and the magnitude of the current I LED is shown in the following mathematical formula 2.

Figure 109145315-A0305-02-0014-1
Figure 109145315-A0305-02-0014-1

其中K為常數，VA為節點A的電位，VTH_T1為開關T1的臨界電壓。值得注意的是，由於開關T1的臨界電壓匹配至開關T4的臨界電壓，因此在數學式2中兩個臨界電壓V TH_T4、V TH_T1相互抵銷，電流ILED的大小已經不受臨界電壓VTH_T1的影響。此外，由於在數學式2補償了操作電壓VSS，因此電流ILED的大小也不受操作電壓VSS的影響。在習知技術中驅動電流經過了兩個以上的開關，當電流較大時會產生壓降使得開關可能進入線性區， 增加操作電壓VDD、VSS之間的跨壓可以解決此問題，但卻提高了功率消耗。相較之下，電流ILED只會流經一個開關T1，因此具有減少功率消耗的功效。 Where K is a constant, V A is the potential of node A, and V TH_T1 is the threshold voltage of switch T1. It is worth noting that since the threshold voltage of switch T1 matches the threshold voltage of switch T4, the two threshold voltages V TH_T 4 and V TH_T 1 cancel each other out in Mathematical formula 2, and the current I LED is no longer affected by the threshold voltage. The influence of V TH_T1. In addition, since the operating voltage VSS is compensated in Equation 2, the magnitude of the current I LED is also not affected by the operating voltage VSS. In the prior art, the driving current has passed through more than two switches. When the current is large, a voltage drop will occur, which may cause the switch to enter the linear region. Increasing the cross voltage between the operating voltage VDD and VSS can solve this problem, but it increases了 Power consumption. In contrast, the current I LED only flows through one switch T1, so it has the effect of reducing power consumption.

圖7是根據一實施例繪示在第四期間內畫素驅動電路的開關示意圖。請參照圖2與圖7，第四期間240是用以關閉發光單元110。在第四期間240內，控制訊號S1及控制訊號S2為低準位VGL，控制訊號EM為高準位VGH，控制訊號Vsweep為高準位Vsweep_H。因此，開關T6、T7處於導通狀態，開關T1、T2、T3、T5、T8~T12處於截止狀態。在此期間，節點B與節點C的電位為二極體電壓VLED。節點B的電位從第二子期間230-2的VSS改變為第四期間240的VLED，其變化量為VLED-VSS，因此節點A的電位從此期間230-2的Vref+VTH_T4+VSS-VLED改變為Vref+VTH_T4。節點D的電位相同於控制訊號Vsweep。節點E的電位相同於VDATA+|VTH_T8|。 FIG. 7 is a schematic diagram showing the switching of the pixel driving circuit in the fourth period according to an embodiment. 2 and FIG. 7, the fourth period 240 is used to turn off the light-emitting unit 110. In the fourth period 240, the control signal S1 and the control signal S2 are at the low level V GL , the control signal EM is at the high level V GH , and the control signal V sweep is at the high level V sweep_H . Therefore, the switches T6 and T7 are in the on state, and the switches T1, T2, T3, T5, and T8 to T12 are in the off state. During this period, the potentials of the node B and the node C are the diode voltage V LED . The potential of node B changes from VSS in the second sub-period 230-2 to V LED in the fourth period 240, and the amount of change is V LED -VSS, so the potential of node A changes from V ref +V TH_T4 + in this period 230-2 The VSS-V LED changes to V ref +V TH_T4 . The potential of the node D is the same as the control signal V sweep . The potential of node E is the same as V DATA +|V TH_T8 |.

在上述實施例中，“連接”可以是直接連接。 In the above embodiment, "connection" may be a direct connection.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100:畫素驅動電路 100: Pixel drive circuit

110:發光單元 110: light-emitting unit

C1:第一電容 C1: The first capacitor

C2:第二電容 C2: second capacitor

C3:第三電容 C3: third capacitor

T1~T12:開關 T1~T12: switch

ILED:電流 I LED : current

110-1,C1-1,C2-1,C3-1,T1-1,T2-1,T3-1,T4-1,T5-1,T6-1,T7-1,T8-1,T9-1,T10-1,T11-1,T12-1:第一端 110-1, C1-1, C2-1, C3-1, T1-1, T2-1, T3-1, T4-1, T5-1, T6-1, T7-1, T8-1, T9- 1, T10-1, T11-1, T12-1: the first end

110-2,C1-2,C2-2,C3-2,T1-2,T2-2,T3-2,T4-2,T5-2,T6-2,T7-2,T8-2,T9-2,T10-2,T11-2,T12-2:第二端 110-2, C1-2, C2-2, C3-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, T7-2, T8-2, T9- 2, T10-2, T11-2, T12-2: second end

T1-3,T2-3,T3-3,T4-3,T5-3,T6-3,T7-3,T8-3,T9-3,T10-3,T11-3,T12-3:控制端 T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3, T8-3, T9-3, T10-3, T11-3, T12-3: control terminal

A,B,C,D,E:節點 A, B, C, D, E: node

VDD,VSS:操作電壓 VDD, VSS: operating voltage

S1,S2,EM,Vsweep:控制訊號 S1, S2, EM, V sweep : control signal

VDATA:資料電壓 V DATA : data voltage

VLED:二極體電壓 V LED : Diode voltage

Vref:參考電壓 V ref : reference voltage

210:第一期間 210: The first period

220:第二期間 220: second period

230:第三期間 230: third period

230-1:第一子期間 230-1: The first sub-period

230-2:第二子期間 230-2: The second sub-period

240:第四期間 240: The fourth period

VGH,Vsweep_H:高準位 V GH ,V sweep_H : high level

VGL,Vsweep_L:低準位 V GL ,V sweep_L : low level

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 圖1是根據一實施例繪示畫素驅動電路的電路架構圖。 圖2是根據一實施例繪示畫素驅動電路中各個控制訊號的時序圖。 圖3是根據一實施例繪示在第一期間內畫素驅動電路的開關示意圖。 圖4是根據一實施例繪示在第二期間內畫素驅動電路的開關示意圖。 圖5是根據一實施例繪示在第三期間內第一子期間的畫素驅動電路的開關示意圖。 圖6是根據一實施例繪示在第三期間內第二子期間的畫素驅動電路的開關示意圖。 圖7是根據一實施例繪示在第四期間內畫素驅動電路的開關示意圖。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings. FIG. 1 is a circuit structure diagram of a pixel driving circuit according to an embodiment. FIG. 2 is a timing diagram of various control signals in the pixel driving circuit according to an embodiment. FIG. 3 is a schematic diagram showing the switching of the pixel driving circuit in the first period according to an embodiment. 4 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to an embodiment. FIG. 5 is a schematic diagram showing the switching of the pixel driving circuit in the first sub-period in the third period according to an embodiment. 6 is a schematic diagram showing the switching of the pixel driving circuit in the second sub-period in the third period according to an embodiment. FIG. 7 is a schematic diagram showing the switching of the pixel driving circuit in the fourth period according to an embodiment.

100:畫素驅動電路 100: Pixel drive circuit

110:發光單元 110: light-emitting unit

C1:第一電容 C1: The first capacitor

C2:第二電容 C2: second capacitor

C3:第三電容 C3: third capacitor

T1~T12:開關 T1~T12: switch

110-1,C1-1,C2-1,C3-1,T1-1,T2-1,T3-1,T4-1,T5-1,T6-1,T7-1,T8-1,T9-1,T10-1,T11-1,T12-1:第一端 110-1, C1-1, C2-1, C3-1, T1-1, T2-1, T3-1, T4-1, T5-1, T6-1, T7-1, T8-1, T9- 1, T10-1, T11-1, T12-1: the first end

110-2,C1-2,C2-2,C3-2,T1-2,T2-2,T3-2,T4-2,T5-2,T6-2,T7-2,T8-2,T9-2,T10-2,T11-2,T12-2:第二端 110-2, C1-2, C2-2, C3-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, T7-2, T8-2, T9- 2, T10-2, T11-2, T12-2: second end

T1-3,T2-3,T3-3,T4-3,T5-3,T6-3,T7-3,T8-3,T9-3,T10-3,T11-3,T12-3:控制端 T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3, T8-3, T9-3, T10-3, T11-3, T12-3: control terminal

A,B,C,D,E:節點 A, B, C, D, E: node

VDD,VSS:操作電壓 VDD, VSS: operating voltage

S1,S2,EM,Vsweep:控制訊號 S1, S2, EM, V sweep : control signal

VDATA:資料電壓 V DATA : data voltage

VLED:二極體電壓 V LED : Diode voltage

Vref:參考電壓 V ref : reference voltage

Claims (10)

一種畫素驅動電路，包括：一發光單元，具有一第一端及一第二端，該發光單元的該第一端連接至第一操作電壓；一第一開關，具有一第一端、一第二端及一控制端，該第一開關的該第一端連接至該發光單元的該第二端，該第一開關的該第二端連接至第二操作電壓；一第二開關，具有一第一端、一第二端及一控制端，該第二開關的該第一端連接至該第一開關的該控制端，該第二開關的該第二端連接至該第一開關的該第二端及該第二操作電壓，該第二開關的該控制端連接至第一控制訊號；一第一電容，具有一第一端及一第二端，該第一電容的該第一端連接至該第一開關的該控制端及該第二開關的該第一端；一第二電容，具有一第一端及一第二端，該第二電容的該第一端連接至該第一電容的該第二端，該第二電容的該第二端連接至一參考電壓；一第三開關，具有一第一端、一第二端及一控制端，該第三開關的該第一端連接至該第一開關的該控制端、該第二開關的該第一端及該第一電容的該第一端，該第三開關的該控制端連接至一第二控制訊號；一第四開關，具有一第一端、一第二端及一控制端，該第四開關的該第一端連接至該第四開關的該控制端以及該第三開關的該第二端，該第四開關的該第二端連接至該參 考電壓；一第五開關，具有一第一端、一第二端及一控制端，該第五開關的該第一端連接至該第一開關的該第二端及該第二開關的該第二端，該第五開關的該第二端連接至該第一電容的該第二端及該第二電容的該第一端；一第六開關，具有一第一端、一第二端及一控制端，該第六開關的該第一端連接至該第五開關的該第二端、該第一電容的該第二端及該第二電容的該第一端，該第六開關的該第二端連接至一二極體電壓，該第六開關的該控制端連接至一第三控制訊號；一第七開關，具有一第一端、一第二端及一控制端，該第七開關的該第一端連接至該第五開關的該控制端，該第七開關的該第二端連接至該二極體電壓，該第七開關的該控制端連接至該第三控制訊號；一第八開關，具有一第一端、一第二端及一控制端，該第八開關的該第一端連接至該第五開關的該控制端及該第七開關的該第一端；一第三電容，具有一第一端及一第二端，該第三電容的該第一端連接至該第八開關的該第二端，該第三電容的該第二端連接至該參考電壓；一第九開關，具有一第一端、一第二端及一控制端，該第九開關的該第一端連接至該第三電容的該第一端及該第八開關的該第二端，該第九開關的該第二端連接至該第一控制訊號，該第九開關的該控制端連接至該第一控制訊 號；一第十開關，具有一第一端、一第二端及一控制端，該第十開關的該第一端連接至該第八開關的該第二端、該第三電容的該第一端及該第九開關的該第一端，該第十開關的該第二端連接至該第八開關的該控制端，該第十開關的該控制端連接至該第一控制訊號；一第十一開關，具有一第一端、一第二端及一控制端，該第十一開關的該第一端連接至該第八開關的該控制端及該第十開關的該第二端，該第十一開關的該第二端連接至一第四控制訊號，該第十一開關的該控制端連接至該第三控制訊號；一第十二開關，具有一第一端、一第二端及一控制端，該第十二開關的該第一端連接至該第八開關的該控制端、該第十開關的該第二端及該第十一開關的該第一端，該第十二開關的該第二端連接至一資料電壓，該第十二開關的該控制端連接至該第二控制訊號。 A pixel driving circuit includes: a light-emitting unit having a first end and a second end, the first end of the light-emitting unit is connected to a first operating voltage; a first switch having a first end, a A second terminal and a control terminal, the first terminal of the first switch is connected to the second terminal of the light-emitting unit, and the second terminal of the first switch is connected to a second operating voltage; a second switch having A first end, a second end and a control end, the first end of the second switch is connected to the control end of the first switch, and the second end of the second switch is connected to the control end of the first switch The second terminal and the second operating voltage, the control terminal of the second switch is connected to the first control signal; a first capacitor having a first terminal and a second terminal, the first capacitor Terminal is connected to the control terminal of the first switch and the first terminal of the second switch; a second capacitor has a first terminal and a second terminal, and the first terminal of the second capacitor is connected to the The second terminal of the first capacitor, the second terminal of the second capacitor is connected to a reference voltage; a third switch has a first terminal, a second terminal and a control terminal, the third switch The first terminal is connected to the control terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor, and the control terminal of the third switch is connected to a second control signal; A fourth switch having a first end, a second end and a control end, the first end of the fourth switch is connected to the control end of the fourth switch and the second end of the third switch, The second end of the fourth switch is connected to the parameter Test voltage; a fifth switch having a first terminal, a second terminal and a control terminal, the first terminal of the fifth switch is connected to the second terminal of the first switch and the second switch At the second end, the second end of the fifth switch is connected to the second end of the first capacitor and the first end of the second capacitor; a sixth switch has a first end and a second end And a control terminal, the first terminal of the sixth switch is connected to the second terminal of the fifth switch, the second terminal of the first capacitor, and the first terminal of the second capacitor, the sixth switch The second end of the switch is connected to a diode voltage, the control end of the sixth switch is connected to a third control signal; a seventh switch has a first end, a second end and a control end, the The first end of the seventh switch is connected to the control end of the fifth switch, the second end of the seventh switch is connected to the diode voltage, and the control end of the seventh switch is connected to the third control Signal; an eighth switch having a first end, a second end and a control end, the first end of the eighth switch is connected to the control end of the fifth switch and the first of the seventh switch End; a third capacitor having a first end and a second end, the first end of the third capacitor is connected to the second end of the eighth switch, the second end of the third capacitor is connected to The reference voltage; a ninth switch having a first terminal, a second terminal and a control terminal, the first terminal of the ninth switch is connected to the first terminal of the third capacitor and the eighth switch The second end, the second end of the ninth switch is connected to the first control signal, and the control end of the ninth switch is connected to the first control signal No.; a tenth switch, having a first end, a second end and a control end, the first end of the tenth switch is connected to the second end of the eighth switch, the third capacitor One end and the first end of the ninth switch, the second end of the tenth switch is connected to the control end of the eighth switch, and the control end of the tenth switch is connected to the first control signal; The eleventh switch has a first terminal, a second terminal, and a control terminal. The first terminal of the eleventh switch is connected to the control terminal of the eighth switch and the second terminal of the tenth switch , The second end of the eleventh switch is connected to a fourth control signal, the control end of the eleventh switch is connected to the third control signal; a twelfth switch has a first end, a second Two ends and a control end, the first end of the twelfth switch is connected to the control end of the eighth switch, the second end of the tenth switch, and the first end of the eleventh switch, the The second end of the twelfth switch is connected to a data voltage, and the control end of the twelfth switch is connected to the second control signal. 如請求項1所述之畫素驅動電路，其中該畫素驅動電路依序操作於一第一期間、一第二期間、一第三期間及一第四期間，其中在該第一期間內，該第二開關、該第四開關、該第六開關、該第七開關、該第九開關及該第十開關處於一導通狀態，該第一開關、該第三開關、該第五開關、該第八開關、該第十一開關及該第十二開關處於一截止狀態， 其中在該第二期間內，該第三開關、該第四開關、該第六開關、該第七開關、該第八開關及該第十二開關處於該導通狀態，該第一開關、該第二開關、該第五開關、該第九開關、該第十開關及該第十一開關處於該截止狀態，其中在該第三期間的一第一子期間內，該第十一開關處於該導通狀態內，該第一開關至該第三開關、該第五開關至該第十開關及該第十二處於該截止狀態，其中在該第三期間的一第二子期間內，該第一開關、該第五開關、該第八開關及該第十一開關處於該導通狀態內，該第二開關、該第三開關、該第六開關、該第七開關、該第九開關、該第十開關及該第十二開關處於該截止狀態，其中在該第四期間內，該第六開關及該第七開關處於該導通狀態，該第一開關、該第二開關、該第三開關、該第五開關、該第八開關至該第十二開關處於該截止狀態。 The pixel driving circuit according to claim 1, wherein the pixel driving circuit sequentially operates in a first period, a second period, a third period, and a fourth period, wherein during the first period, The second switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch, and the tenth switch are in a conducting state, and the first switch, the third switch, the fifth switch, the The eighth switch, the eleventh switch and the twelfth switch are in an off state, Wherein during the second period, the third switch, the fourth switch, the sixth switch, the seventh switch, the eighth switch, and the twelfth switch are in the conducting state, and the first switch, the second switch The second switch, the fifth switch, the ninth switch, the tenth switch, and the eleventh switch are in the off state, wherein during a first sub-period of the third period, the eleventh switch is in the on state In the state, the first switch to the third switch, the fifth switch to the tenth switch, and the twelfth switch are in the off state, wherein in a second sub-period of the third period, the first switch , The fifth switch, the eighth switch, and the eleventh switch are in the conducting state, the second switch, the third switch, the sixth switch, the seventh switch, the ninth switch, the tenth switch The switch and the twelfth switch are in the off state, wherein during the fourth period, the sixth switch and the seventh switch are in the on state, the first switch, the second switch, the third switch, the The fifth switch, the eighth switch to the twelfth switch are in the cut-off state. 如請求項2所述之畫素驅動電路，其中該第八開關及該第十一開關為P型電晶體，該第一開關至該第七開關、該第九開關、該第十開關及該第十二開關為N型電晶體。 The pixel driving circuit according to claim 2, wherein the eighth switch and the eleventh switch are P-type transistors, the first switch to the seventh switch, the ninth switch, the tenth switch, and the The twelfth switch is an N-type transistor. 如請求項3所述之畫素驅動電路，其中該第一開關的臨界電壓匹配至該第四開關的臨界電壓。 The pixel driving circuit according to claim 3, wherein the threshold voltage of the first switch matches the threshold voltage of the fourth switch. 如請求項3所述之畫素驅動電路，其中在該 第一期間內，該第一控制訊號與該第三控制訊號為一第一高準位，該第二控制訊號為一第一低準位，該第四控制訊號為一第二高準位，其中在該第二期間內，該第一控制訊號為該第一低準位，該第二控制訊號及該第三控制訊號為該第一高準位，該第四控制訊號為該第二高準位，其中在該第三期間內，該第一控制訊號、該第二控制訊號及該第三控制訊號為該第一低準位，該第四控制訊號由該第二高準位逐漸地降低至一第二低準位，其中在該第四期間內，該第一控制訊號及該第二控制訊號為該第一低準位，該第三控制訊號為該第一高準位，該第四控制訊號為該第二高準位。 The pixel driving circuit according to claim 3, wherein the In the first period, the first control signal and the third control signal are at a first high level, the second control signal is at a first low level, and the fourth control signal is at a second high level, In the second period, the first control signal is the first low level, the second control signal and the third control signal are the first high level, and the fourth control signal is the second high level Level, wherein during the third period, the first control signal, the second control signal, and the third control signal are the first low level, and the fourth control signal gradually changes from the second high level Down to a second low level, where in the fourth period, the first control signal and the second control signal are the first low level, the third control signal is the first high level, and the The fourth control signal is the second high level. 如請求項5所述之畫素驅動電路，其中該第一操作電壓大於該第二操作電壓。 The pixel driving circuit according to claim 5, wherein the first operating voltage is greater than the second operating voltage. 如請求項1所述之畫素驅動電路，其中該發光單元為發光二極體。 The pixel driving circuit according to claim 1, wherein the light-emitting unit is a light-emitting diode. 如請求項7所述之畫素驅動電路，其中該發光二極體的尺寸為次毫米。 The pixel driving circuit according to claim 7, wherein the size of the light-emitting diode is sub-millimeter. 如請求項1所述之畫素驅動電路，其中該畫素驅動電路設置於一顯示面板內。 The pixel driving circuit according to claim 1, wherein the pixel driving circuit is provided in a display panel. 如請求項1所述之畫素驅動電路，其中該畫素驅動電路設置於一背光模組內。 The pixel driving circuit according to claim 1, wherein the pixel driving circuit is arranged in a backlight module.
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