JP2014093100A - Shift register circuit and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shift register circuit that prevents a decrease in potential of an output signal.SOLUTION: A shift register circuit 10 includes a transistor 1 that decreases a potential of a node 12 in accordance with an increase in potential of a node 11, and a transistor 2 that decreases the potential of the node 11 in accordance with an increase in potential of the node 12. The shift register circuit 10 further includes a transistor 3 that outputs OUTin association with an increase in potential of the node 11 upon input of CLK.

Description

  The present invention relates to a shift register circuit and an image display device.

  Conventionally, a shift register circuit that transmits a signal output from a preceding circuit to a subsequent circuit is known. Such a shift register circuit is used as a driver circuit for sequentially operating display elements such as an LCD (Liquid Crystal Display) and an organic EL (Electronic Luminescence) display.

  Hereinafter, the operation of the shift register circuit will be described with reference to FIG. FIG. 8 is a circuit diagram illustrating a conventional shift register. For example, the shift register circuit 30 illustrated in FIG. 8 includes a plurality of transistors 31 to 38 and nodes 40 and 41. In the example shown in FIG. 8, the gates (base) and drain (collector) of the transistors 31 and 37 are diode-connected.

  In such a shift register circuit 30, when the signal input from the previous circuit is not output to the next circuit, the potential of the node 40 is in the low state and the potential of the node 41 is in the high state. In the shift register circuit 30, when the signal input from the previous circuit is output to the next circuit, the potential of the node 40 is in a high state and the potential of the node 41 is in a low state.

  Here, when a pulse of “in” that is an input signal is input from the preceding circuit, the shift register circuit 30 inputs a pulse to the node 40 via the transistor 31 that operates as a diode. In such a case, as a result of the potential of the node 40 being in a high state and the transistor 35 being in an on state, the shift register circuit 30 outputs “CLK” that is a clock signal as “OUT” that is an output signal.

  Further, the shift register circuit 30 inputs an “in” pulse to the gate (base) of the transistor 34. In such a case, the transistor 34 is turned on, and the potential of the node 41 drops to “VGL (low potential)”. The shift register circuit 30 inputs a clock signal pulse to the gate of the transistor 38. As a result, the transistor 38 is turned on, the potential of the node 41 is lowered to “VGL”, the transistor 33 is turned off, and the potential of the node 40 is in a high state.

  Further, the shift register circuit 30 inputs “OUT” output from the circuit in the next stage to the gate of the transistor 32. Then, since the transistor 32 is turned on, the potential of the node 40 drops to “VGL”. After the operation of the shift register circuit 30, the transistors 34 and 38 are turned off, the potential of the node 41 is changed from the low state to the high state, and the transistors 33 and 36 are turned on. As a result, the node 40 is turned on. A stable low state is obtained.

JP 2003-046090 A

  However, the above-described shift register circuit 30 has a problem that the potential of the node 41 is not sufficiently lowered and the potential of the output signal is lowered.

  For example, when the transistor 34 is not sufficiently turned on and the potential of the node 41 is not sufficiently lowered, the transistor 33 is not completely turned off. For this reason, the node 40 cannot maintain a sufficiently high potential, and the potential of “OUT” drops.

  Further, when the potential of “OUT” drops, the transistor 38 is not sufficiently turned on, so that the potential of the node 41 is not sufficiently lowered and the transistor 33 is not completely turned off. As a result, the potential of the node 40 further decreases, and the transistor 35 is not sufficiently turned on, so that the potential of “OUT” decreases.

  The present invention has been made in view of the above, and an object of the present invention is to provide a shift register circuit and an image display device that prevent a drop in potential of an output signal.

  The shift register circuit according to the present invention includes a first conductive path having a gate connected to a first conductive path, a drain connected to a second conductive path, and a source connected to a low potential terminal. There is a first transistor that lowers the potential of the second conductive path in response to an increase in potential. In the shift register circuit, the potential of the second conductive path having a gate connected to the second conductive path, a drain connected to the first conductive path, and a source connected to a low potential terminal is There is a second transistor that lowers the potential of the first conductive path in response to the rise. In the shift register circuit, the gate is connected to the first conductive path, the input terminal of the first clock signal is connected to the drain, and the output terminal that outputs the output signal is connected to the source. And a third transistor that outputs an output signal from the output terminal in response to an increase in potential of the first conductive path when a clock signal is input.

  The shift register circuit according to the present invention can prevent a drop in the potential of the output signal.

It is a circuit diagram which shows the shift register circuit of a 1st form. It is a graph explaining the current characteristic of a transistor. It is a figure explaining the signal waveform input into a shift register circuit. It is a figure explaining operation | movement of a shift register circuit. It is a figure explaining an example of simulation. It is a first diagram illustrating an application example of a shift register circuit. It is a 2nd figure explaining the application example of a shift register circuit. It is a circuit diagram explaining the conventional shift register.

  Embodiments of a shift register circuit according to the present invention will be described below in detail with reference to the drawings. Note that this embodiment does not limit the present invention. And the embodiment illustrated below can be suitably changed and combined in the range which does not contradict a shape.

(First form)
[Structure of shift register circuit]
A first embodiment of the shift register circuit will be described with reference to FIG. FIG. 1 is a circuit diagram showing a shift register circuit according to the first embodiment. As shown in FIG. 1, the shift register circuit 10 includes a plurality of transistors 1 to 8 and nodes 11 and 12. Further, the shift register circuit 10 includes “in” output from the previous shift register circuit, “CLK ₁ ” and “CLK ₂ ” which are clock signals, and “OUT ₂ ” which is an output signal of the next shift register circuit. Are input terminals. The shift register circuit 10 has an output terminal “OUT ₁ ” that outputs a signal to the shift register circuit at the next stage. For example, when applied to the driver circuit of the image display device, the shift register circuit 10 outputs a signal from the output terminal of “OUT ₁ ” to the next-stage shift register circuit and the gate line of the image display area. .

  The shift register circuit 10 includes a high potential terminal whose potential is maintained at a value “VGH” higher than a predetermined threshold value, and a low potential terminal whose potential is maintained at a value “VGL” lower than a predetermined threshold value. And have. In the following description, the value of “VGH” is a value higher than GND (ground), for example, 8 (V) to 20 (V), and the value of “VGL” is a value lower than GND. -5 (V) to -15 (V).

  Each of the transistors 1 to 8 is, for example, an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but the present invention is not limited to this. For example, each of the transistors 1 to 8 may be an NPN type transistor or a field effect transistor (FET) adopting a MIS (Metal Insulator Semiconductor) structure of an electron (n type) carrier. Good.

  Each of the transistors 1 to 8 may be a thin film transistor (TFT) which is a kind of FET, that is, an n-MISFET TFT. Alternatively, a circuit that exhibits a function equivalent to that of the shift register circuit 10 may be configured by using a PNP transistor, a FET whose carrier is a hole (p-type), a TFT, or the like.

  Here, each of the transistors 1 to 8 has three electrodes of a gate, a source, and a drain, and the source and the drain are defined by the conductivity of the transistor and the relative potential relationship. For this reason, in the following description, it is assumed that each of the transistors 1 to 8 is an n-channel MOSFET, and among the terminals of each of the transistors 1 to 8, the high potential side terminal is the drain, and the low potential side terminal is the source. Describe.

  Here, a connection relationship between the transistors 1 to 8, the node 11, and the node 12 in the shift register circuit 10 illustrated in FIG. 1 will be described.

  Node 11 is a conductive path connecting transistors 1, 2, 3, 7, and 8. Specifically, the node 11 is connected to the gate of the transistor 1, the drain of the transistor 2, the gate of the transistor 3, the drain of the transistor 7, and the source of the transistor 8.

  Node 12 is a conductive path connecting transistors 1, 2, 4 to 6. Specifically, the node 12 is connected to the drain of the transistor 1, the gate of the transistor 2, the drain of the transistor 4, the source of the transistor 5, and the gate of the transistor 6.

  The transistor 1 has a node 11 connected to the gate, a node 12 connected to the drain, and a low potential terminal connected to the source. The transistor 1 is turned on when the potential of the node 11 is higher than a predetermined threshold. As a result, the potential of the node 12 is lowered to “VGL”.

  In the transistor 2, the node 12 is connected to the gate, the node 11 is connected to the drain, and the low potential terminal is connected to the source. The transistor 2 is turned on when the potential of the node 12 is higher than a predetermined threshold. As a result, the potential of the node 11 is lowered to “VGL”.

In the transistor 3, the node 11 is connected to the gate, the input terminal of “CLK ₁ ” is connected to the drain, the output terminal of “OUT ₁ ” is connected to the source, and the drain of the transistor 6 is connected. The transistor 3 is turned on when the potential of the node 11 is higher than a predetermined threshold value. As a result, “CLK ₁ ” is output as “OUT ₁ ”.

  In the transistor 4, the “in” input terminal is connected to the gate, the node 12 is connected to the drain, and the low potential terminal is connected to the source. The transistor 4 is turned on when the potential of “in” is higher than a predetermined threshold value. As a result, the potential of the node 12 is lowered to “VGL”.

In the transistor 5, the terminal of “CLK ₂ ” is connected to the gate, the high potential terminal is connected to the drain, and the node 12 is connected to the source. The transistor 5 is turned on when the potential of “CLK ₂ ” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the node 12 and the potential of the node 12 rises.

The transistor 6 has a gate connected to the node 12, a drain connected to the source of the transistor 3, and a source connected to the low potential terminal. The transistor 6 is turned on when the potential of the node 12 is higher than a predetermined threshold value. As a result, the potential at the source of the transistor 3, that is, the output terminal of “OUT ₁ ” is lowered to “VGL”.

In the transistor 7, the input terminal “OUT ₂ ” is connected to the gate, the node 11 is connected to the drain, and the low potential terminal is connected to the source. The transistor 7 is turned on when the potential of “OUT ₂ ” is higher than a predetermined threshold value. As a result, the potential of the node 11 is lowered to “VGL”.

  In the transistor 8, the input terminal of the signal “in” is connected to the gate, the high potential terminal is connected to the drain, and the node 11 is connected to the source. The transistor 8 is turned on when the potential of the signal “in” is higher than a predetermined threshold, and electrically connects the high potential terminal and the node 11. In such a case, “VGH” is supplied to the node 11 and the potential of the node 11 rises.

  Here, the current flowing between the drain and the source of each of the transistors 1 to 8 changes according to the potential between the gate and the source. Therefore, each of the transistors 1 to 8 is completely turned on when the potential of the gate is sufficiently higher than a predetermined threshold, but is completely turned on when it is not sufficiently higher than the predetermined threshold. Must not. Each of the transistors 1 to 8 is completely turned off when the gate potential is sufficiently lower than the predetermined threshold value, but is completely turned off when the gate potential is not sufficiently lower than the predetermined threshold value. It is not turned off.

  For example, FIG. 2 is a graph illustrating current characteristics of a transistor. In the graph shown in FIG. 2, the horizontal axis represents the potential Vg (V: Volt) between the gate and source of each transistor 1 to 8, and the vertical axis represents the current Id (A: Ampere) between the drain and source in logarithm. did. As shown in FIG. 2, when the potential Vg is sufficiently low, each of the transistors 1 to 8 is in an off state in which almost no current Id flows.

  Further, each of the transistors 1 to 8 is in an on (low) state in which the current Id flows when the potential Vg is not sufficiently low. Each of the transistors 1 to 8 is in an on (medium) state where the current Id does not sufficiently flow when the potential Vg is not sufficiently high. Further, when the potential Vg is sufficiently high, each of the transistors 1 to 8 is saturated with the current Id and is turned on (high), which is a complete on state.

  Therefore, in the conventional shift register circuit, when the potential applied to the gates of the transistors 1 to 8 is not sufficiently higher than a predetermined threshold value, the transistors 1 to 8 are not in the on (high) state. May cause malfunction. In addition, the conventional shift register circuit may not be turned off when the potential applied to the gates of the transistors 1 to 8 is not sufficiently lower than a predetermined threshold value, which may cause malfunction.

On the other hand, the shift register circuit 10 of the present invention lowers the potential of the node 12 not according to the potential of “OUT ₁ ” but according to the potential of the node 11. As a result, the shift register circuit 10 can reliably reduce the potential of the node 12 when outputting “OUT ₁ ”, and can prevent the signal output from dropping by keeping the potential of the node 11 sufficiently high. be able to.

Specifically, the shift register circuit 10 includes a transistor 2 that decreases the potential of the node 11 as the potential of the node 12 increases, and a transistor 1 that decreases the potential of the node 12 as the potential of the node 11 increases. And have. The shift register circuit 10 includes a transistor 3 that outputs “CLK ₁ ” to “OUT ₁ ” as the potential of the node 11 increases. Here, when “CLK ₁ ” flows in the transistor 3, the potential of the node 11 rises due to the bootstrap effect. As a result, the potential of the node 12 is lowered, the transistor 2 is surely turned off, and the potential of the node 11 is raised. Therefore, the shift register circuit 10 can prevent a decrease in the potential of “CLK ₁ ”.

[Operation Flow of Shift Register Circuit 10]
The operation flow of the shift register circuit 10 will be described. First, signals input to the shift register circuit 10 will be described with reference to FIG. FIG. 3 is a diagram for explaining a signal waveform input to the shift register circuit. For example, in the example illustrated in FIG. 3, for example, “VST” (vertical scan start signal: Vertical Start) is input to the shift register circuit 10 as “in”, and “CLK ₁ ” and “CLK ₂ ”. Is entered.

Here, “VST” is a signal that is input to the shift register circuit 10 as “in” when there is no other shift register circuit in the preceding stage of the shift register circuit 10, and a plurality of shift registers receive the signal. It is a signal which shows the start of the process to transmit. “CLK ₁ ” is a first clock signal whose potential periodically changes from VGH to VGL, and indicates the timing at which the shift register circuit 10 outputs “OUT ₁ ” to the next-stage shift register circuit. Signal. “CLK ₂ ” is a second clock signal, which is a clock signal synchronized with the timing input to “in” in the shift register shown in FIG. In the following description, “CLK ₂ ” is a signal obtained by inverting the phase of “CLK ₁ ”.

Next, the operation of the shift register circuit 10 when each signal is input will be described with reference to FIG. FIG. 4 is a diagram for explaining the operation of the shift register circuit. In FIG. 4, the input waveforms of “CLK ₁ ”, “CLK ₂ ”, and “in” input to the shift register circuit 10, the potential changes of the nodes 11 and 12, and “OUT ₁ ”, “ The waveform of “OUT ₂ ” is shown.

  Further, in FIG. 4, the range in which each of the transistors 1 to 8 is in the on (high) state is indicated by shading, the range in which the on (medium) state is indicated by dark stippling, and the range in which the on (low) state is indicated. Shown in light stippling. The range in which each of the transistors 1 to 8 is turned off is shown in white. Further, in the state before T1 in FIG. 4, it is assumed that the potential of the node 11 is “VGL” and the potential of the node 12 is “VGH”.

In FIG. 4, “in” synchronized with “CLK ₂ ” whose potential changes periodically is input to output “OUT ₁ ”, and the output is stopped by “OUT ₂ ” input from the shift register circuit at the subsequent stage. A series of flow is shown. Here, the above series of flows will be specifically described using the states of the transistors 1 to 8 in the period shown by T1 to T11 in FIG.

Specifically, T1 is the stage prior to the "in" signal is input, T2, the potential of "CLK _1" is "VGL" potential "VGH" in "CLK _2", and " This is a period during which an "in" pulse is input.

T3 is a period in which the potential of “CLK ₁ ” and “CLK ₂ ” is “VGL” after “in” is input, and T4 is the potential of “CLK ₁ ” and “CLK ₂ ”. ”Is a period in which the potential becomes“ VGL ”. T5 is a period in which the potentials of “CLK ₁ ” and “CLK ₂ ” are “VGL” after “OUT ₁ ” is output, and T6 is the potential of “CLK ₁ ”. This is a period during which the potential of “CLK ₂ ” is “VGH”. T7 to T11 are periods in which the potential of “CLK ₂ ” periodically repeats “VGL” and “VGH” after “OUT ₂ ” is input.

For example, from T1 before T1 in FIG. 4, when the potential of “CLK ₂ ” periodically changes to “VGH” and “VGL”, “VGH” is periodically transferred to the node 12 during the “VGH” period. Since the potential of the node 12 is maintained at “VGH”, the transistors 2 and 6 are turned on (high), and the potentials of the node 11 and OUT ₁ are “VGL”.

Subsequently, at T < _b > ₂ in FIG. 4, the potential of “CLK ₁ ” is “VGL”, and the potential of “CLK ₂ ” is “VGH”. Here, since an “in” pulse is input to the transistor 4, the transistor 4 is turned on. Further, although “CLK ₂ ” is input to the transistor 5, the transistor 5 is turned on (medium) by the potential of the node 12. Then, the node 12 is supplied with “VGH” through the transistor 5 in the on (medium) state, and is pulled down to “VGL” through the transistor 4 in the on (high) state. As a result, the potential of the node 12 becomes an intermediate value lower than “VGH”, so that the transistors 2 and 6 are turned on (medium).

  On the other hand, when the “in” pulse is input, the transistor 8 is turned on (high), so that “VGH” is supplied to the node 11 and the potential of the node 11 is increased. As described above, the potential of the node 12 is an intermediate potential that is low from “VGH” as described above, but is gradually lowered to “VGL” by the transistors 1 and 4, so that the transistor 2 is turned on (low) from the on (medium) state. Change to state. Therefore, the potential of the node 11 is in a high state higher than GND (ground). The potential of the node 12 is supplied with “VGH” through the transistor 5 in the on (medium) state, while the transistor 1 in the on (medium) state and the transistor 4 in the on (high) state. Therefore, it is lowered to “VGL”, so that the Low state is lower than GND.

Further, at T3 in FIG. 4, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, and “in” is “VGL”. Then, the transistors 4, 5, and 8 are turned off. For this reason, the supply of “VGH” to the node 12 is cut off, and the voltage drop of the node 12 by the transistor 4 is suppressed, but the transistor 1 continues to pull down to “VGL”.

4, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGL”, and the potential of “in” is “VGL”. The transistor 8 is off. In such a case, when “CLK ₁ ” is applied from the drain to the source of the transistor 3, a bootstrap effect occurs, and the potential of the node 11 rises due to coupling.

  Then, since the transistor 1 is turned on (high), the potential of the node 12 is lowered to “VGL”, so that the transistor 2 is turned off. Then, the potential of the node 11 rises by about 1.3 to 1.5 times with respect to “VGH”, so that the transistor 1 is turned on (high).

Here, since the transistor 5 is in the off state, “VGH” is not supplied to the node 12. For this reason, the potential of the node 12 becomes the same Low state as “VGL”. Further, since the transistor 3 is turned on (high) state, a pulse of "CLK _1" is output as "OUT _1".

As described above, the shift register circuit 10 includes the transistor 1 that electrically connects the node 12 and the low potential terminal in accordance with the potential of the node 11, and when the potential of the node 11 rises, the node 12 The potential of is lowered. Therefore, the shift register circuit 10 can set the potential of the node 12 to the low state when outputting “OUT ₁ ”.

Further, the shift register circuit 10 raises the potential of the node 11 due to the bootstrap effect when “CLK ₁ ” flows from the drain to the source of the transistor 3, so that the transistor 1 is turned on (high), and the node 1 The potential of 12 is further lowered. As a result, the transistor 2 is completely turned off, so that the potential of the node 11 can be maintained high. As a result, the shift register circuit 10 can stabilize the output of a signal transmitted to the next circuit.

Further, at T5 in FIG. 4, the potential of “CLK ₁ ” is “VGL”, and the potential of “CLK ₂ ” is “VGL”. Therefore, when the transistor 3 is pulled back to the low potential of “CLK ₁ ” from the source to the drain, the node 11 returns to the high state that is slightly higher than the GND due to the coupling, and the transistor 1 is turned on (medium). Become. Further, at T5 in FIG. 5, since the transistor 5 is in an off state, “VGH” is not supplied to the node 12, and as a result, the potential of the node 12 maintains the same Low state as “VGL”. Further, the potential of “OUT ₁ ” is also “VGL”.

Further, at T6 in FIG. 4, the potential of “CLK ₁ ” is “VGL”, and the potential of “CLK ₂ ” is “VGH”. In such a case, the transistor 5 is turned on (high) by the potential of “CLK ₂ ”, so that “VGH” is supplied to the node 12, and as a result, the potential of the node 12 rises and is slightly lower than GND. It becomes a high state. Therefore, the transistors 2 and 6 are turned on (medium).

Further, at T6 in FIG. 4, when a pulse of “OUT ₂ ” is output from the shift register circuit in the next stage, the transistor 7 is turned on (high) by the potential of “OUT ₂ ”. Here, since the transistor 8 is in the off state, the node 11 is not supplied with “VGH”. As a result, the potential of the node 11 is pulled down via the transistors 2 and 7 and is in a Low state substantially the same as “VGL”. Further, since the potential at the output terminal of “OUT ₁ ” is maintained at “VGL” via the transistor 6 in the on (medium) state, the shift register circuit 10 can further stabilize the state of the output signal. .

Further, at T7 in FIG. 4, the potential of “CLK ₁ ” is “VGH”, and the potential of “CLK ₂ ” is “VGL”. In such a case, since the potential of “CLK ₂ ” is “VGL”, the transistor 5 is turned off, and the potential of “in” and the potential of the node 11 are “VGL”. 4 is also turned off. As a result, the potential of the node 12 is kept at a High state slightly higher than GND without being pulled down by “VGL”. Therefore, the transistors 2 and 6 are turned on (medium), and the potentials of the node 11 and “OUT ₁ ” are maintained at “VGL”.

Further, at T8 in FIG. 4, the potential of “CLK ₁ ” is “VGL”, and the potential of “CLK ₂ ” is “VGH”. In such a case, although the potential of “CLK ₂ ” is “VGH”, since the node 12 is in the high state, the transistor 5 is turned on (medium). Then, “VGH” is supplied to the node 12, the potential of the node 12 is increased, and a high state close to “VGH” is obtained. As a result, the transistors 2 and 6 are kept on (high), and the potentials of the node 11 and “OUT ₁ ” are maintained at “VGL”.

After that, at T9 in FIG. 4, the potential of “CLK ₁ ” is “VGH”, and the potential of “CLK ₂ ” is “VGL”. In such a case, since the potential of the node 12 is in a high state close to “VGH”, the transistor 2 is turned on (high), and the potential of the node 11 is maintained at “VGL”, so that the transistor 3 is turned off. As a result, “OUT ₁ ” is not output.

Further, at T10 in FIG. 4, the potential of “CLK ₁ ” is “VGL”, and the potential of “CLK ₂ ” is “VGH”. In such a case, although the potential of “CLK ₂ ” is “VGH”, since the node 12 is in a high state close to “VGH”, the transistor 5 is turned on (low). Then, “VGH” is supplied to the node 12, and as a result, the potential of the node 12 is kept in a high state. Note that, at T11 in FIG. 4, “OUT ₁ ” is not output, and the potential of the node 12 is kept in a high state close to “VGH”, similarly to T9 in FIG.

Here, when “in” is input simultaneously with “CLK ₂ ” after T 8 in FIG. 4, the shift register circuit 10 operates in the same manner as T 2 to T 7 in FIG. “OUT ₁ ” can be output to the shift register circuit 10.

[Simulation result of shift register circuit 10]
Next, simulation results of the shift register circuit 10 will be described with reference to FIG. FIG. 5 is a diagram for explaining an example of the simulation. The graph shown in FIG. 5 is a result of simulating “in” input to the shift register circuit 10, “OUT ₁ ” output from the shift register circuit 10, and potential transitions of the nodes 11 and 12. In the example shown in FIG. 5, the horizontal axis represents time, the vertical axis represents “OUT ₁ ”, and the potentials of the nodes 11 and 12 are plotted.

For example, in FIG. 5 in t12 to t13, "OUT _1", the node 11, there is not much change in the potential of the node 12. 5, when an “in” signal pulse is input, the potential of the node 11 increases and the potential of the node 12 decreases. At T15 in FIG. 5, the potential of the node 11 is further improved due to the bootstrap effect, and the potential of the node 12 is further lowered. Therefore, the shift register circuit 10 outputs “OUT ₁ ” with no potential drop. After that, at T16 and T17 in FIG. 5, the potential of the node 11 drops and the potential of the node 12 rises, so that the shift register circuit 10 can change to a standby state.

[Effect of the shift register circuit 10]
As described above, the shift register circuit 10 includes the transistor 1 that decreases the potential of the node 12 in response to the increase in the potential of the node 11 and the potential of the node 11 in response to the increase in the potential of the node 12. And a transistor 2 for lowering. The shift register circuit 10 includes the transistor 3 that raises the potential of the node 11 by the bootstrap effect when outputting “OUT ₁ ” in response to the rise of the potential of the node 11. For this reason, the shift register circuit 10 can prevent a potential drop of “OUT ₁ ”.

Further, the shift register circuit 10 includes the transistor 4 that lowers the potential of the node 12 in response to the rise of the potential of “in”. As described above, the shift register circuit 10 lowers the potential of the node 12 when “in” is input. Therefore, as a result of increasing the potential of the node 11, the potential drop of “OUT ₁ ” can be further prevented. .

The shift register circuit 10 includes the transistor 5 that raises the potential of the node 12 in response to the rise of the potential of “CLK ₂ ”. Therefore, the shift register circuit 10 can stabilize the operation in the non-selected state in which “OUT ₁ ” is not output.

In addition, the shift register circuit 10 includes a transistor 6 that lowers the potential of the output terminal of “OUT ₁ ” in response to the potential of the node 12 rising. Therefore, the shift register circuit 10 can prevent the output of “OUT ₁ ” erroneously in the non-selected state.

In addition, the shift register circuit 10 includes the transistor 7 that lowers the potential of the node 11 in response to the rise of the potential of “OUT ₂ ”. Therefore, the shift register circuit 10 can reliably transition to the non-selected state when the shift register circuit at the subsequent stage outputs a signal.

[Scope of application]
For example, the shift register circuit 10 exemplified in the above embodiment is suitably applied to a driver circuit that operates an image display device using a liquid crystal panel or an organic EL (Electronic Luminescent) panel. The shift register circuit 10 can also be applied to circuits other than the driver circuit described above. The shift register circuit 10 can be applied to an arbitrary device such as a sensor device, a light emitting element array, or a thermal head having a plurality of transistors and a driver circuit for sequentially driving each element.

(Application to LCD panel)
In the following description, an example in which the shift register circuit 10 is applied to a driver circuit that operates an image display apparatus using a liquid crystal panel will be described as an application example of the shift register circuit 10.

  FIG. 6 is a first diagram illustrating an application example of the shift register circuit. In the example illustrated in FIG. 6, the image display device 50 includes a control circuit 51 and a panel 52. The image display device 50 includes a light source device such as a backlight, a color filter substrate, and polarizing plates having different polarization directions. However, in FIG. 6, the description thereof is omitted for easy understanding.

  The control circuit 51 is provided on, for example, an FPC (Flexible printed circuits) disposed on the panel 52 or is provided on an external circuit board of the panel 52, and a control signal for driving the panel 52 is provided. Output to the drive circuit 55. In FIG. 6, illustration of the FPC or the external circuit board is omitted.

  In addition, a liquid crystal panel is used for the panel 52, and it is composed of a pair of substrates. For example, the panel 52 is composed of a pair of glass substrates including an array substrate in which a thin film transistor is formed in the active area 57 and a color filter substrate facing the array substrate. A peripheral portion 54 is formed around the array substrate in the active area 57. The peripheral portion 54 is provided with a driving circuit 55 and a scanning line driving circuit 56, and the scanning line driving circuit 56 is formed on the glass of the array substrate. The driving circuit 55 and the scanning line driving circuit 56 are connected by a scanning line control line 53.

  The drive circuit 55 is composed of a semiconductor element for driving, and includes a signal line drive circuit for outputting an image signal to a data line extending on the active area, a scanning line control circuit, a counter potential drive circuit, and the like. The drive circuit 55 is mounted on the peripheral portion 54 of the active area 57 by a COG (Chip On Glass) method.

  Further, the shift register circuit 10 described in the first embodiment is applied to the scanning line driving circuit 56 provided in the peripheral portion 54 of the panel 52. The drive circuit 55 is connected to the scan line drive circuit 56 through the scan line control line 53, and outputs a control signal to the shift register circuit 10 through the scan line control line 53. The shift register circuit 10 is formed integrally with the peripheral portion 54 of the panel 52 on the array substrate.

  The active area 57 has a plurality of pixels 58 arranged in a matrix. Specifically, in the active area 57, a plurality of data lines are extended in the column direction, and a plurality of scanning lines are extended in the row direction. In the active area 57, pixels 58 are formed corresponding to the intersections of the data lines and the scanning lines.

  Here, the pixel 58 includes a thin film transistor 59 that operates as an active element, and a pixel electrode 60. The image display device 50 displays an image by controlling liquid crystal molecules with a voltage applied between a pixel electrode 60 provided on the array substrate and a common electrode (not shown) provided on the color filter substrate. Here, the panel 52 is described in a vertical electric field method in which the pixel electrode 60 is provided on the array substrate and the common electrode is provided on the color filter substrate. Alternatively, a horizontal electric field method in which a pixel electrode 60 and a common electrode are provided may be used.

  The scanning line driving circuit 56 is configured by a circuit in which shift register circuits 10, 10a to 10c similar to the shift register circuit 10 according to the first embodiment are connected in multiple stages. Note that although the scanning line driving circuit 56 includes a plurality of shift register circuits in addition to the shift register circuits 10 and 10a to 10c, the description is omitted in FIG. 6 for easy understanding.

  Here, the scanning line driving circuit 56 inputs a signal output from each of the shift register circuits 10, 10 a to 10 c to the next-stage shift register circuit, and inputs it to a scanning line extending on the active area 57. For this reason, when a control signal is input from the drive circuit 55 via the scanning line control line 53, the scanning line driving circuit 56 applies voltages to the scanning lines on the active area 57 in order from the top. Apply.

For example, when receiving the control signal, the shift register circuit 10 outputs OUT ₁ to the shift register circuit 10a and applies a voltage to the first-stage scanning line. Next, the shift register circuit 10a outputs OUT ₁ to the next-stage shift register circuit, and applies a voltage to the second-stage scanning line. At this time, since the shift register circuit 10a outputs OUT ₂ to the shift register circuit 10, output of signals to the shift register circuit 10 is stopped, and application of voltage to the first scanning line is stopped. As a result, the scanning line driving circuit 56 sequentially applies a voltage to each scanning line on the active area 57.

  In the thin film transistor 59, a data line and a source corresponding to the position where the pixel 58 is formed are connected, and a scanning line and a gate corresponding to the position where the pixel 58 is formed are connected. When a voltage is applied to the corresponding scanning line from the scanning line driving circuit 56 and a voltage is applied to the corresponding data line from the driving circuit 55, the voltage applied to the data line is passed through the thin film transistor 59. Applied to the pixel electrode 60.

  Here, when the scanning line driving circuit 56 is configured by the shift register circuit 10 according to the first embodiment, it is possible to prevent the voltage applied to each scanning line by each shift register circuit 10 from being lowered. As a result, the image display device 50 can prevent a decrease in the voltage applied to each pixel 58 even when the number of scanning lines increases due to the increase in the size of the active area 57 or the densification of the pixels 58. Can work.

  Note that FIG. 6 illustrates an example in which the shift register circuit 10 is applied to an image display device using a liquid crystal panel. However, the embodiment is not limited to this. For example, the shift register circuit 10 may be applied to an image display device using an organic EL panel. For example, FIG. 7 is a second diagram illustrating an application example of the shift register circuit 10.

(Application to organic EL)
In the example illustrated in FIG. 7, the image display device 70 that includes the scanning line driving circuit 56 including the plurality of shift register circuits 10 and 10 a and uses an organic EL panel is described. Further, in the example shown in FIG. 7, for the sake of easy understanding, an example in which the scanning line driving circuit 56 includes the shift register circuits 10 and 10 a is described. It suffices to have a circuit. Note that the shift register circuit 10 is integrally formed on the peripheral portion of the panel 52 on the array substrate, similarly to the image display device 50 using the above-described liquid crystal panel.

  In the example shown in FIG. 7, the pixel 58 includes a light emitting element 80 whose anode is electrically connected to the constant potential supply circuit 71, and a transistor 81 whose one electrode is connected to the cathode of the light emitting element 80. The pixel 58 includes an n-type thin film transistor, and includes a driver element 83 whose drain is connected to the drain of the transistor 82 and whose source is electrically connected to the power supply circuit 72. In addition, the pixel 58 includes a transistor 82 that controls the conduction state between the gate and the drain of the thin film transistor that forms the driver element 83, and a capacitance 84.

  In the example shown in FIG. 7, a constant potential supply circuit 71 for supplying a constant on potential to the anode of the light emitting element 80 provided in each pixel 58, and a transistor 81 provided in the pixel 58 via a control line. And a power supply circuit 72 for supplying an ON potential or a zero potential to the source of the driver element 83.

  The light emitting element 80 has a mechanism for emitting light by current injection, and is formed of, for example, an organic EL element. The organic EL device includes an anode layer and a cathode layer formed of Al, Cu, ITO (Indium Tin Oxide), and the like, and phthalocyanine, trisaluminum complex, benzoquinolinolato, and beryllium complex between the anode layer and the cathode layer. And a light emitting layer formed of an organic material such as an organic material, and has a function of generating light by recombination of holes and electrons injected into the light emitting layer.

  The transistor 81 has a function of controlling conduction between the light emitting element 80 and the driver element 83, and is formed of an n-type thin film transistor in the first embodiment. That is, the drain and the source of the thin film transistor are connected to the light emitting element 80 and the driver element 83, respectively, while the gate is electrically connected to the drive control circuit 73, and supplied from the drive control circuit 73. Based on the potential, the conduction state between the light emitting element 80 and the driver element 83 is controlled.

  The driver element 83 has a function for controlling the current flowing through the light emitting element 80. Specifically, the driver element 83 has a function of controlling a current flowing through the light emitting element 80 in accordance with a potential difference equal to or greater than a threshold value. In the present embodiment, the driver element 83 is formed of an n-type thin film transistor, and controls the light emission luminance of the light emitting element 80 according to the potential difference applied between the gate and the source.

  In such a pixel 58, charges are accumulated in the capacitance 84 by the voltage applied to the signal line by the drive circuit 55. While the drive control circuit 73 applies a voltage to the gate of the transistor 81, a current corresponding to the charge accumulated in the capacitance 84 flows to the light emitting element 80, and the light emitting element 80 emits light.

  As described above, even when each pixel 58 includes the light emitting element 80, the scanning line driving circuit 56 connects a shift register circuit similar to the shift register circuit 10 for each scanning line, and each shift register has a pixel. An output signal is output to the scanning line. For this reason, the image display device 70 can operate normally because the voltage applied to each pixel 58 can be prevented from decreasing even when the pixel 58 has an organic EL panel.

1 to 8 transistors 10 shift register circuits 11 and 12 nodes

Claims (8)

The gate is connected to the first conductive path, the drain is connected to the second conductive path, and the source is connected to the low potential terminal. A first transistor that lowers the potential of the second conductive path;
In response to an increase in potential of the second conductive path, the gate being connected to the second conductive path, the drain being connected to the first conductive path and the source being connected to the low potential terminal. A second transistor that lowers the potential of the first conductive path;
The first clock signal is input, the gate being connected to the first conductive path, the input terminal of the first clock signal being connected to the drain, and the output terminal outputting the output signal being connected to the source. And a third transistor that outputs an output signal from the output terminal in response to a rise in potential of the first conductive path.   The gate is connected to the input terminal of the input signal, the drain is connected to the second conductive path, and the source is connected to the low potential terminal. The shift register circuit according to claim 1, further comprising a fourth transistor that drops the potential.   In response to the input of the second clock signal, the gate is connected to the input terminal of the second clock signal, the source is connected to the second conductive path, and the drain is connected to the high potential terminal. The shift register circuit according to claim 1, further comprising a fifth transistor that raises a potential of the second conductive path.   The output signal in response to an increase in potential of the second conductive path, the gate being connected to the second conductive path, the output terminal being connected to the drain and the low potential terminal being connected to the source. 4. The shift register circuit according to claim 1, further comprising: a sixth transistor that drops a potential of a terminal that outputs the signal. 5.   Output of a signal output by the other circuit, the gate being connected to the output terminal of the signal output from the other circuit, the drain being connected to the first conductive path and the source being connected to the low potential terminal 5. The shift register circuit according to claim 1, further comprising: a seventh transistor that lowers the potential of the first conductive path in response to the signal.   The first conductive path according to the input of the input signal, wherein the gate is connected to the input terminal of the input signal, the source is connected to the first conductive path, and the drain is connected to the high potential terminal. 6. The shift register circuit according to claim 1, further comprising an eighth transistor that raises the potential of. A driver circuit having the shift register circuit according to any one of claims 1 to 6;
An image display device comprising: a display panel having a light emitting element that emits light according to a signal output from the driver circuit. A driver circuit having the shift register circuit according to any one of claims 1 to 6;
An image display device comprising: a liquid crystal panel that displays an image according to a signal output from the driver circuit.

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