TWI818761B - Sweep voltage generator - Google Patents

Abstract

A sweep voltage generator is provided. The sweep voltage generator includes a first voltage regulator, a second voltage regulator, an output stage circuit, and a voltage regulator. The first voltage regulator has a first node, and adjusts a voltage level of the first node according to a lighting control signal, a first control signal and a second control signal. The second voltage regulator has a second node, and adjusts voltage levels of the first node and the second node according to the lighting control signal, the first control signal and the second control signal. The output stage circuit has an output node, and generates a sweep signal at the output node according to the voltage level of the first node. The voltage regulator is configured to regulate the output node according to a clock signal and the lighting control signal.

Description

Ramp voltage generator

The present invention relates to a voltage generator, and in particular to a ramp voltage generator.

In conventional display technology, the pixel circuit usually receives a ramp signal from an external digital-to-analog converter, and uses the ramp signal and written data to determine the current width or light-emitting time of the light-emitting diode. However, in the existing ramp voltage generator, the slope of the ramp signal generated by the ramp voltage generator is easily affected by the load variation of the output node and/or the critical voltage variation of the driving transistor, thereby causing the pixel The gray scale control capability of the circuit is reduced.

In view of this, how to effectively compensate for the load variation and/or the critical voltage variation of the driving transistor so that the output waveform of the ramp signal is not affected by the variation, so as to improve the accuracy of the grayscale control of the pixel circuit, will be a problem in this field. Important topics for relevant technical personnel.

The present invention provides a ramp voltage generator that can effectively compensate for load variations and critical voltage variations of drive transistors, so that the output waveform of the ramp signal is not affected by variations and increases the use of pulse-width modulation. , PWM) control of the grayscale control accuracy of the pixel circuit.

The ramp voltage generator of the present invention includes: a first voltage regulator, a second voltage regulator, an output stage circuit and a voltage regulator. The first voltage regulator has a first node. The first voltage regulator is coupled to the system low voltage and adjusts the voltage level of the first node according to the lighting control signal, the first control signal and the second control signal. The second voltage regulator has a second node. The second voltage regulator is coupled to the first node, the system low voltage, the system high voltage and the reference voltage, and adjusts the voltage levels of the first node and the second node according to the lighting control signal, the first control signal and the second control signal. Bit. The output stage circuit has an output node. The output stage circuit is coupled to the first node and generates a ramp signal at the output node according to the voltage level of the first node. The voltage regulator is coupled to the system high voltage and the output node, and is used to regulate the voltage of the output node according to the clock signal and the lighting control signal.

Based on the above, the ramp voltage generator of the embodiment of the present invention can effectively compensate for the load variation and the critical voltage variation of the driving transistor, and prevent the output waveform of the ramp signal from being affected by the variation, thereby increasing the use of pulse width modulation control. The precision of grayscale control of the pixel circuit.

The word "coupling (or connection)" used throughout the specification of this case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if a first device is coupled (or connected) to a second device, it should be understood that the first device can be directly connected to the second device, or the first device can be connected through other devices or other devices. A connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers are used in the drawings and embodiments to represent the same or similar parts. Elements/components/steps using the same numbers or using the same terms in different embodiments can refer to the relevant descriptions of each other.

FIG. 1 is a schematic diagram of a ramp voltage generator according to an embodiment of the present invention. Referring to FIG. 1 , the ramp voltage generator 100 includes a voltage regulator 110 , a voltage regulator 120 , an output stage circuit 130 and a voltage regulator 140 . In this embodiment, the voltage regulator 110 has a node P1 and a node P3. The voltage regulator 110 is coupled to the system low voltage VL. Among them, the voltage regulator 110 can use the light-emitting control signal EM, the control signal S1[n] (that is, the first control signal) and the next-stage control signal S1[n+1] (that is, the second control signal) to Adjust the voltage levels of node P1 and node P3.

Specifically, the voltage regulator 110 includes transistors T1 to T3 and a capacitor C1. The first terminal of the transistor T1 is coupled to the system low voltage VL, the second terminal of the transistor T1 is coupled to the node P1, and the control terminal of the transistor T1 receives the control signal S1[n]. The first terminal of the transistor T2 is coupled to the system low voltage VL, the second terminal of the transistor T2 is coupled to the node P3, and the control terminal of the transistor T2 receives the lighting control signal EM. The first terminal of the transistor T3 is coupled to the node P1, the second terminal of the transistor T3 is coupled to the node P3, and the control terminal of the transistor T3 receives the control signal S1[n+1] of the next stage. Capacitor C1 is coupled between system low voltage VL and node P1.

Voltage regulator 120 has node P2 and node P4. The voltage regulator 120 is coupled to the node P1, the system low voltage VL, the system high voltage VH, and the reference voltage VREF. The voltage regulator 120 can adjust the voltage levels of the nodes P1, P2 and P4 according to the light emission control signal EM, the control signal S1[n] and the next-stage control signal S1[n+1].

Specifically, the voltage regulator 120 includes transistors T4 to T9 and a capacitor C2. The first terminal of the transistor T4 is coupled to the system high voltage VH, the second terminal of the transistor T4 is coupled to the node P2, and the control terminal of the transistor T4 receives the control signal S1[n]. The first terminal of the transistor T5 is coupled to the node P2, and the control terminal of the transistor T5 receives the control signal S1[n+1] of the next stage. The first terminal of the transistor T6 is coupled to the node P1, the second terminal of the transistor T6 is coupled to the second terminal of the transistor T5, and the control terminal of the transistor T6 receives the light-emitting control signal EM.

The first terminal of the transistor T7 is coupled to the second terminal of the transistor T5, the second terminal of the transistor T7 is coupled to the node P4, and the control terminal of the transistor T7 is coupled to the node P2. The first terminal of the transistor T8 is coupled to the reference voltage VREF, the second terminal of the transistor T8 is coupled to the node P4, and the control terminal of the transistor T8 receives the next-stage control signal S1[n+1]. The first terminal of the transistor T9 is coupled to the system low voltage VL, the second terminal of the transistor T9 is coupled to the node P4, and the control terminal of the transistor T9 receives the lighting control signal EM. Capacitor C2 is coupled between system low voltage VL and node P2.

On the other hand, the output stage circuit 130 has an output node OUT. Among them, the output stage circuit 130 includes a transistor T12 (ie, a driving transistor). The first terminal of the transistor T12 is coupled to the output node OUT, the second terminal of the transistor T12 is coupled to the node P3, and the control terminal of the transistor T12 is coupled to the node P1. It should be noted that the transistor T12 in this embodiment may be formed in a source follower configuration (or architecture).

Specifically, the output stage circuit 130 can generate the ramp signal SWEEP[n] through the output node OUT according to the voltage level of the node P1 of the voltage regulator 110 to the corresponding pixel circuit (not shown), where n is a derivative.

Regulator 140 has node P5. The voltage regulator 140 is coupled to the system high voltage VH and the output node OUT of the output stage circuit 130 . The voltage regulator 140 may perform a voltage stabilizing action on the output node OUT according to the light emission control signal EM and the clock signal CK (or the reverse clock signal XCK). An external clock generator (not shown) can provide a periodically changing clock signal CK or a reverse clock signal XCK to the ramp voltage generator 100 .

Specifically, the voltage regulator 140 includes transistors T10 and T11 and a capacitor C3. The first terminal of the transistor T10 is coupled to the system high voltage VH, the second terminal of the transistor T10 is coupled to the node P5, and the control terminal of the transistor T10 receives the lighting control signal EM. The first terminal of the transistor T11 is coupled to the system high voltage VH, the second terminal of the transistor T11 is coupled to the output node OUT of the output stage circuit 130, and the control terminal of the transistor T11 is coupled to the node P1. The first terminal of the capacitor C3 can receive the clock signal CK (or the reverse clock signal XCK), and the second terminal of the capacitor C3 is coupled to the node P5.

By the way, in terms of the design of the transistors T1 to T12, the transistors T1 to T6 and the transistors T8 to T12 in this embodiment can be P-type transistors, and the transistor T7 can be N-type. A transistor is taken as an example, but the embodiment of the present invention is not limited to this. In addition, in this embodiment, the voltage level of the reference voltage VREF may be higher than the voltage level of the system high voltage VH, and the voltage level of the system high voltage VH may be higher than the voltage level of the system low voltage VL.

Regarding the operation details of the ramp voltage generator 100, please refer to FIG. 2 and FIG. 3A to FIG. 3D. FIG. 2 is an operation waveform diagram of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention. FIG. 3A to FIG. 3D is an equivalent circuit diagram of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention.

Referring to FIG. 2 , in this embodiment, the ramp voltage generator 100 can sequentially operate in the reset phase IP, the compensation phase CP, the voltage output phase VOP and the voltage stabilization phase SP. And the reset phase IP, the compensation phase CP, the voltage output phase VOP and the voltage stabilization phase SP do not overlap with each other.

It should be noted that, for convenience of illustration, disconnected transistors are indicated by a cross in FIGS. 3A to 3D , while conductive transistors are indicated by an uncrossed one.

Please refer to Figure 2 and Figure 3A. In the reset phase IP, the clock signal CK and the control signal S1[n] can be set to a low voltage level (equal to the gate low voltage VGL), and the next stage control signal S1 [n+1] and the light emission control signal EM can be set to a high voltage level (equal to the gate high voltage VGH).

In the reset phase IP, the transistors T1, T4, T7, T11 and T12 of the ramp voltage generator 100 are in a conductive state. Specifically, the voltage regulator 120 can provide the system high voltage VH to the node P2 through the conduction path of the transistor T4 according to the pulled-down control signal S1[n], so that the voltage level of the node P2 is correspondingly pulled up. to a voltage value equal to the system high voltage VH, and causes the transistor T7 to be in a conductive state during the reset phase IP.

On the other hand, the voltage regulator 110 can provide the system low voltage VL to the node P1 through the conduction path of the transistor T1 according to the pulled-down control signal S1[n], so that the voltage level of the node P1 corresponds to ground. is pulled down to a voltage value equal to the system low voltage VL, causing the transistor T12 to be in a conductive state during the reset phase IP.

In addition, during the reset phase IP, the voltage regulator 140 can pull down the voltage level of the node P5 according to the clock signal CK through the coupling effect of the capacitor C3, thereby turning on the transistor T11. In this case, the voltage regulator 140 can provide the system high voltage VH to the output node OUT through the conduction path of the transistor T11, so that the ramp signal SWEEP[n] generated by the output stage circuit 130 at the output node OUT is pulled A voltage level up to the system high voltage VH.

Furthermore, the voltage regulator 140 can provide the system high voltage VH to the node P3 through the conduction paths of the transistor T11 and the transistor T12, so that the voltage level of the node P3 is correspondingly pulled up to a voltage value equal to the system high voltage VH. .

Next, please refer to Figure 2 and Figure 3B. In the compensation phase CP, the clock signal CK, the control signal S1[n] and the emission control signal EM can be set to a high voltage level (equal to the gate high voltage VGH), and the lower The control signal S1[n+1] of the first stage can be set to a low voltage level (equal to the gate low voltage VGL).

In the compensation phase CP, the transistors T3, T5, T7, T8 and T12 of the ramp voltage generator 100 are in a conductive state. Specifically, the voltage regulator 120 provides the reference voltage VREF to the node P4 through the conduction path of the transistor T8 according to the lowered control signal S1[n+1], so that the voltage level of the node P4 corresponds to Ground is pulled up to a voltage equal to the reference voltage VREF.

In addition, the voltage regulator 120 can perform a discharge operation on the node P2 through the conduction paths of the transistors T5, T7 and T8, so that the voltage level of the node P2 is adjusted to be equal to the reference voltage VREF and the threshold voltage (Threshold) of the transistor T7. Voltage) The voltage value of the sum of VTH7 (ie, VREF+VTH7).

It is worth mentioning that when the transistors T5 and T7 of the voltage regulator 120 are turned on according to the control signal S1[n+1] of the next stage and the voltage level of the node P2, the transistors T5 and T7 can be turned on according to Diode configuration (Diode Connection) connection method to form a diode. In addition, the voltage regulator 120 can compensate the transistor T7 by detecting the threshold voltage VTH7 of the transistor T7 to achieve a self-compensation effect.

On the other hand, during the compensation phase CP, the voltage regulator 110 can charge the node P1 through the conduction paths of the transistors T3 and T12 and through the system high voltage VH on the output node OUT, so that the node P1 The voltage level is adjusted to a voltage value equal to the sum of the system high voltage VH and the critical voltage VTH12 of the transistor T12 (that is, VH + VTH12), and the voltage level on the node P3 is adjusted to be equal to the system high voltage. The voltage value of the difference between VH and the threshold voltage VTH12 of the transistor T12 (ie, VH-VTH12).

It is worth mentioning that when the transistors T3 and T12 of the voltage regulator 110 are turned on according to the control signal S1[n+1] of the next stage and the voltage level of the node P1, the transistors T3 and T12 can be turned on according to Diode configuration is a method of connecting to form a diode. In addition, the voltage regulator 110 can compensate the transistor T12 (ie, the driving transistor) by detecting the threshold voltage VTH12 of the transistor T12 to achieve a self-compensation effect.

Next, please refer to Figure 2 and Figure 3C. In the voltage output stage VOP, the control signal S1[n] and the next-stage control signal S1[n+1] can be set to a high voltage level (equal to the gate high voltage VGH) , and the light emission control signal EM can be set to a low voltage level (equal to the gate low voltage VGL).

In the voltage output stage VOP, the transistors T2, T6, T7, T9, T10 and T12 of the ramp voltage generator 100 are in a conductive state. Specifically, the voltage regulator 120 can provide the system low voltage VL to the node P4 through the conduction path of the transistor T9 according to the pulled-down light emission control signal EM, so that the voltage level of the node P4 is adjusted to be equal to the system low voltage. The voltage value of voltage VL.

Then, the transistor T7 of the voltage regulator 120 can generate the conduction current IREF according to the voltage level of the node P2 (ie, VREF + VTH7) to determine the node P1 through the conduction paths of the transistors T6, T7 and T9. The current discharge action enables node P1 to generate an output waveform that decreases with a fixed slope.

At this time, the conduction current IREF flowing through the transistor T7 can be expressed as follows: IREF=K7（VREF+VTH7-VL-VTH7）^2

Among them, the above IREF is the current value of the on-current IREF; K7 is the process parameter of the transistor T7; VREF is the voltage value of the reference voltage VREF; VL is the voltage value of the system low voltage VL; VTH7 is the critical voltage of the transistor T7 voltage value.

When the voltage regulator 120 performs a constant current discharge operation on the node P1, the voltage level of the node P1 can be adjusted to a voltage value equal to VH-VTH12-ΔV. Among them, the above-mentioned △V is the voltage difference of node P1 that changes with time in the voltage output stage VOP.

On the other hand, in this embodiment, during the voltage output stage VOP, the voltage regulator 140 can provide the system high voltage VH to the node P5 through the conduction path of the transistor T10 according to the pulled-down light emission control signal EM, thereby The voltage level of the node P5 is adjusted to the voltage value of the system high voltage VH.

In addition, in the voltage output stage VOP, the voltage regulator 110 can provide the system low voltage VL to the node P3 through the conduction path of the transistor T2 according to the pulled-down light emission control signal EM, so that the voltage of the node P3 The level is adjusted to a voltage value equal to the system low voltage VL.

It is worth mentioning that in this embodiment, since the transistor T12 of the output stage circuit 130 is formed in a source follower configuration (or architecture), the first terminal of the transistor T12 (ie, The voltage level on the output node OUT) may follow the voltage level on the control terminal of the transistor T12 (ie, the node P1).

On this basis, the voltage regulator 120 will perform a constant current discharge operation on the node P1, so that the node P1 generates an output waveform that decreases with a fixed slope. The output stage circuit 130 of this embodiment can utilize the structure of a source follower. , causing the transistor T12 to generate a ramp signal SWEEP[n] at the output node OUT that steadily follows the decline of the output waveform of the node P1. At this time, the voltage level of the output node OUT can be adjusted to be equal to the difference between the system high voltage VH and the voltage difference of the node P1 that changes with time in the voltage output stage VOP (that is, VH-ΔV).

In other words, in the voltage output stage VOP, the voltage level of the node P1 and the voltage level of the output node OUT differ by the threshold voltage VTH12 of the transistor T12 .

According to the above description, it can be known that in this embodiment, the ramp voltage generator 100 can effectively compensate for the load variation and the critical voltage variation of the transistors T7 and T12, and make the output waveform of the ramp signal SWEEP[n] It is not affected by variation, thereby increasing the accuracy of grayscale control of pixel circuits controlled by pulse width modulation.

Next, please refer to Figure 2 and Figure 3D. In the voltage stabilization phase SP, the clock signal CK can be set to a low voltage level (equal to the gate low voltage VGL), and the control signal S1[n], the next-level control signal S1[n+1] and the light emission control signal EM can be set to a high voltage level (equal to the gate high voltage VGH).

In the voltage stabilization phase SP, the transistors T11 and T12 of the ramp voltage generator 100 are in a conductive state. Specifically, the voltage regulator 140 can couple the pulled-down clock signal CK to the node P5 through the capacitor C3, and periodically turn on the transistor T11 to provide the system high voltage VH to the output node OUT. Thereby, the voltage regulator 140 can raise the voltage level of the ramp signal SWEEP[n] to the voltage value of the system high voltage VH during the voltage stabilization phase SP to achieve a 50% voltage stabilization period.

To sum up, the ramp voltage generator according to the embodiment of the present invention can effectively compensate for the load variation and the critical voltage variation of the driving transistor, and prevent the output waveform of the ramp signal from being affected by the variation, thereby increasing the use of pulse width modulation. The precision of gray scale control of variable control pixel circuit.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100: Ramp voltage generator 110, 120: Voltage regulator 130:Output stage circuit 140: Voltage regulator C1, C2, C3: capacitor CK: clock signal CP: Compensation stage EM: Luminous control signal IP: reset phase IREF: conduction current OUT: output node P1～P5: nodes S1[n], S1[n+1]: control signal SWEEP[n]: ramp signal SP: Stabilization stage T1～T12: transistor VH: system high voltage VL: system low voltage VGH: gate high voltage VGL: gate low voltage VREF: reference voltage VOP: voltage output stage

FIG. 1 is a schematic diagram of a ramp voltage generator according to an embodiment of the present invention. FIG. 2 is an operation waveform diagram of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention. 3A to 3D are equivalent circuit diagrams of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention.

100: Ramp voltage generator

110, 120: Voltage regulator

130:Output stage circuit

140: Voltage regulator

C1, C2, C3: capacitor

CK: clock signal

EM: Luminous control signal

OUT: output node

P1~P5: nodes

S1[n], S1[n+1]: control signal

SWEEP[n]: ramp signal

T1~T12: transistor

VH: system high voltage

VL: system low voltage

VREF: reference voltage

Claims (11)

A ramp voltage generator includes: a first voltage regulator having a first node, the first voltage regulator being coupled to a system low voltage and based on a lighting control signal, a first control signal and a The second control signal is used to adjust the voltage level of the first node; a second voltage regulator has a second node, the second voltage regulator is coupled to the first node, the system low voltage, and a system high voltage. voltage and a reference voltage, and adjust the voltage levels of the first node and the second node according to the light-emitting control signal, the first control signal and the second control signal; an output stage circuit having an output node, The output stage circuit is coupled to the first node and generates a ramp signal at the output node according to the voltage level of the first node, wherein the output stage circuit uses a source follower; and a stable A voltage regulator is coupled to the system high voltage and the output node for stabilizing the output node according to a clock signal and the lighting control signal. The ramp voltage generator of claim 1, wherein in a reset phase, the first voltage regulator provides the system low voltage according to the first control signal that is pulled down to pull down the first The voltage level of the node. The ramp voltage generator of claim 2, wherein in the reset phase, the second voltage regulator provides the system high voltage according to the first control signal that is pulled down to pull up the second The voltage level of the node. As for the ramp voltage generator of claim 1, in a compensation phase, the first voltage regulator provides the system high voltage according to the pulled-down second control signal to charge the first node. . As for the ramp voltage generator of claim 4, in the compensation phase, the second voltage regulator provides the reference voltage according to the pulled-down second control signal to discharge the second node. As for the ramp voltage generator of claim 1, in a voltage output stage, the second voltage regulator provides the system low voltage according to the pulled-down light-emitting control signal to discharge the first node. , and the output stage circuit generates the pulled-down ramp signal according to the voltage level of the first node that is pulled down. As for the ramp voltage generator described in claim 1, in a voltage stabilization stage, the voltage regulator provides the system with a high voltage based on the clock signal that is pulled down, so that the output stage circuit generates a high voltage. the ramp signal. The ramp voltage generator of claim 1, wherein the first voltage regulator includes: a first transistor, a first terminal of which is coupled to the system low voltage, and a second terminal of which is coupled to the first transistor. A node, its control terminal receives the first control signal; a second transistor, its first terminal is coupled to the system low voltage, its second terminal is coupled to the output stage circuit, and its control terminal receives the light-emitting control signal ; A third transistor, its first terminal is coupled to the first node, its second terminal is coupled to the output stage circuit, and its control terminal receives the second control signal; and A capacitor has a first terminal coupled to the system low voltage and a second terminal coupled to the first node. The ramp voltage generator of claim 1, wherein the second voltage regulator includes: a first transistor, a first terminal of which is coupled to the system high voltage, and a second terminal of which is coupled to the second node. , its control terminal receives the first control signal; a second transistor, its first terminal is coupled to the second node, and its control terminal receives the second control signal; a third transistor, its first terminal is coupled Connected to the first node, its second end is coupled to the second end of the second transistor, and its control end receives the light-emitting control signal; a fourth transistor, its first end is coupled to the second transistor a second terminal of the crystal, its control terminal coupled to the second node; a fifth transistor, its first terminal coupled to the reference voltage, and its second terminal coupled to the second terminal of the fourth transistor , its control terminal receives the second control signal; a sixth transistor, its first terminal is coupled to the system low voltage, its second terminal is coupled to the second terminal of the fifth transistor, and its control terminal receives the lighting control signal; and a capacitor having a first end coupled to the system low voltage and a second end coupled to the second node. The ramp voltage generator of claim 1, wherein the output stage circuit includes: A transistor with a first terminal coupled to the output node, a second terminal coupled to the first voltage regulator, and a control terminal coupled to the first node, wherein the transistor forms the source follower device configuration. The ramp voltage generator of claim 1, wherein the voltage regulator includes: a first transistor, the first end of which is coupled to the system high voltage, and the control end of which receives the lighting control signal; a second transistor; a transistor having a first terminal coupled to the system high voltage, a second terminal coupled to the output node, and a control terminal coupled to the second terminal of the first transistor; and a capacitor having a first terminal After receiving the clock signal, the second terminal is coupled to the second terminal of the first transistor.

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