TWI782585B - Display device - Google Patents

Abstract

A display device includes a driving transistor, a control circuit, a shift register circuit. The control circuit is coupled to the driving transistor, and is configured to control the driving transistor. The shift register circuit is coupled to the control circuit, and is configured to output a sweep signal to the control circuit according to a plurality of signals. The shift register circuit adjusts a voltage level of a node of the control circuit by the sweep signal. The control circuit is configured to control the driving transistor according to the voltage level of the node of the control circuit.

Description

display device

This case involves an electronic device. Specifically, this case relates to a display device.

In the existing display device, the driving control circuit of the display device adopts a direct switch mode. This design causes the thrust of the signal to gradually decrease, which in turn causes the phase shift of the light-emitting circuit inside the panel. Therefore, the slight phase shift of the signal causes obvious display artifacts (mura) in the display device.

Therefore, the above-mentioned technology still has many defects, and it is waiting for practitioners in the field to develop other suitable circuit designs.

One aspect of the present application relates to a display device including a driving transistor, a control circuit, and a shift register circuit. The control circuit is coupled to the driving transistor and used for controlling the driving transistor. The shift register circuit is coupled to the control circuit, and is used for outputting a frequency sweep signal to the control circuit according to a plurality of signals. The shift register circuit adjusts the voltage levels of the nodes of the control circuit through the frequency sweep signal. The control circuit controls the driving transistor according to the voltage level of the node.

The following will clearly illustrate the spirit of this case with diagrams and detailed descriptions. Anyone with ordinary knowledge in the technical field can change and modify the technology taught in this case after understanding the embodiment of this case. It does not depart from the spirit of this case. Spirit and scope.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present case. Singular forms such as "a", "the", "the", "this" and "the", as used herein, also include plural forms.

"Includes", "including", "has", "containing" and so on used in this article are all open terms, meaning including but not limited to.

Regarding the terms (terms) used in this article, unless otherwise specified, generally have the ordinary meaning of each term used in this field, in the content of this case and in the special content. Certain terms used to describe the subject matter are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the subject matter.

FIG. 1 is a schematic circuit block diagram of a display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 1 , the display device 100 includes a driving transistor DT1 , a control circuit 110 , a shift register circuit 120 , a first transistor T1 , a second transistor T2 and a light emitting element L. Referring to FIG. In some embodiments, the display device 100 adopts Gate Driver on Array (GOA) technology. In some embodiments, the display device 100 uses a progressive scan method to drive the pixel circuits inside the panel of the display device 100 .

In some embodiments, please count as the first end from the upper end and the right end of the device in the drawing, and the driving transistor DT1 includes the first end, the second end and the control end. The first end of the driving transistor DT1 is coupled to the first transistor T1. The second end of the driving transistor DT1 is coupled to the second transistor T2. The control terminal of the driving transistor DT1 is coupled to the control circuit 110 .

In some embodiments, the first transistor T1 includes a first terminal, a second terminal and a control terminal. The first terminal of the first transistor T1 receives the power supply voltage VDD. The second end of the first transistor T1 is coupled to the first end of the driving transistor DT1. The control terminal of the first transistor T1 receives the driving signal EM1[n].

In some embodiments, the second transistor T2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T2 is coupled to the second terminal of the driving transistor DT1. The second end of the second transistor T2 is coupled to the light emitting element L. In some embodiments, the light emitting element L includes a first end and a second end. The first end of the light emitting element L is coupled to the second end of the second transistor T2. The second end of the light emitting element L receives the power supply voltage VSS. It should be noted that the light-emitting path of the display device 100 in this case is the shortest path between the power supply voltage VDD and the power supply voltage VSS. The light emitting path of the display device 100 in this case is through the first transistor T1 , the driving transistor DT1 and the second transistor T2 . The light emitting element L is controlled by the first transistor T1 , the driving transistor DT1 and the second transistor T2 .

In some embodiments, the control circuit 110 is coupled to the driving transistor DT1 and used for controlling the driving transistor DT1. The shift register circuit 120 is coupled to the control circuit 110 and used to output the sweep signal SWEEP[ n] to the control circuit 110. The shift register circuit 120 adjusts the voltage level of the node N2 of the control circuit 110 through the sweep signal SWEEP[n]. In some embodiments, the shift register circuit 120 uses the sweep signal SWEEP[n] to raise or lower the voltage level of the node N2 of the control circuit 110 .

In some embodiments, the control circuit 110 includes a transistor T3 , a transistor T4 , a transistor T5 , a transistor T6 , a pulse width modulation transistor PT1 , a capacitor C1 , a node N1 and a node N2 . In some embodiments, the transistor T3 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T3 receives the off signal PPO. The control terminal of the transistor T3 receives the first driving signal EM[n]. The pulse width modulation transistor PT1 includes a first terminal, a second terminal and a control terminal. The first terminal of the pulse width modulation transistor PT1 is coupled to the node N2. The second end of the pulse width modulation transistor PT1 is coupled to the second end of the transistor T3. The control terminal of the pulse width modulation transistor PT1 is coupled to the node N1.

In some embodiments, the transistor T4 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T4 is coupled to the node N2. The second end of the transistor T4 is coupled to the node N1. The control terminal of the transistor T4 receives the gate signal Gate[n]. The transistor T5 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T5 receives the DC signal RES_DC. The second end of the transistor T5 is coupled to the node N1. The control terminal of the transistor T5 receives the reset signal R[n]. The transistor T6 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T6 is coupled to the second end of the pulse width modulation transistor PT1 and the second end of the transistor T3. The second end of the transistor T6 receives the input signal Input. The control terminal of the transistor T6 receives the gate signal Gate[n]. The capacitor C1 includes a first terminal and a second terminal. A first end of the capacitor C1 is coupled to the node N1. The second terminal of the capacitor C1 is coupled to the input terminal of the control circuit 110 (ie, the scanning resistor-capacitor terminal 111 ), and receives the sweep signal SWEEP[n].

In some embodiments, the shift register circuit 120 includes a selection transistor ST1 , a capacitor C2 , an output circuit 121 and a sweep voltage driving circuit 122 . In some embodiments, the output circuit 121 is coupled to the selection transistor ST1 and the capacitor C2. In some embodiments, the sweep voltage driving circuit 122 is coupled to the output circuit 121 .

In some embodiments, the selection transistor ST1 outputs the sweep signal SWEEP[n] to the I/O terminal of the control circuit 110 (ie, the scanning resistor and capacitor terminal 111 ) according to the driving signal. The capacitor C2 is used to stabilize the voltage of the sweep signal SWEEP[n].

In some embodiments, the capacitor C2 includes a first terminal and a second terminal. The first end of the capacitor C2 is coupled to the output circuit 121 . The second terminal of the capacitor C2 is the input terminal of the control circuit 110 (ie, the scanning resistor-capacitor terminal 111 ). The selection transistor ST1 includes a first terminal, a second terminal and a control terminal. The first terminal of the selection transistor ST1 is coupled to the input terminal of the control circuit 110 (ie, the scanning resistor-capacitor terminal 111 ). The second terminal of the selection transistor ST1 outputs the sweep signal SWEEP[n] according to the driving signal EM[n] and the slope signal SW_slope[P] received by the output circuit 121 .

In some embodiments, the driving transistor DT1, the first transistor T1, the second transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the pulse width modulation transistor PT1 and the selection transistor ST1 is a P-type metal oxide semiconductor field effect transistor PMOS (p type Metal Oxide Semiconductor, PMOS). Although the embodiment of this case adopts PMOS, it is not limited to the embodiment in the drawing. In detail, if the transistors T7 to T15 are N type metal oxide semiconductor field effect transistors (N type Metal Oxide Semiconductor, NMOS). The electrical operation of the display device 100 in this case is reversed.

In some embodiments, the display device 100 further includes a driving shift register circuit 910 , a first scan shift register circuit 930 and a second scan shift register circuit 950 . In some embodiments, the drive shift register circuit 910, the first scan shift register circuit 930, and the second scan shift register circuit 950 are all controlled by the system side of the display device 100 (not shown in the figure). controlled by.

In some embodiments, the driving shift register circuit 910 is used to receive the driving clock signal EM_CLK, the first serial input signal S1 and the gate driving signal GOA, so as to output the driving signal EM1[n] to the first transistor T1 and the output circuit 121 of the shift register circuit 120 may output the driving signal EM2[n] to the second transistor T2.

In some embodiments, the first scan shift register circuit 930 is used to receive the first scan clock signal SC_CLK1 and the second serial input signal S2[N], so as to output the gate signal Gate[n] or multi-stage Gate signal. In some embodiments, the first scan shift register circuit 930 outputs the gate signal Gate[n] or multi-level gate signals to the control circuit 110 or the shift register circuit 120 .

In some embodiments, the second scan shift register circuit 950 is used to receive the second scan clock signal SC_CLK2 and the secondary second serial input signal S2[N+1], so as to output the gate signal Gate[n ] or multi-level gate signal. In some embodiments, the second scan shift register circuit 950 outputs the gate signal Gate[n] or multi-level gate signals to the control circuit 110 or the shift register circuit 120 .

In some embodiments, in order to make the operation of the display device 100 in FIG. 1 easy to understand, please also refer to FIG. 2 . FIG. 2 is a schematic diagram of a timing sequence of driving signals of a display device according to some embodiments of the present invention. In some embodiments, the shift register circuit 120 is used to output the sweep signal SWEEP[n] to the control circuit 110 according to a plurality of signals. The shift register circuit 120 adjusts the voltage level of the node N2 of the control circuit 110 by the sweep signal SWEEP[n]. The control circuit 110 controls the driving transistor DT1 according to the voltage level of the node N2. It should be noted that, the phase I11 to the phase I17 are one driving cycle of the display device 100 .

In some embodiments, the first transistor T1 , the driving transistor DT1 and the second transistor T2 control the light emitting element L. Referring to FIG. The control terminal of the first transistor T1 is turned on in response to the driving signal EM1[n]. The control terminal of the second transistor T2 is turned on in response to the driving signal EM2[n]. The driving transistor DT1 is turned on in response to the voltage level of the node N2 of the control circuit 110 , so as to control the light-emitting element L together with the first transistor T1 and the second transistor T2 .

In some embodiments, the duty cycle P1 of the driving signal EM1[n] is greater than the duty cycle P2 of the driving signal EM2[n]. It should be noted that R[n] is a reset signal, and the control circuit 110 is used for resetting according to the reset signal R[n]. The signal PAM[n] is the change of the voltage level of the node N2 of the control circuit 110 . The signal PAM[n] changes in response to the sweep signal SWEEP[n] and is closely related to the internal operation of the shift register circuit 120 . In order to better understand the internal operation of the shift register circuit 120, its detailed steps will be explained in the following paragraphs.

In essence, the duty cycle P1 of the driving signal EM1 [n] is a control phase of the display device 100 . The duty cycle P2 of the driving signal EM2[n] is the light-emitting phase of the light-emitting element L. The duration of the duty cycle P2 is adjusted to achieve a driving method similar to pulse width modulation.

In some embodiments, in order to understand the internal operation of the shift register circuit 120, please refer to FIG. 3 and FIG. 4 together. FIG. 3 is a schematic circuit block diagram of a shift register circuit 120 of a display device according to some embodiments of the present invention. In some embodiments, FIG. 3 is an expanded view of the internal structure of the shift register circuit 120 of the display device 100 in FIG. 1 . FIG. 4 is a schematic diagram of the timing sequence of the driving signals of the shift register circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 3 and FIG. 4 , the output circuit 121 is used to control the selection transistor ST1 according to the driving signal EM[n]. The sweep voltage driving circuit 122 is used to control the selection transistor ST1 through the output circuit 121 according to the selection signal PHG[n]. The selection transistor ST1 controlled by the output circuit 121 and the sweep voltage driving circuit 12 imitates the slope signal SW_slope[P] according to the driving signal EM[n] to output the sweep signal SWEEP[n].

It should be noted that the voltage levels VGH and VGL are both DC levels. Both the sweep high level SW_H and the sweep low level SW_L are DC levels. The phase I21 to the phase I24 are one driving cycle of the shift register circuit 120 of the display device 100 .

In some embodiments, the shift register circuit 120 includes an output circuit 121 and a sweep voltage driving circuit 122 . In some embodiments, the output circuit 121 includes a transistor T9, a transistor T11 and a transistor T12. In some embodiments, the frequency sweep voltage driving circuit 122 includes a transistor T7 , a transistor T8 , a transistor T10 , a transistor T13 , a transistor T14 , a transistor T15 , a capacitor C3 and a capacitor C4 .

In some embodiments, the transistors T7 to T15 are all PMOS (p type Metal Oxide Semiconductor, PMOS) transistors. Although the embodiment of this case adopts PMOS, it is not limited to the embodiment in the drawing. In detail, if the transistors T7 to T15 are N type metal oxide semiconductor field effect transistors NMOS (N type Metal Oxide Semiconductor, NMOS). The electrical operation of the display device 100 in this case is reversed.

FIG. 5 is a schematic diagram of the state of the shift register circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 4 and FIG. 5 , in the stage I21 , the sweep voltage driving circuit 122 of the shift register circuit 120 receives the sweep clock signal SW_CLK. The sweep clock signal SW_CLK is used to stabilize the internal voltage of the sweep voltage driving circuit 122 . At this time, the driving voltage EM[n] is at the high level, and the transistor T7, the transistor T8, and the transistor T9 are turned on, so as to guide the current input from the output terminal Output of the shift register circuit 120 to the frequency sweep low level. bit SW_L. It should be noted that, in the stage I21, the slope signal SW_slope[P] will be input to the first terminal of the selection transistor ST1 in advance.

FIG. 6 is a schematic diagram of the state of the control circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 2 and FIG. 6 , in the phase I12 , the gate signal Gate[n] is at a low level, and the transistor T6 and the transistor T4 are turned on in response to the gate signal Gate[n]. At this time, the input signal Input is input through the second end of the transistor T6, and the voltage level is input to the above-mentioned shift register through the pulse width modulation transistor PT1, node N2, transistor T4, node N1 and capacitor C1 The output terminal Output of the circuit 120 is used for compensation. It should be noted that the stage I12 in FIG. 2 roughly corresponds to the stage I21 in FIG. 4 .

In some embodiments, please refer to FIG. 2 , in the phase I11 , the reset potential R[n] is at a low level, and the transistor T5 is turned on to reset the potential of the node N1 or the node N2 to the DC signal RES_DC.

FIG. 7 is a schematic diagram of the state of the shift register circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 4 and FIG. 7. In phase I22, the selection signal PHG[n] is at a low level, the control terminal of the transistor T15 is turned on in response to the selection signal PHG[n], and the transistor T10 The control terminal of the transistor T14 and the control terminal of the transistor T14 are turned on in response to the voltage level VGL. At this time, the transistor T7, the transistor T8 and the transistor T9 are turned off. The frequency-sweeping high-level bit SW_H starts to output the high-level bit to the output terminal Output of the shift register circuit 120 through the transistor T10 , and then outputs the high-level bit to the above-mentioned control circuit 110 .

FIG. 8 is a schematic diagram of the state of the control circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 2 and FIG. 8 , in the stage I13 , the frequency sweep signal SWEEP[n] is at a high level. The sweep signal SWEEP[n] output from the output terminal Output of the shift register circuit 120 raises the voltage level of the node N1, thereby generating a high thrust to indirectly raise the voltage level of the node N2.

FIG. 9 is a schematic diagram of the state of the shift register circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 4 and FIG. 9. In stage I22, the selection signal PHG[n] changes from a low level to a high level, and the control terminal of the transistor T15 responds to the selection signal PHG[n] closure. At this time, the control terminal of the transistor T10 and the control terminal of the transistor T14 maintain a low level, and the frequency-sweeping high level SW_H continuously outputs a high level to the output terminal Output of the shift register circuit 120 through the transistor T10, and then The high level is output to the above-mentioned control circuit 110 . It should be noted that the stage I13 in FIG. 2 roughly corresponds to the stage I22 in FIG. 4 .

FIG. 10 is a schematic diagram of the state of the shift register circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 4 and FIG. 10. In phase I23, the driving signal EM[n] is at a low level, and the transistor T11, the transistor T12, the transistor T13 and the selection transistor ST1 respond to the driving The signal EM[n] is turned on, and the control terminals of the transistor T10 and the transistor T14 are turned off in response to the voltage level VGH. The slope signal SW_slope[P] is output to the output terminal Output of the shift register circuit 120 through the selection transistor ST1 . The selection transistor ST1 starts to imitate the falling edge of the slope signal SW_slope[P], so as to output the gradually falling slope signal to the control circuit 110 .

FIG. 11 is a schematic diagram of the state of the control circuit 120 of the display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 2 and FIG. 11. In phase I14, phase I15, and phase I16, since the frequency sweep signal SWEEP[n] gradually decreases, the voltage of node N2 changes (that is, the signal PAM[n] ) gradually decreases in response to the node N1, the driving signal EM[n] is at a low level, and the cut-off signal PPO is written into the node N2 through the transistor T3 and the pulse width modulation transistor PT1. The control end of the drive transistor DT1 is cut off in response to the node N2, and outputs current to the light-emitting element L together with the first transistor T1 and the transistor T2, so as to realize the driving method of pulse amplitude modulation. It should be noted that the stage I14, stage I15 and stage I16 in FIG. 2 roughly correspond to the stage I23 in FIG. 4 .

FIG. 12 is a schematic diagram of a state of a shift register circuit 120 of a display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 4 and FIG. 12. In phase I24, the driving voltage EM[n] is at a high level, and transistor T7, transistor T8, and transistor T9 are turned on, so as to shift the slave The current input by the output terminal Output of the register circuit 120 is directed to the sweep low level SW_L. It should be noted that the stage I17 in FIG. 2 roughly corresponds to the stage I24 in FIG. 4 .

FIG. 13 is a schematic circuit block diagram of a display device 100A according to some embodiments of the present invention. In some embodiments, compared with the display device 100 in FIG. 1, the embodiment in FIG. 13 adds two transistors (for example: transistor T16 and transistor T17) in the control circuit 110A, and adds a setting shift Bit register circuit 970A and driving transistor DT2. The setting shift register circuit 970A is coupled to the control terminal of the transistor T17. It should be noted that by adding the circuit structure in FIG. 13 to simultaneously control the driving transistor DT1 and the driving transistor DT2, the display defect (mura) of the display device can be reduced.

According to the foregoing embodiments, the present application provides a display device, which uses the circuit structure of the present application to generate a continuous thrust of a sweeping signal to reduce display muras caused by phase shift of the display device.

Although this case discloses the above with detailed embodiments, this case does not exclude other feasible implementation forms. Therefore, the scope of protection of this case should be defined by the scope of the appended patent application, rather than being limited by the foregoing embodiments.

For those skilled in the art, without departing from the spirit and scope of this document, various changes and modifications can be made to this document. Based on the foregoing embodiments, all changes and modifications made to this case are also covered within the scope of protection of this case.

100, 100A: display device 110, 110A: control circuit 111, 111A: scanning resistance and capacitance terminals 120, 120A: shift register circuit 121, 121A: output circuit 122, 122A: frequency sweep voltage drive circuit 910, 910A: drive shift register circuit 930, 930A: the first scan shift register circuit 950, 950A: the second scan shift register circuit 970A: Set shift register circuit T1~T17: Transistor DT1, DT2: drive transistor ST1: select transistor PT1: pulse width modulation transistor C1~C4: capacitance N1~N2: Node L: light emitting element R[n]: reset signal EM[n], EM1[n], EM[n]: drive signal VDD, VSS: power supply voltage Gate[n], Gate[n+1]: gate signal EM_CLK: drive clock signal S1: The first serial input signal GOA: gate drive signal SC_CLK1: first scan clock signal S2[N]: The second serial input signal SC_CLK2: Second scan clock signal S2[N+1]: secondary second serial input signal SW_CLK: frequency sweep clock signal SW_H: Frequency sweep high level SW_L: Sweep low level SW_slope[P]: slope signal RES_DC: DC signal SWEEP[n]: frequency sweep signal PAM[n]: signal P1~P3: work cycle I11~I17: stage I21~I24: stage VGL, VGH: voltage level PHG[n]: select signal Input: input signal Output: output terminal PWD_DC: DC signal SET[n]: set signal SET_CLK: clock signal

The content of this case can be better understood with reference to the implementation manner in the following paragraphs and the following drawings: Figure 1 is a schematic circuit block diagram of a display device according to some embodiments of the present invention; FIG. 2 is a schematic diagram of a timing sequence of driving signals of a display device according to some embodiments of the present invention; FIG. 3 is a schematic circuit block diagram of a shift register circuit of a display device according to some embodiments of the present invention; FIG. 4 is a schematic diagram of a timing sequence of driving signals of a shift register circuit of a display device according to some embodiments of the present invention; FIG. 5 is a schematic diagram of the state of the shift register circuit of the display device according to some embodiments of the present invention; FIG. 6 is a schematic diagram of the state of the control circuit of the display device according to some embodiments of the present invention; FIG. 7 is a schematic diagram of a state of a shift register circuit of a display device according to some embodiments of the present invention; FIG. 8 is a schematic diagram of the state of the control circuit of the display device according to some embodiments of the present invention; FIG. 9 is a schematic diagram of the state of the shift register circuit of the display device according to some embodiments of the present invention; FIG. 10 is a schematic diagram of the state of the shift register circuit of the display device according to some embodiments of the present invention; FIG. 11 is a schematic diagram of the state of the control circuit of the display device according to some embodiments of the present invention; FIG. 12 is a schematic diagram of a state of a shift register circuit of a display device according to some embodiments of the present invention; and FIG. 13 is a schematic circuit block diagram of a display device according to some embodiments of the present invention.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

120: Shift register circuit

121: output circuit

122: frequency sweep voltage drive circuit

910: Driving shift register circuit

930: first scanning shift register circuit

950: The second scan shift register circuit

T7~T15: Transistor

C2~C4: capacitance

ST1: select transistor

EM_CLK: drive clock signal

S1: The first serial input signal

GOA: gate drive signal

SC_CLK1: first scan clock signal

S2[N]: The second serial input signal

SC_CLK2: Second scan clock signal

S2[N+1]: secondary second serial input signal

SW_CLK: frequency sweep clock signal

SW_H: Frequency sweep high level

SW_L: Sweep low level

SW_slope[P]: slope signal

VGL, VGH: voltage level

PHG[n]: select signal

Output: output terminal

EM[n]: drive signal

SWEEP[n]: frequency sweep signal

Claims (10)

A display device, comprising: a driving transistor; a control circuit, coupled to the driving transistor, and used to control the driving transistor; and a shift register circuit, coupled to the control circuit, and used to A plurality of signals output a frequency sweep signal to the control circuit, wherein the frequency sweep signal is a high level in a first stage, and the frequency sweep signal gradually decreases from the high level in a second stage; wherein the shift The temporary register circuit adjusts a voltage level of a node of the control circuit according to the frequency sweep signal, wherein the control circuit controls the driving transistor according to the voltage level of the node. The display device according to claim 1, wherein the shift register circuit uses the frequency sweep signal to raise or lower the voltage level of the node of the control circuit. The display device according to claim 2, wherein the shift register circuit includes a selection transistor, wherein the selection transistor outputs the frequency sweep signal to the control circuit according to a first driving signal of the signals. The display device according to claim 3, wherein the shift register circuit includes a capacitor, wherein the capacitor is used to stabilize the voltage of the frequency sweep signal. The display device as described in claim 4, wherein the shift register circuit includes an output circuit coupled to the selection transistor and the capacitor, and used to control the selection transistor according to the first driving signal of these signals The crystal is used to drive the driving transistor to output a current to a light emitting element. The display device as described in claim 5, wherein the shift register circuit includes a frequency-sweeping voltage driving circuit, wherein the frequency-sweeping voltage driving circuit is coupled to the output circuit, and is used to select a signal according to one of the signals to The selection transistor is controlled by the output circuit to output the frequency sweep signal. The display device as described in claim 1, wherein the control circuit includes a pulse width modulating transistor, wherein the pulse width transistor includes a first terminal, a second terminal and a control terminal, wherein the pulse width transistor The first terminal is coupled to the driving transistor, and the control terminal of the pulse width transistor responds to the voltage level of the node to control the driving transistor. The display device as described in Claim 1, wherein the display device comprises a first transistor, wherein the first transistor is coupled to the driving transistor, and the first transistor is connected to the control transistor according to a second driving signal The circuit collectively controls the driving transistor. The display device as described in Claim 8, wherein the display device comprises a second transistor, wherein the second transistor is coupled to the drive transistor, and the second transistor is connected to the control transistor according to a third drive signal The circuit and the first transistor jointly control the driving transistor. The display device according to claim 9, wherein a first duty cycle of the second driving signal is greater than a second duty cycle of the third driving signal.

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