JPH0682754A - Active matrix type display device - Google Patents

Abstract

PURPOSE:To miniaturize an active matrix type display device and sharply improve yield in a driving circuit integrated type device by simultaneously selecting a plurality of video signal lines so that even a shift resistor with slow operating speed is operable at high speed as a display device, and suppressing the enlargement of an external circuit. CONSTITUTION:An active matrix type display device is provided with a video signal supplying circuit 6 for sampling and distributing video signals, outputting the divided video signals to a plurality of video input lines 11 with their timings being conformed to each other; and a video signal line driving circuit 4 having a plurality of resistors A1,... every stage of shift resistors 41,..., optionally selecting one resistor every stage, and simultaneously outputting the shift output from this resistor A1,... every stage and the signal from the video signal supplying circuit 6 to one set of video signal lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device which performs display based on a video signal.

[0002]

2. Description of the Related Art A liquid crystal display device, an electroluminescence display device, and the like have been attracting attention as a compact and lightweight flat display device which replaces a CRT display device. Among them, liquid crystal display devices are being put to practical use for various applications as next-generation display devices.

The active matrix type liquid crystal display device is
A plurality of video signal lines and scanning signal lines are arranged in a matrix, and an auxiliary capacitance line that forms an auxiliary capacitance (Cs) between the pixel electrodes via the thin film transistors as switch elements at each intersection. Is provided, and liquid crystal is sandwiched between the pixel electrode and a counter electrode facing the pixel electrode. Further, the active matrix liquid crystal display device is configured by further including a video signal line drive circuit connected to the video signal line and a scanning signal line drive circuit connected to the scanning signal line.

When the scanning signal (Vg, on) is applied from the scanning signal line to the gate electrode of the thin film transistor, the thin film transistor is turned on and the voltage of the video signal (Vs) on the video signal line is written to the pixel electrode and the auxiliary capacitance, respectively. . Then, while the scanning signal (Vg, off) is applied to the scanning signal line, the thin film transistor is turned off, and the voltage (Vs) applied to the pixel electrode and the auxiliary capacitor is held, and the voltage (Vs) is applied. The liquid crystal responds and a display is made.

In recent years, higher definition has been required for active matrix type display devices typified by such active matrix type liquid crystal display devices, and accordingly, scanning signal lines and video signal lines have been conventionally formed. It also tends to increase.

Therefore, in order to eliminate the inconvenience of connection between each signal line and the drive circuit and improve the productivity, the drive circuit and the matrix wiring portion are integrally formed on the same substrate in a drive circuit integrated type. Display devices have been put to practical use.

In an active matrix type display device integrated with a driving circuit, a high-performance polycrystalline silicon thin film transistor is usually used in the driving circuit, and it is attempted to cope with high-speed driving of the driving circuit. However, even if a high-performance polycrystalline silicon thin film transistor is used, it has been difficult to cope with an increase in operating speed due to an increase in scanning signal lines or video signal lines.

Therefore, as a method of forming a driving circuit capable of high-speed operation by using the thin film transistor whose operating speed is insufficient, there is a method of dividing a shift register into a plurality of parts and connecting each of them in parallel to drive them. .

Further, as disclosed in Japanese Patent Laid-Open No. 59-83198 or Japanese Patent Laid-Open No. 2-153391, the video signal is divided into multiple phases and sequentially supplied to the video signal line. There is a method of setting a sample and hold time of a video signal to be long according to the number of divisions and thereby realizing a high-density display image.

FIG. 9 is a schematic configuration diagram of a video signal line drive circuit 81 of an active matrix type liquid crystal display device which can be considered from a combination of such conventional techniques. The video signal line drive circuit 81 has four divided video signals (Vs1) to (Vs1).
s4) is input and each video input line 82, 83, 84, 85
Applied to. The video signal line drive circuit 81 includes four shift registers 86, 87, 88, 89, each of which has a start pulse (ST1) to a start pulse (ST1) shown in FIG.
(ST4), the clocks (CK1) to (CK4) are input, and the shift register outputs (SR1, i) to (SR4, i) are sequentially output in synchronization with the clocks (CK1) to (CK4).

Each output of the first shift register 86 (SR
1, i) is a video signal (Vs1) supplied to the first video input line 82 for each video signal line (Y1), (Y5), ...
It is connected to the gate electrode of each thin film transistor 90 for controlling the timing of output to (Y (4i-3)). Each output of the second shift register 87 (SR
2, i) is a video signal (Vs2) supplied to the second video input line 83 for each video signal line (Y2), (Y6), ...
It is connected to the gate electrode of each thin film transistor 91 for controlling the timing of output to (Y (4i-2)). Each output of the third shift register 88 (SR3,
In (i), the video signal (Vs3) supplied to the third video input line 84 is supplied to each video signal line (Y3), (Y7), ..., (Y
(4i-1)) is connected to the gate electrode of each thin film transistor 92 for controlling the output timing. Then, each output of the fourth shift register 89 (SR
4) displays the video signal (Vs4) supplied to the fourth video input line 85 on each video signal line (Y4), (Y8), ..., (Y
It is connected to the gate electrode of each thin film transistor 93 for controlling the timing of outputting to (4i)).

By adopting such a structure, the clock (CK) speed of each shift register can be reduced to 1/4 as compared with the case where the video signal line drive circuit 81 is composed of one shift register. .

Further, as can be seen from this figure, by dividing the shift registers 86 to 89, the time (T) of the output of each shift register 86 to 89 is about four times as long as that in the case where one shift register is used. It can be set long. Thereby, the thin film transistors 90 to 93
The operating speed required for is good even if it is slow.

[0014]

By configuring the video signal line drive circuit as described above, even if a shift register operating at a low speed is used, the drive circuit as a whole can operate at a high speed. Moreover, since the output time (T) of each shift register 86 to 89 can be lengthened, each video signal (Vs1)
The application time of (Vs4) can be set to be long, whereby a good display image can be obtained.

However, when the active matrix type display device is constructed in this way, there are the following problems. That is, if the shift registers 86 to 89 are divided and configured as described above, the shift registers 86 to 89 are separated.
In addition to the increase in circuit area due to the division, the start pulses (ST1) to (ST4) and the clock (CK1) to drive the shift registers 86 to 89, respectively.
This leads to an increase in external circuits for receiving (CK4) from the outside, which makes it difficult to downsize the active matrix display device.

Further, in the above-mentioned configuration, the number of wirings connected to the external circuit increases in proportion to the increase in the number of shift registers, so that there is a possibility that productivity may be reduced due to an increase in mounting work time.

The present invention has been made in response to such a problem, and even if the video signal drive circuit is constituted by a circuit having a slow operation speed, the display device can operate at high speed and the yield is high. It is an object of the present invention to provide an active matrix type display device capable of improving the above.

[0018]

In the active matrix type display device of the present invention, there are K sets, K sets of K sets, K sets of N video signal lines and m sets of scanning signal lines are arranged in a matrix. And the matrix wiring part formed by sampling the video signal at a timing corresponding to one display pixel
A video signal supply circuit having a distribution means for distributing the video signals of the book and a timing control means for matching the timings of the distributed video signals and outputting the video signals to the K video input lines. And a video signal line driving circuit for simultaneously outputting a video signal output via the video input line to a corresponding set of video signal lines. Further, at least the matrix wiring section and the video signal line are provided. The driving circuit and the driving circuit are integrally formed on the same substrate.

The active matrix type display device is characterized in that the video signal line drive circuit includes an n-stage shift register. Further, the timing control means is characterized by including two or more voltage holding means.

Further, the active matrix type display device is characterized in that the distributing means comprises K sampling means and K shift registers for determining the sampling period of the sampling means.

Further, the drive circuit integrated type device is characterized in that a shift register having a plurality of registers is formed for each stage, and one register is arbitrarily selected for each stage.

[0022]

As described above, in the active matrix type display device of the present invention, the video signal supply circuit samples the video signal at a timing corresponding to one display pixel and distributes the video signal to K video signals. Since it is provided with timing control means for matching the timings of the distributed video signals and outputting to the K video input lines,
The timings of the divided video signals are matched and output to the K video input lines.

As a result, according to the present invention, it is possible to simultaneously select the distributed video signals corresponding to a plurality of video signal lines, each of which is K in number. Therefore, according to the present invention, the circuit configuration itself of the video signal line drive circuit can be simplified, and the operation speed is equivalent to the number of divisions of the video signal.
That is, it is possible to slow the speed to about 1 / K times.

Further, with the simplification of the video signal line drive circuit, the circuit configuration of the external circuit for controlling the video signal line line drive circuit can be simplified, so that the size of the device can be greatly reduced. be able to.

Further, in the drive circuit integrated type device, the shift register of the video signal line drive circuit can be provided with redundancy without complicating the structure, and the yield can be dramatically improved.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of an active matrix type liquid crystal display device of the present invention. The active matrix type liquid crystal display device 1 performs display based on an analog input video signal (Vs), and a liquid crystal display unit 3 and a video signal line drive which are integrally formed on an insulating substrate 2. It is composed of a circuit 4, a scanning signal line drive circuit 5, a video signal supply circuit 6, a switching circuit 7, and a control circuit (not shown).

The liquid crystal display section 3 includes a set of four 720
, (Y1 to Y720) and 480 scanning signal lines 12, ... Are arranged in a matrix, and pixel electrodes 14 are provided at each intersection as switching elements via thin film transistors 13. , A matrix wiring portion including an auxiliary capacitance line 15 connected to a common bias voltage forming an auxiliary capacitance Cs with the pixel electrode 14. A liquid crystal 17 is sandwiched between the pixel electrode 14 and the counter electrode 16 in the matrix wiring portion.

The video signal line drive circuit 4 receives each of the video signal lines 11, ... Based on the analog video signals (Vsa1 ') to (Vsa4') supplied from the video signal supply circuit 6 through the external wiring.
Is to drive. A start pulse ST1 is supplied to the video signal line drive circuit 4 by an input line 4a, and a clock CK1 as shown in FIG.
5 is supplied, the switching signal from the switching circuit 7 is supplied via the input lines 4c to 4f, and the video input lines 4g to 4j are supplied with the switching signals shown in FIG.
Four video signals are supplied from the video signal supply circuit 6 as shown in (f) to (i).

The scanning signal line drive circuit 5 includes the scanning signal line 1
, 2 are driven, the start pulse ST2 is supplied by the input line 4k, and the clock CK3 is supplied by the input line 4l.

The video signal supply circuit 6 samples the supplied analog video signal Vs at a timing corresponding to one display pixel and distributes it to four (K) video signals, and the timing of this distributed video signal. Match 4 pieces (K
Main) video input line, and is supplied with a vertical synchronizing signal VS, a horizontal synchronizing signal HS, a clock CK2, and an analog video signal Vs.

The switching circuit 7 is composed of, for example, a 4-bit DIP switch, and by switching a switching switch (described later) in the video signal line drive circuit 4, a plurality of n-stage shift registers 41 to 44 are provided. The output from one of the shift registers is valid. The output of the switching circuit 7 is external wiring 29e to 29h.
Is supplied to each of the input lines 4c to 4f of the video signal line drive circuit 4 via.

As shown in FIG. 2, the video signal supply circuit 6 includes a shift register 21, an AND circuit 22, an analog / digital converter 23, a first data latch section 24,
The second data latch unit 25, the digital / analog conversion unit 27, and the amplification / inversion unit 28 are included.

The shift register 21 has a four-stage structure, is reset by the horizontal synchronizing signal HS, and starts to operate with only the first-stage shift outputs (SR2, 1) turned on to perform horizontal sampling. By the horizontal sampling signal (clock) CK2 corresponding to the cycle, (b) of FIG.
The shift outputs (SR2, 1) to (SR2,
4) is output. The shift outputs (SR2, 1) to (SR2, 4) of the shift register 21 are supplied to the latch circuits 24a and 24d of the first data latch unit 24, respectively.

The shift output (SR2, 1) is supplied to the latch circuit 24a, the shift output (SR2, 2) is supplied to the latch circuit 24b, and the shift output (SR2, 3) is supplied to the latch circuit 24c. Output (SR2,
4) is supplied to the latch circuit 24d.

The shift outputs (SR2, 4) are supplied to the start input of the shift register 21 and
It is supplied to one input terminal of the AND circuit 22. The shift register 21 is configured such that after the fourth-stage shift outputs (SR2, 4) are turned on, the first-stage shift outputs (SR2, 1) are returned to the on state.

The AND circuit 22 outputs the shift outputs (SR2, 4) of the shift register 21 and the horizontal sampling signal CK.
The logical product output ST ((j) in FIG. 3) is supplied to each latch circuit 25a, 25d of the second data latch unit 25.

The analog / digital converter 23 supplies the analog video signal (V) as shown in FIG.
s) is converted into a 10-bit digital video signal (Vsd), and the digital video signal (Vsd) is used for the latch circuits 24a to 24 of the first data latch section 24.
supplied to d.

The first data latch section 24 is composed of four latch circuits 24a to 24d, and each latch circuit 24a to 24d receives the digital video signal (Vsd) from the analog / digital converter 23. It is to be latched, and its latching (holding) timing is controlled by the shift output of the shift register 21 having four stages. That is, by the first data latch unit 24,
The digital video signal (Vsd) from the analog / digital converter 23 is time-distributed in order to four, and the latch outputs (L1, 1) to (f) to (i) of FIG.
(L1, 4) can be obtained.

The latch circuit 24a is provided in the shift register 21.
The digital video signal (Vsd) from the analog / digital converter 23 is latched when the first-stage shift output (SR2, 1) is turned on. Latch circuit 24b
Is the second-stage shift output (SR
2, 1) is on, the analog / digital converter 2
The digital video signal (Vsd) from the circuit 3 is latched. The latch circuit 24c corresponds to 3 of the shift register 21.
The digital video signal (Vsd) from the analog / digital converter 23 is latched when the shift output (SR2, 1) of the stage is on. Latch circuit 24d
Is the shift output of the fourth stage of the shift register 21 (SR
2, 1) is on, the analog / digital converter 2
The digital video signal (Vsd) from the circuit 3 is latched.

The latch outputs of the latch circuits 24a, 24d of the first data latch section 24 are output to the latch circuits 25a, 25d of the second data latch section 25, respectively.

The second data latch section 25 is composed of four latch circuits 25a and 25d, and each latch circuit 25a and 25d receives the logical product output ST from the AND circuit 22. , Latch outputs (L1, 1) from the latch circuits 24a, 24d, respectively.
(L1, 4) is latched, and each latch circuit 2
Latch outputs (L2, 1) to (L2, 4) of 5a to 25d shown in (k) to (n) of FIG. 3 are supplied to digital / analog converters 27a and 27d, respectively.

That is, the latch circuits 24a, ...
When the latch outputs (L1, 1) to (L1, 4) by d have been captured, those latch outputs (L1, 1) to
(L1, 4) are respectively held by the latch circuits 25a, 25d, and the latch outputs (L2, 1) to (L2, 4) of the latch circuits 25a, 25d are supplied to the digital / analog converters 27a, 27d. To be done.

In this way, the digital video signal (V
sd) is divided into four latch outputs (L1, 1) to (L
The second data latch section 25 arranges the phases 1 and 4) so that the phases thereof, that is, the times at which the potential changes are the same.

The digital / analog converter 27 is composed of four digital / analog converters 27a to 27d.
a, .about.27d are latch outputs (L2, 1) to (L2, L2, 1) to (L2, 1) from the latch circuits 25a, 25d.
4) are analog video signals (Vsa1) to (Vsa4) respectively.
), And the outputs of the respective digital / analog converters 27a to 27d are amplified / inverted circuits 28a to 28d.
28d.

The amplification / inversion unit 28 includes four amplification / inversion circuits 2.
8a to 28d, each amplification inverting circuit 2
8a to 28d are analog video signals (Vsa1) from the digital / analog converters 27a and 27d, respectively.
An analog video signal (Vsa) that can drive the liquid crystal 17 by amplifying the voltage value of (Vsa4) and inverting the polarity for each field by the vertical synchronization signal (VS).
1 ') to (Vsa4'), and the outputs of the amplification and inversion circuits 28a to 28d are the video input lines 4g to 4j of the video signal line drive circuit 4 via the external wirings 29a to 29d.
Is supplied to.

The operation of the video signal supply circuit 6 having such a configuration will be described. First, an analog video signal (Vs) as shown in FIG. 3A is supplied to the analog / digital converter 23. Then, the analog / digital converter 23 converts the analog video signal (Vs) into a 10-bit digital video signal (Vsd),
The shift outputs (SR2, 1) to (SR2, 4) of the shift register 21 shown in (b) to (e) of FIG.
Latch circuits 24a, 24d of the data latch unit 24 of
Then, the digital video signal (Vsd) is sequentially held.

For example, as shown in (f) to (i) of FIG. 3, the latch circuit 24a holds the voltage value Va as the latch output (L1, 1), and the latch circuit 24b holds the latch output (L1, 2). ) Is held, the latch circuit 24c holds the voltage value Vc as the latch output (L1, 3), and the latch circuit 24d holds the latch output (L).
The voltage value Vd as 1, 4) is held.

When the latch output to the latch circuits 24a to 24d is completed, the AND output ST from the AND circuit 22 causes the latch circuits 25a to 25d.
Holds latch outputs (L1, 1) to (L1, 4) from the respective latch circuits 24a, 24d, and (k) through FIG.
As shown in (n), the latch outputs (L2, 1) of the respective latch circuits 25a, 25d whose phases are aligned
(L2, 4) are digital / analog converters 2 respectively
7a to 27d. As a result, the digital / analog converters 27a to 27d are latched by the latch circuit 25.
Latch outputs (L
2, 1) to (L2, 4) are converted into analog video signals (Vsa1) to (Vsa4) respectively, and the amplification / inversion circuit 28a is used.
~ 28d.

These amplifying and inverting circuits 28a to 28d are
Digital / analog converters 27a, 27d, respectively
The voltage values of the analog video signals (Vsa1) to (Vsa4) from the same are amplified, and the polarities are inverted for each field by the vertical synchronization signal (VS), thereby the liquid crystal 17
Video signals (Vsa1 ') to (Vsa4') that can drive the
And are supplied to the video input lines 4g to 4j of the video signal line drive circuit 4 via the external wirings 29a to 29d, respectively.

The video signal line drive circuit 4 is composed of a shift register section 31, a changeover switch section 32, and a sample hold section 33. The changeover switch unit 32 is
Thin film transistor SW as 720 changeover switches
1 to SWN.

The sample-hold section 33 is composed of 720 sample-hold circuits V1 to VN. Each sample-hold circuit V1, ... Includes a thin film transistor S1 ,.
1, ... CDN.

The shift register section 31 is composed of four (four systems) shift registers 41 to 44 of 180 stages, and the registers A1, A2, ..., B1 of each stage of the shift registers 41 to 44 ,. B2, ..., C1, C2,
, And D1, D2, ... Are sequentially connected. For each stage of the shift registers 41 to 44, the registers A1, B1, C1, D1, A2, B2,
C2, D2, ..., An-1, Bn-1, Cn-1, Dn
-1, An, Bn, Cn, and Dn are arranged in a nest. Each register is composed of a thin film transistor as a transfer gate, a charge storage capacitor, and the like.

That is, the clock CK from the input line 4b
1 (see (a) of FIG. 5) indicates each shift register 41-44.
Of the start pulse ST1 from the input line 4a is commonly input to the registers A1 and B of the first stage.
1, C1, D1 are supplied to the first-stage registers A1, B
The respective shift outputs of 1, C1, and D1 are supplied to the registers A2, B2, C2, and D2 of the second stage, ... And the registers An-1, Bn-1, Cn-1, and Dn- of the (n-1) th stage. 1
The respective shift outputs of are the n-th stage registers An and B.
n, Cn, Dn.

First-stage registers A1, B1, C1, D1
Each shift output of the thin film transistors SW1 to SW1
It is supplied to the source of SW4 and registers A2 and B of the second stage
The shift outputs of 2, C2 and D2 are respectively supplied to the sources of the thin film transistors SW5 to SW8, ..., And the registers An-1, Bn-1, Cn-1, Dn-1 of the (n-1) th stage.
Of each shift output of the thin film transistor SWN-
7 to SWN-4, and the shift outputs of the n-th stage registers An, Bn, Cn, and Dn are supplied to the sources of the thin film transistors SWN-3 to SWN, respectively.

The switching signals from the switching circuit 7 are input to the gates of the thin film transistors SW1 to SWN by the input lines 4c to 4c.
It is supplied via f and is turned on and off. The input line 4c includes thin film transistors SW1 and SW5,
Input line 4d connected to the gates of SW9, ..., SWN-3
Are thin film transistors SW2, SW6, SW10, ...
The input line 4e is connected to the gate of WN-2, the input line 4e is connected to the gates of the thin film transistors SW3, SW7, SW11, ... SWN-1, and the input line 4f is connected to the thin film transistor SW.
4, SW8, SW12, ... SWN are connected to the gates.

As a result, when the switching signal is supplied to the input line 4c, the thin film transistors SW1, SW5, SW9,
... When SWN-3 is turned on, registers A1 and A
When the shift outputs from 2, A3, ... An-1, An are guided to the subsequent stage and a switching signal is supplied to the input line 4d, the thin film transistors SW2, SW6, SW10, ... B1, B2, B3, ... n
-1, shift output from Bn is led to the subsequent stage, and input line 4
When a switching signal is supplied to e, the thin film transistor SW
When SW3, SW7, SW11, ... SWN-1 are turned on, shift outputs from the registers C1, C2, C3, ... Cn-1, Cn are guided to the subsequent stage, and a switching signal is supplied to the input line 4f. , Thin film transistors SW4, SW8, S
When W12, ... SWN are turned on, the register D
The shift outputs from 1, D2, D3, ... Dn-1, Dn are guided to the subsequent stage.

The shift outputs from the thin film transistors SW1 to SWN are supplied to the gates of the thin film transistors S1, ... SN, and the video signals from the video signal supply circuit 6 are supplied to their sources via the video input lines 4g to 4h. Supplied.

That is, the thin film transistors SW1 to SW
, 4 are commonly connected to the gates of thin film transistors S1, ... S4, the drains of thin film transistors SW5 to SW8 are commonly connected to the gates of thin film transistors S5, ... S8, ..., Thin film transistors SWN-7 to SWN.
The drain of N-4 is commonly used by thin film transistors SN-7-
Connected to the gate of SN-4, thin film transistor SWN
The drains of -3 to SWN are commonly used for the thin film transistor SN.
-3 to SN gates are connected. Video input line 4g
The video input line 4h is connected to the gates of the thin film transistors S1, S5, S9, ...
2, S6, S10, ... Connected to the gates of SN-2, the video input line 4i has thin film transistors S3, S7, S1.
Video input line 4j connected to the gate of SN-1
Are connected to the gates of the thin film transistors S4, S8, S12, ... SN.

As a result, when the thin film transistors S1, ... Are turned on, the analog video signal (Vsa1 ') from the video input line 4g is sequentially transferred to the capacitors CD1, CD5, CD.
The analog video signal (Vsa2 ') from the video input line 4h is sequentially held by the capacitors CD2 and C.
D6, CD10, ... CDN-2 are held, and analog video signals (Vsa3 ') from the video input line 4i are sequentially held by capacitors CD3, CD7, CD11, ... CDN-1, and analog video from the video input line 4j. Signal (Vsa4 ')
Are sequentially capacitors CD4, CD8, CD12, ... CDN
Held in.

The outputs of the sample hold circuits V1 to VN, that is, the holding voltages of the capacitors CD1 to CDN are supplied to Y1 to Y720 as the video signal lines 11 ,.

With this structure, when the switching signal of the input line 4c is turned on, the thin film transistors SW1 and SW1 are turned on.
5, SW9, ... SWN-3 are turned on so that the registers A1, A2, A3 ,.
Shift outputs from An-1 and An ((o) to Fig. 3)
(Q) and (b) to (e) in FIG. 5 are supplied to the gates of the thin film transistors S1, ... SN of the sample hold circuits V1 to VN. Thereby, the thin film transistor S
1, ... By turning on SN, the video signal supply circuit 6
From the video signal input lines 4g to 4h corresponding to the divided video signals (see (f) to (i) of FIG. 5) divided into four, the capacitor CD1 of each of the sample and hold circuits V1 to VN. , ... Charged to the CDN.

As a result, the liquid crystal display section 3 of the liquid crystal display section 3 is driven according to the charging voltage values of the sample and hold circuits V1 to VN in the video signal line driving circuit 4 and the scanning signal lines 12, ... Driven by the scanning signal line driving circuit 5. Drive is performed.

Further, when the switching signal of the input line 4d is turned on, the thin film transistors SW2, SW6, SW10, ... S.
When WN-2 is turned on, the shift outputs from the registers B1, B2, B3, ... Bn-1, Bn as the shift register 42 are supplied to the gates of the thin film transistors S1, ... SN of the sample hold circuits V1 to VN. It
As a result, the thin film transistors S1, ... SN are turned on, and the same operation is performed as when the switching signal of the input line 4c is turned on.

Further, when the switching signal of the input line 4e is turned on, the thin film transistors SW3, SW7, SW11, ... S.
When WN-1 is turned on, shift outputs from the registers C1, C2, C3, ... Cn-1, Cn as the shift register 43 are supplied to the gates of the thin film transistors S1 ,. It
As a result, the thin film transistors S1, ... SN are turned on, and the same operation is performed as when the switching signal of the input line 4c is turned on.

Further, when the switching signal of the input line 4f is turned on, the thin film transistors SW4, SW8, SW12, ... S.
When WN is turned on, the shift outputs from the registers D1, D2, D3, ... Dn-1, Dn as the shift register 44 are supplied to the gates of the thin film transistors S1, ... SN of the sample hold circuits V1 to VN. As a result, the thin film transistors S1, ... SN are turned on, and the same operation is performed as when the switching signal of the input line 4c is turned on.

Therefore, even if some of the four shift registers 41, ... Of the shift register unit 31 in the video signal line drive circuit 4 are partially damaged and inoperable, only one shift register can operate. If such a material remains, the active matrix type liquid crystal display device 1 can be completely operated.

As described above, according to this embodiment, the analog video signal (Vsa1 ') inputted from the video signal supply circuit 6 to the video input lines 4g, 4j of the video signal line drive circuit 4 is inputted.
In (-Vsa4 '), since the voltage changing timings are aligned, it is possible to simultaneously select the video input lines 4g, four video signal lines 11 corresponding to the number of ~ 4j ,. The number of stages of the shift register unit 31 can be reduced to 180 as compared with the number of 720 ...

Therefore, a plurality of shift registers can be formed in the video signal line drive circuit 4 so as to have redundancy and can be switched, and the yield of the video signal line drive circuit 4 becomes a problem. Active matrix type liquid crystal display device 1 in which a driving circuit is integrated
The yield of the shift register 41 can be improved, and the operation speed required for each shift register 41 of the shift register unit 31 can be reduced to 1/4 of the conventional operation speed. A sufficiently high operating speed can be ensured even if it is configured with elements. Further, the analog video signals (Vsa1 ') to (Vsa1') to (V
The time (T) during which sa4 ′) is supplied is ¼ times as long as that in the system in which the analog video signal (Vs) is not divided, so that sufficient time can be obtained for writing the potential.

Further, since the shift registers 41, ... Constituting the video signal line drive circuit 4 can be operated by the input of the start pulse ST1 and the clock CK1, an external circuit for inputting the start pulse ST1 and the clock CK1 is provided. Since the device can be downsized and the number of connecting wires can be further reduced, the device can be downsized and the manufacturing yield can be improved.

Further, since the video signal supply circuit 6 of this embodiment divides the analog video signal (Vs) in the form of a digital signal, there is almost no deterioration in image quality due to the division of the analog video signal (Vs). Absent. Therefore, according to this embodiment, a high quality display image can be obtained.

Further, the video signal line drive circuit and the scanning signal line drive circuit are formed on the same substrate as the array substrate on which the pixel electrodes and the like are formed, and the drive circuit unit and the display unit are integrated into a drive circuit integrated type. In the active matrix type liquid crystal display device, the yield of the drive circuit, which is a problem in such a drive circuit integrated type, can be dramatically improved.

That is, when the display section and the drive circuit section are originally produced separately, and the product for which good characteristics are obtained is assembled, the yields are independent. On the other hand, when the drive circuit unit and the display unit are integrally formed, the combination of the display unit and the drive circuit is determined from the beginning, and the overall yield is the probability that both non-defective products can be obtained at the same time. If the yield of the driving circuit is 100%, this is not a problem because it matches the yield of only the display portion, but the actual yield of the driving circuit is not 100%, which is a problem.

Here, the number of thin film transistors forming the driving circuit is compared with the number of thin film transistors in the display portion.
In the case of a driver circuit using a shift register, the number of thin film transistors included in the driver circuit is about 10% at most with respect to the display portion. Therefore, it can be considered that the yield of the liquid crystal display device integrated with the drive circuit is determined by the yield of the display section simply by comparing the numbers. However, in reality, the yield of the driving circuit cannot be ignored in consideration of the required performance and the influence when the thin film transistor is defective.

Although a part of the driving circuit is a digital circuit, when it is driven under a condition close to the limit speed, it rather affects the yield. In the display unit, when the operating current of the thin film transistor is small, the brightness of the pixel is affected. However, this is a problem only in the pixel having the defective thin film transistor, and is not likely to be a definite defect. On the other hand, when the operating current of the thin film transistor in the drive circuit decreases and the operating speed decreases, the drive circuit stops from that portion. This is a definite defect even if there is only one defective thin film transistor, and a display device having this defect has no commercial value. Therefore, the thin film transistor forming the driving circuit becomes more strict in yield.

Therefore, since the yield of the driving circuit actually becomes a problem, as described above, the shift register can be provided with redundancy and an effective shift register can be selected, and the redundancy does not complicate the structure. By doing so, the above problem is solved.

Next, an active matrix type liquid crystal display device according to another embodiment of the present invention will be described. This embodiment differs from the active matrix type liquid crystal display device 1 described above in the configuration of the video signal supply circuit 6, as shown in FIG.
Will be described with reference to.

The video signal supply circuit 6 of this embodiment divides the analog video signal (Vs) without digital conversion. The analog video signal (Vs) is input to the eight sample hold circuits 51a, ... 51h,
Outputs (SR2, 1) to (SR2, of the shift register 52)
Sequentially based on 8).

The shift register 52 is composed of 8 stages and has the same structure except that the number of stages is different from that of the above-mentioned embodiment, and is reset by the horizontal synchronizing signal (HS).
The operation is started in a state where only the output (SR2, 1) of the stage is turned on, and the operation is performed based on the horizontal sampling signal (CK2).

The output terminals of the sample and hold circuits 51a, ... Are connected to the changeover switch 53, and the sample and hold circuits 51e to 51h are selected while the sample and hold circuits 51a to 51d are selected by the shift register 52.
Are all turned on, and the sample hold circuits 51e to 51
During the period in which h is selected by the shift register 52, the 1/4 frequency divider 54 is controlled by the horizontal synchronizing signal (HS) and the horizontal sampling signal (CK2) so that the sample and hold circuits 51a to 51d are all turned on. To be selected.

In this way, the video signals (Vs1) to (Vs4) or (Vs5) to (Vs8) selected by the changeover switch 53 are the latch outputs of the latch circuits 25a, ... Of the above-mentioned embodiment. Similarly, the signals are aligned so that the phases, that is, the times at which the potential changes are the same.

The output selected by the change-over switch 53 is set to an appropriate voltage for driving the liquid crystal by the amplifying and inverting circuit 55 having the function of amplifying the voltage and inverting the polarity for each field, and then the external wiring 29a. Is supplied to the video input lines 4g to 4h via the -29d.

As described above, according to this embodiment, the input analog video signal (Vs) remains in the analog state.
Analog video signals (Vs1 ')-(V
s4 ') and is supplied to the video input lines 4g to 4j of the video signal line drive circuit 4 through the external wirings 29a to 29d.

As a result, since the video signal supply circuit 6 can be configured with a small-scale analog circuit as compared with the above-described embodiment, it is possible to further reduce the size and cost of the device.

In each of the above-described embodiments, a configuration is adopted in which four video signal lines 11, ... Are selected as one set at the same time, but the number of divisions of the video signal (Vs) is 2 for example. Video signal line 1 as divided or divided into 16
The number of simultaneous selections of 1, ... May be different from 2 or 16 as appropriate.

The present invention can also be implemented in various active matrix type display devices other than the above-mentioned active matrix type liquid crystal display device. Further, for example, as shown in FIG. 7, each stage of the shift register may be configured by four independent registers, and one of the registers may be connected to the next stage or the previous stage. With such a structure, for example, FIG.
When the register A2 in the second stage is defective, as shown in FIGS. 8 (b) and 8 (c), the connection of the next stage and the previous stage by the register A2 is cut off and the other register B
2, D2 (or the register C2) may be connected to the next stage or the previous stage. In this case, the changeover circuit 7 and the changeover switch unit 32 used in the above embodiment are unnecessary. Note that the disconnection of the connection with the next stage and the previous stage of the register (cutting of the fuse) and the connection with the next stage and the previous stage of the register (by dielectric breakdown) are performed by applying a predetermined voltage.

Alternatively, a bidirectional shift register may be used. In this case, the bidirectional shift register can be formed without complicating the wiring to the next stage. Further, this bidirectional shift register has redundancy because the circuits of each stage are independent in the scanning direction.

[0087]

As described above, according to the present invention, since the signals from the video signal supply circuit are simultaneously output to one set of video signal lines, they are sequentially output to the individual video signal lines. The circuit scale can be reduced as compared with the case of outputting, and the degree of freedom in pattern layout and the like can be increased.

Further, since the selection speed of the video signal line drive circuit can be slowed down by several times the division of the video signal supplied from the video signal supply circuit, the video signal line drive circuit can be operated with a circuit having a slow operation speed. Even if configured, the display device can operate at high speed. As a result, the matrix wiring portion and the video signal line drive circuit can be integrally formed on the same substrate, and the number of connection wirings can be reduced. Further, since the external circuit for inputting the start pulse and the clock to the video signal line drive circuit can also have a simple structure, the active matrix display device can be further downsized.

Further, the operating frequency is also the video signal (V
Since it is possible to make s) smaller than in the case where it is not divided, it is possible to improve the display performance.
Further, in the device integrated with the drive circuit, the shift register of the video signal line drive circuit can be provided with redundancy without making the structure complicated, and the yield can be dramatically improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an active matrix type liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of the video signal supply circuit of FIG.

3 is a diagram showing operation waveforms of the video signal supply circuit of FIG.

FIG. 4 is a schematic configuration diagram of the video signal line drive circuit of FIG.

5 is a diagram showing operation waveforms of the video signal line drive circuit of FIG.

FIG. 6 is a schematic configuration diagram for explaining another embodiment of the video signal supply circuit.

FIG. 7 is a schematic configuration diagram for explaining another embodiment of the video signal line drive circuit.

8 is a diagram showing a connection state of a second-stage shift register in the video signal line drive circuit of FIG.

FIG. 9 is a schematic configuration diagram for explaining a conventional video signal supply circuit.

10 is a diagram showing operation waveforms of the video signal supply circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Active matrix type liquid crystal display device 2 ... Insulating substrate 3 ... Liquid crystal display part 4 ... Video signal line drive circuit 4a-4l ... Input line 5 ... Scan signal line drive circuit 6 ... Video signal supply circuit 7 ... Switching circuit 11, ... video signal line 12, scan signal line 13, thin film transistor 21, shift register 22, AND circuit 23, analog / digital converter 24, first data latch section 25, second data latch section 27, digital / Analog conversion unit 28 ... Amplification / inversion unit 31 ... Shift register unit 32 ... Changeover switch unit 33 ... Sample hold unit 41 to 44 ... Shift register

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (8)

[Claims] 1. K × n video signal lines and m scan signal lines consisting of n sets of K lines arranged in a matrix as one set, and intersections of these video signal lines and the scan signal lines. In an active matrix type display device having a liquid crystal display section composed of a pixel electrode installed via a switching element arranged in the above, a video signal is sampled at a timing corresponding to one display pixel and distributed to K video signals. Video signal supply circuit including a distributing means and a timing control means for matching the timings of the distributed video signals and outputting to the K video input lines, and the K video input lines from the timing control means. And a video signal line drive circuit for simultaneously outputting a video signal output via the video signal line to a corresponding set of the above video signal lines. Scan type display device. 2. The active matrix display device according to claim 1, wherein the liquid crystal display section and the video signal line drive circuit are integrally formed on the same substrate. 3. The active matrix type display device according to claim 1, wherein the video signal line drive circuit includes an n-stage shift register. 4. The active matrix type display device according to claim 1, wherein the timing control means comprises two or more voltage holding means. 5. The active matrix type display according to claim 1, wherein the distributing means comprises K sampling means and K shift registers for determining a sampling period of the sampling means. apparatus. 6. K × n video signal lines and m scan signal lines consisting of n sets of K lines arranged in a matrix as one set and intersections of these video signal lines and the scan signal lines. Corresponding to n sets of the video signal lines, a liquid crystal display section including a pixel electrode disposed via a switching element disposed in the above, a scanning signal line drive circuit that sequentially transfers scanning signals to the scanning signal lines. A video signal line drive circuit that has a plurality of n-stage shift registers and sequentially transfers a video signal to the video signal line, and one of the plurality of shift registers of the video signal line drive circuit according to a selection signal from the outside. An active matrix type display device characterized in that a changeover switch to be selected is integrally formed on the same substrate. 7. The active matrix type display device according to claim 6, wherein the plurality of n-stage shift registers are arranged alternately for each stage. 8. K × n video signal lines and m scanning signal lines consisting of n sets of K lines arranged in a matrix as one set, and intersection points of these video signal lines and scanning signal lines. , A liquid crystal display section composed of pixel electrodes installed via switching elements, a scanning signal line drive circuit for sequentially transferring scanning signals to the scanning signal lines, and a video signal for sequentially transferring to the video signal lines. In the active matrix type display device in which the video signal line drive circuit is integrally formed on the same substrate, the video signal line drive circuit has an n-stage shift register corresponding to n sets of the video signal lines. However, an active matrix display having a plurality of registers for each stage of the shift register, and one register is arbitrarily selected for each stage of the shift register. Location.